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WO2009001652A1 - タイミング発生回路および位相シフト回路 - Google Patents

タイミング発生回路および位相シフト回路 Download PDF

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Publication number
WO2009001652A1
WO2009001652A1 PCT/JP2008/060085 JP2008060085W WO2009001652A1 WO 2009001652 A1 WO2009001652 A1 WO 2009001652A1 JP 2008060085 W JP2008060085 W JP 2008060085W WO 2009001652 A1 WO2009001652 A1 WO 2009001652A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
phase shift
signal
timing
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/060085
Other languages
English (en)
French (fr)
Inventor
Fujio Kurokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nagasaki University NUC
Original Assignee
Nagasaki University NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nagasaki University NUC filed Critical Nagasaki University NUC
Priority to EP08777071A priority Critical patent/EP2211463A1/en
Priority to KR1020097025327A priority patent/KR101119903B1/ko
Priority to JP2009520413A priority patent/JP5303761B2/ja
Priority to US12/665,396 priority patent/US8248131B2/en
Publication of WO2009001652A1 publication Critical patent/WO2009001652A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1502—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

パルスの立上がりエッジ、立下りエッジ等を、繰返し信号発生回路の周波数よりも細かいタイミングで生成できるタイミング発生回路およびこのタイミング発生回路に使用できる位相シフト回路を提供する。 　繰返し信号を入力する前記位相シフト回路は、繰返し信号に基づき、位相が所定量シフトした信号を出力し、前記位相シフトコントローラは、前記位相シフト回路が第１から第Ｍのどの位相の信号を出力するかを制御し、前記計数回路は、前記位相シフト回路の出力信号を所定数計数し、計数値がセットされた値に達したときに計数終了信号を発生することで、前記計数回路は、前記繰り返し信号のタイミングと、前記位相シフト回路によりシフトしたタイミングとの合成タイミングの信号を出力する。
PCT/JP2008/060085 2007-06-18 2008-06-01 タイミング発生回路および位相シフト回路 Ceased WO2009001652A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP08777071A EP2211463A1 (en) 2007-06-18 2008-06-01 Timing generation circuit and phase shift circuit
KR1020097025327A KR101119903B1 (ko) 2007-06-18 2008-06-01 타이밍 발생 회로
JP2009520413A JP5303761B2 (ja) 2007-06-18 2008-06-01 タイミング発生回路および位相シフト回路
US12/665,396 US8248131B2 (en) 2007-06-18 2008-06-01 Timing generating circuit and phase shift circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007159611 2007-06-18
JP2007-159611 2007-06-18
JP2007-200249 2007-08-01
JP2007200249 2007-08-01

Publications (1)

Publication Number Publication Date
WO2009001652A1 true WO2009001652A1 (ja) 2008-12-31

Family

ID=40185474

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060085 Ceased WO2009001652A1 (ja) 2007-06-18 2008-06-01 タイミング発生回路および位相シフト回路

Country Status (5)

Country Link
US (1) US8248131B2 (ja)
EP (1) EP2211463A1 (ja)
JP (1) JP5303761B2 (ja)
KR (1) KR101119903B1 (ja)
WO (1) WO2009001652A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8982099B2 (en) 2009-06-25 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Touch panel and driving method of the same
JP2012060606A (ja) * 2010-09-13 2012-03-22 Toshiba Corp 半導体集積回路および無線通信装置
US9584105B1 (en) * 2016-03-10 2017-02-28 Analog Devices, Inc. Timing generator for generating high resolution pulses having arbitrary widths
US10255960B2 (en) 2016-09-13 2019-04-09 Toshiba Memory Corporation Write pulse generator in a resistive memory
JP7183018B2 (ja) * 2018-12-11 2022-12-05 株式会社小糸製作所 点灯回路および車両用灯具

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186682A (ja) * 1995-12-28 1997-07-15 Nec Eng Ltd クロック信号調整回路
JP2003202936A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体集積回路

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423364A (en) * 1977-07-22 1979-02-21 Hitachi Ltd Waveform generating circuit
JPS5815323A (ja) * 1981-07-21 1983-01-28 Yokogawa Hewlett Packard Ltd 位相シフト回路
JPH01161912A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体集積回路
JPH0613857A (ja) * 1992-06-25 1994-01-21 Fujitsu Ltd ディレイ調整回路
JPH06177722A (ja) * 1992-11-30 1994-06-24 Yokogawa Hewlett Packard Ltd 広範囲遅延生成回路
JPH0837453A (ja) * 1994-07-22 1996-02-06 Advantest Corp プログラマブル遅延回路
JP3378667B2 (ja) * 1994-08-10 2003-02-17 株式会社アドバンテスト 周期クロックの可変遅延回路
JPH10285003A (ja) * 1997-04-04 1998-10-23 Nippon Samusun Kk 遅延回路及びこれを利用したキャラクタ生成回路
JP4105831B2 (ja) * 1998-09-11 2008-06-25 株式会社アドバンテスト 波形発生装置、半導体試験装置、および半導体デバイス
JP4286375B2 (ja) * 1999-04-02 2009-06-24 株式会社アドバンテスト 遅延クロック生成装置および遅延時間測定装置
US6501311B2 (en) * 2000-01-24 2002-12-31 Broadcom Corporation System and method for compensating for supply voltage induced signal delay mismatches
JP3895520B2 (ja) * 2000-05-29 2007-03-22 富士通株式会社 クロック変調装置
JP2002076858A (ja) * 2000-08-29 2002-03-15 Sanyo Electric Co Ltd タイミング信号生成回路
JP2002108493A (ja) * 2000-09-29 2002-04-10 Fujitsu General Ltd クロック位相シフト回路
JP4810738B2 (ja) * 2001-03-14 2011-11-09 株式会社デンソー シフトクロック発生装置
US7282973B1 (en) * 2005-12-07 2007-10-16 Altera Corporation Enhanced DLL phase output scheme
JP2008236273A (ja) * 2007-03-20 2008-10-02 Nec Corp 自動遅延制御回路およびその回路を用いたメモリインタフェース制御回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186682A (ja) * 1995-12-28 1997-07-15 Nec Eng Ltd クロック信号調整回路
JP2003202936A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体集積回路

Also Published As

Publication number Publication date
KR20100020953A (ko) 2010-02-23
KR101119903B1 (ko) 2012-03-13
JPWO2009001652A1 (ja) 2010-08-26
EP2211463A1 (en) 2010-07-28
US8248131B2 (en) 2012-08-21
JP5303761B2 (ja) 2013-10-02
US20100253408A1 (en) 2010-10-07

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