WO2009096326A1 - Ceramic multilayer substrate manufacturing method, and ceramic multilayer substrate - Google Patents
Ceramic multilayer substrate manufacturing method, and ceramic multilayer substrate Download PDFInfo
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- WO2009096326A1 WO2009096326A1 PCT/JP2009/051045 JP2009051045W WO2009096326A1 WO 2009096326 A1 WO2009096326 A1 WO 2009096326A1 JP 2009051045 W JP2009051045 W JP 2009051045W WO 2009096326 A1 WO2009096326 A1 WO 2009096326A1
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- ceramic
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- multilayer substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
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- H10W70/63—
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- H10W90/724—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a method for manufacturing a ceramic multilayer substrate and a ceramic multilayer substrate, and more particularly to a method for manufacturing a ceramic multilayer substrate incorporating a chip-type ceramic electronic component and a ceramic multilayer substrate.
- An electronic component built-in multilayer ceramic substrate described in Patent Document 1 includes a multilayer ceramic substrate, a chip-type ceramic electronic component housed in a space formed by a recess or a through hole in the multilayer ceramic substrate, and a multilayer ceramic substrate. It is provided with the conductor which has wired the above-mentioned chip type electronic component provided in the interlayer or space. Thus, since the chip-type electronic component is accommodated in the space in the multilayer ceramic substrate, a multilayer ceramic substrate having a desired shape can be obtained without deteriorating the flatness.
- the unsintered composite laminate includes a base green layer, a constraining layer containing a hardly sinterable material, and a wiring conductor. When fired, the base green layer is formed by the action of the constraining layer. Shrinkage in the main surface direction is suppressed.
- the unsintered composite laminate can be fired without any problems in a state in which the functional element is incorporated, and the components are mutually exchanged between the functional element and the green layer for the substrate. Diffusion does not occur and the characteristics of the functional element are maintained after firing.
- a multilayer ceramic substrate is obtained by firing a multilayer body of ceramic green sheets incorporating chip-type ceramic electronic components. Cracks were generated in the chip-type ceramic electronic component built in the multilayer ceramic substrate, and in some cases, the chip-type ceramic electronic component was even destroyed. This phenomenon was also observed in the non-shrinkage method using a constrained layer.
- these multilayer ceramic substrates are fired in a state where the chip-type electronic component and the ceramic green sheet are in close contact, it is difficult to prevent mutual diffusion of material components between the chip-type electronic component and the ceramic layer. Even with the technique described in Patent Document 2, the characteristics of the chip-type electronic component may be deteriorated.
- Patent Document 1 in the case of a multilayer ceramic substrate in which a recess or a through hole for accommodating a chip-type electronic component is formed in the cavity, the problem is that the substrate strength is significantly reduced at the cavity portion. There was also.
- the present invention has been made in order to solve the above-described problems, and is a highly reliable ceramic multilayer in which chip-type ceramic electronic components are not damaged such as cracks and the characteristics of chip-type ceramic electronic components are not deteriorated. It is an object of the present invention to provide a substrate manufacturing method and a ceramic multilayer substrate.
- chip-type ceramic electronic components built in the ceramic multilayer substrate As a result of various studies on the cause of damage to chip-type ceramic electronic components built in the ceramic multilayer substrate, the present inventor has obtained the following knowledge. That is, it has been found that when the thermal expansion coefficients of the ceramic layer of the ceramic multilayer substrate and the chip-type ceramic electronic component are greatly different, the chip-type ceramic electronic component is cracked or damaged. If shrinkage in the surface direction of the substrate is suppressed by adopting a non-shrinkage construction method, a chip-type ceramic electronic component that does not shrink can be incorporated.
- chip-type ceramic electronic components such as multilayer capacitors are often made of a high dielectric constant material, and the high dielectric constant material generally has a large thermal expansion coefficient.
- the material of the ceramic green layer serving as the ceramic layer is often composed of a low dielectric constant material, and the low dielectric constant material generally has a small thermal expansion coefficient.
- the chip-type ceramic electronic component shrinks more than the ceramic layer during cooling, and the chip-type ceramic electronic component from the ceramic layer Pulling force works against.
- the chip-type ceramic electronic component is formed of a ceramic material.
- the ceramic material is weak against tensile stress, the tensile force from the ceramic layer causes cracking or breakage.
- the constituent material of the chip-type ceramic electronic component incorporated in the ceramic multilayer substrate is limited. In other words, if the chip-type ceramic electronic component and the ceramic layer are not in close contact with each other, it is possible to eliminate the disadvantage that the chip-type ceramic electronic component is damaged or that the constituent material of the chip-type ceramic electronic component is limited. .
- the method for producing a ceramic multilayer substrate according to the present invention includes a ceramic green laminate having a plurality of ceramic green layers laminated and having a conductor pattern, a ceramic sintered body, a terminal electrode, and an interior of the ceramic green laminate. And a ceramic ceramic substrate containing the chip-type ceramic electronic component by simultaneously firing the chip-type ceramic electronic component disposed at the same time and having the terminal electrode electrically connected to the conductor pattern.
- a second step of burning out the layer is a first step of forming an adhesion preventive agent layer at a portion of the ceramic green layer in contact with the chip-type ceramic electronic component.
- the method for producing a ceramic multilayer substrate of the present invention preferably includes a step of disposing the adhesion preventive agent layer on both surfaces of the chip-type ceramic electronic component.
- the adhesion preventing agent is a resin paste, and in the first step, the resin paste is applied onto the ceramic green layer.
- the adhesion preventing agent does not burn out in a low oxygen atmosphere, but includes a burned material burned out in a high oxygen atmosphere.
- the burnout material is composed of the burned material.
- the ceramic green laminate and the chip-type ceramic electronic component are fired in a low oxygen atmosphere, and then both are fired again in a high oxygen atmosphere. It is preferable to burn off the burnout material.
- the burnout material is preferably carbon.
- the method for producing a ceramic multilayer substrate of the present invention includes a step of forming a via hole at a position overlapping the terminal electrode of the chip-type ceramic electronic component of the adhesion preventive agent layer and filling the via hole with a conductive paste. Is preferred.
- the ceramic ceramic laminate with the constraining layer made of an inorganic material that is not sintered at the firing temperature of the ceramic green laminate is disposed on at least one main surface of the ceramic green laminate.
- the green laminate and the chip-type ceramic electronic component are preferably fired.
- the thermal expansion coefficient of the sintered body of the ceramic green laminate is substantially equal to the thermal expansion coefficient of the ceramic sintered body constituting the chip-type ceramic electronic component. preferable.
- the ceramic multilayer substrate of the present invention is provided at the interface between a ceramic laminate in which a plurality of ceramic layers are laminated and have a conductor pattern, and upper and lower ceramic layers, and is electrically connected to the ceramic sintered body and the conductor pattern.
- a ceramic multilayer substrate comprising a chip-type ceramic electronic component having a terminal electrode, wherein a gap exists at an interface between the ceramic layer and the chip-type ceramic electronic component, The terminal electrode and the conductor pattern are electrically connected by a protruding electrode formed in the gap.
- the protruding electrode is directly connected to a via-hole conductor formed in a ceramic layer in contact with the gap.
- the terminal electrodes of the chip-type ceramic electronic component are arranged apart from each other in the stacking direction of the ceramic layers.
- the protruding electrode is formed of a material having high ductility.
- the material having high ductility is silver.
- a highly reliable method for manufacturing a ceramic multilayer substrate and a ceramic multilayer substrate in which the chip-type ceramic electronic component is not damaged such as cracks and the characteristics of the chip-type ceramic electronic component are not deteriorated. can do.
- (A), (b) is a figure which shows one Embodiment of the ceramic multilayer substrate of this invention, respectively, (a) is sectional drawing which shows the whole, (b) is the part enclosed with (circle) of (a). It is sectional drawing shown. (A)-(e) is process drawing which shows the principal part of the method of manufacturing the ceramic multilayer substrate shown in FIG. 1, respectively. It is sectional drawing equivalent to (b) of FIG. 1 which shows other embodiment of the ceramic multilayer substrate of this invention. It is sectional drawing equivalent to FIG.1, (b) which shows other embodiment of the ceramic multilayer substrate of this invention.
- FIGS. 1A and 1B are diagrams showing an embodiment of the ceramic multilayer substrate of the present invention
- FIG. 1A is a sectional view showing the whole of the ceramic multilayer substrate
- FIG. 2 is an enlarged cross-sectional view
- FIGS. 2A to 2E are process diagrams showing the main part of the method for manufacturing the ceramic multilayer substrate shown in FIG. 1, and
- FIG. sectional view corresponding to FIG. 1 (b) shows another embodiment of the ceramic multilayer substrate of the invention, corresponding to (b) of FIG. 1
- FIG. 4 showing still another embodiment of the ceramic multilayer substrate of the present invention It is sectional drawing.
- a ceramic multilayer substrate 10 of the present embodiment includes, for example, as shown in FIG. 1A, a ceramic laminate 11 in which a plurality of ceramic layers 11A are laminated and have a conductor pattern 12, and upper and lower ceramics.
- a chip-type ceramic electronic component 13 which is provided at the interface of the layer 11A and has a ceramic sintered body 13A as a base body and terminal electrodes 13B at both ends thereof. Further, surface electrodes 14 and 14 are formed on both main surfaces (upper and lower surfaces) of the ceramic laminate 11, respectively.
- a plurality of surface mount components 20 are mounted on one main surface (upper surface in the present embodiment) of the ceramic laminate 11 via a surface electrode 14.
- active elements such as semiconductor elements and gallium arsenide semiconductor elements, passive elements such as capacitors, inductors, resistors, etc. are bonded via solder or conductive resin, or bonding wires such as Au, Al, and Cu.
- bonding wires such as Au, Al, and Cu.
- the chip-type ceramic electronic component 13 and the surface mount component 20 are electrically connected to each other via the surface electrode 14 and the internal conductor pattern 12.
- the ceramic multilayer substrate 10 can be mounted on a mounting substrate such as a mother board via the surface electrode 14 on the other main surface (lower surface in the present embodiment).
- a gap V exists at the interface between the upper and lower ceramic layers 11A and 11A and the chip-type ceramic electronic component 13, and the entire surface (6 Surface) is opposed to the inner surfaces of the upper and lower ceramic layers 11A and 11A through the gap V.
- a conductor pattern 12 is formed on the upper ceramic layer 11A.
- the conductor pattern 12 includes a surface electrode 12A formed in a predetermined pattern on the surface of the upper ceramic layer 11A, and a via-hole conductor 12B formed vertically through the upper ceramic layer 11A from the surface electrode 12A, And a protruding electrode 12C that protrudes from the via-hole conductor 12B into the gap V and is electrically connected to the terminal electrode 13B of the chip-type ceramic electronic component 13.
- the protruding electrode 12C is formed integrally with the via hole conductor 12B, for example, and electrically connects the via hole conductor 12B and the terminal electrode 13B of the chip-type ceramic electronic component 13 to each other. Accordingly, the chip-type ceramic electronic component 13 is suspended by the protruding electrode 12C in the space formed between the upper and lower ceramic layers 11A and 11A.
- the material of the ceramic layer 11A constituting the ceramic laminate 11 is not particularly limited as long as it is a ceramic material.
- a low temperature co-fired ceramic (LTCC) material is preferable.
- the low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C. or less and can be simultaneously fired with Ag, Cu, or the like having a small specific resistance.
- Specific examples of the low-temperature sintered ceramic include a glass composite LTCC material obtained by mixing borosilicate glass with ceramic powder such as alumina and forsterite, and ZnO—MgO—Al 2 O 3 —SiO 2 crystal.
- Non-glass using crystallized glass-based LTCC material using a crystallized glass BaO—Al 2 O 3 —SiO 2 ceramic powder, Al 2 O 3 —CaO—SiO 2 —MgO—B 2 O 3 ceramic powder, etc.
- System LTCC materials and the like
- a low melting point metal having a low resistance and a low melting point such as Ag or Cu can be used as the conductor pattern 12.
- the ceramic laminate 11 and the conductor pattern 12 can be simultaneously fired at a low temperature of 1050 ° C. or lower.
- the protruding electrode 12C connected to the via-hole conductor 12B suspends the chip-type ceramic electronic component 13 in the ceramic laminate 11, and therefore absorbs the thermal expansion difference between the ceramic layer 11A and the chip-type ceramic electronic component 13. It is preferable that it is formed of Ag having high ductility so as to obtain.
- a high temperature sintered ceramic (HTCC) material can be used as the ceramic material.
- the high-temperature sintered ceramic material include alumina, aluminum nitride, mullite, and other materials added with a sintering aid such as glass and sintered at 1100 ° C. or higher.
- a metal selected from molybdenum, platinum, palladium, tungsten, nickel, and alloys thereof is used as the conductor pattern 12.
- the chip-type ceramic electronic component 13 is not particularly limited.
- a ceramic sintered body 13A such as barium titanate or ferrite, which is fired at 1050 ° C. or higher, and further 1200 ° C. or higher, is used, for example, FIG.
- chip-type ceramic electronic components such as an inductor, a filter, a balun, and a coupler can be used.
- One or a plurality of these chip-type ceramic electronic components 13 can be appropriately selected according to the purpose and arranged in the ceramic laminate 11.
- the terminal electrode 13B of the chip-type ceramic electronic component 13 used for the ceramic multilayer substrate 10 is a conductive paste applied and baked, the conductive paste is applied and dried before baking. It may be a thing.
- the gap V is interposed at the interface between the chip-type ceramic electronic component 13 and the ceramic laminate 11, even if a stress such as a thermal stress acts on the ceramic laminate 11 in the plane direction, the stress is reduced to the chip-type. It is not directly transmitted to the ceramic electronic component 13, but is absorbed by the protruding electrodes 12C, and the chip-type ceramic electronic component 13 is not cracked or damaged.
- the thermal expansion coefficient of the ceramic laminate 11 and the thermal expansion coefficient of the ceramic sintered body 13A of the chip-type ceramic electronic component 13 substantially the same, the thermal stress applied to the protruding electrode 12C can be reduced, Even if the projecting electrode 12C has poor ductility, it is possible to prevent a large load from being applied to the projecting electrode 12C.
- the chip-type ceramic electronic component 13 has upper and lower ceramic layers 11A, A plurality of them may be arranged side by side at any location on the interface of 11A, or may be arranged in a plurality of stages on a plurality of different upper and lower interfaces. Therefore, the plurality of chip-type ceramic electronic components 13 are electrically connected to each other in series and / or in parallel via the conductor pattern 12 according to the purpose, so that the ceramic multilayer substrate 10 has multiple functions and high performance. be able to.
- the non-shrinkage construction method refers to a construction method in which the shrinkage in the planar direction of the ceramic laminate is suppressed or prevented before and after the firing of the ceramic laminate, and the dimensions in the planar direction are not substantially changed.
- a required number of ceramic green sheets 111A are produced using a slurry containing a low-temperature sintered ceramic material as shown in FIG.
- the two ceramic green sheets 111A are defined as a first ceramic green sheet 111A and a second ceramic green sheet 111A ', respectively. Since the ceramic green sheet becomes a ceramic green layer in the ceramic green laminate, the ceramic green layer composed of the first and second ceramic green sheets 111A and 111A ′ is also denoted by the same reference numerals as the ceramic green sheet. To do.
- an adhesion preventing agent made of a paste containing a burned-out material as a main component as shown in FIG. 2A is applied to the upper surfaces of the first and second ceramic green sheets 111A and 111A ′.
- the adhesion preventing agent layer 114 is formed by printing.
- the adhesion preventive agent prevents mutual diffusion of material components between the chip-type ceramic electronic component 13 and the first and second ceramic green sheets 111A and 111A ′ during firing, and is burned out after firing and the upper and lower ceramics.
- a material that forms the void V at the interface between the layers 11A and 11A and the chip-type ceramic electronic component 13 is used.
- the adhesion inhibitor is not particularly limited as long as it has the above function.
- a burned-out material such as resin or carbon can be used.
- the first ceramic green sheet 111A and the adhesion are formed as shown in FIG.
- the conductive paste containing Ag as a main component is screen-printed on the first ceramic green sheet 111A from the surface opposite to the adhesion preventive agent layer 114.
- the via hole of one ceramic green sheet 111A is filled with a conductive paste to form the via hole conductor portion 112B and the surface electrode portion 112A.
- the protruding electrode portion 112C is integrally formed with the via-hole conductor portion 112B in the through hole of the adhesion preventing agent layer 114.
- These via-hole conductor portions 112B and protruding electrode portions 112C are formed corresponding to the pair of terminal electrodes 13B of the chip-type ceramic electronic component 13 (see FIG. 2C).
- the second ceramic green sheet 111A ′ is disposed with the adhesion preventing agent layer 114 facing upward, and the adhesion preventing agent layer 114 of the second ceramic green sheet 111A ′ is disposed.
- the first ceramic green sheet 111A is disposed above them with the adhesion preventing agent layer 114 facing downward.
- the chip-type ceramic electronic component 113 is fixed to a predetermined portion of the adhesion preventing agent layer 114 of the second ceramic green sheet 111A ′ with an adhesive.
- the chip-type ceramic electronic component 113 and the first ceramic green sheet 111A are stacked on the second ceramic green sheet 111A ′ and bonded to each other, and then the ceramic green laminate including the chip-type ceramic electronic component 113. 111 is formed.
- the chip-type ceramic electronic component before being built in the ceramic multilayer substrate 10 will be described with reference numeral “113”.
- the first and second ceramic green sheets 111A and 111A ′ are pressure-bonded, the first and second ceramic green sheets 111A and 111A ′ are laminated as ceramic green layers 111A and 111A ′ as shown in FIG.
- the ceramic green multilayer body 111 is formed, and the chip-type ceramic electronic component 113 is encased in the adhesion preventing agent layer 114 in the ceramic green multilayer body 111.
- the constraining layers 115 are disposed on both upper and lower surfaces of the ceramic clean laminate 111, and the ceramic green laminate 111 is sandwiched between the upper and lower constraining layers 115, followed by thermocompression bonding at a predetermined temperature and pressure.
- a pressure-bonded body 110 shown in d) is obtained.
- the constraining layer 115 as shown in the figure from a hardly sinterable powder that does not sinter at the sintering temperature of the ceramic green laminate 111, for example, a slurry containing Al 2 O 3 as a main component and an organic binder as a sub component. The one formed in a sheet shape is used.
- the firing conditions are different between the case where the adhesion preventing agent layer 114 is formed of a resin paste and the case of being formed of a carbon paste.
- the adhesion preventing agent layer 114 is formed of a resin paste
- the adhesion preventing agent layer 114 is completely burned by firing the pressure-bonded body 110 shown in FIG. Thereafter, the constraining layer 115 is removed to obtain the ceramic multilayer substrate 10 shown in FIG.
- the adhesion preventing agent layer 114 is formed of a carbon paste
- a low oxygen atmosphere having a lower oxygen partial pressure than the atmosphere in which the carbon is not burned down in the crimped body 110 shown in FIG. For example, when the oxygen partial pressure is set to 10 ⁇ 3 to 10 ⁇ 6 atm) and calcined at 870 ° C., then adjusted to a high oxygen atmosphere (for example, air with a high oxygen partial pressure) to 900 ° C. Then, the adhesion preventive agent layer 114 made of carbon paste is completely burned off by firing again to obtain the ceramic multilayer substrate 10 shown in FIG.
- the carbon of the adhesion prevention layer 114 remains without being burned out and maintains its occupied space, and a high oxygen atmosphere When refired, the carbon burns completely and burns out.
- the firing temperature is preferably a temperature at which the low-temperature sintered ceramic material is sintered, for example, in the range of 800 to 1050 ° C. If the firing temperature is less than 800 ° C., the ceramic component of the ceramic green laminate 111 may not be sufficiently sintered, and if it exceeds 1050 ° C., the metal particles such as the surface electrode 12A may melt and diffuse into the ceramic green layer 11. There is.
- the adhesion preventive agent layer 114 enclosing the chip-type ceramic electronic component 113 is burned off when the ceramic green laminate 111 is fired, and as shown in FIG. A narrow gap V is formed at the interface between the ceramic laminate 11 and the projecting electrode 12C that electrically connects the via-hole conductor 12B and the terminal electrode 13B. At this time, even if the difference between the thermal expansion coefficient of the ceramic laminate 11 and the thermal expansion coefficient of the chip-type ceramic electronic component 13 is large, the gap V is interposed between the ceramic laminate 11 and the chip-type ceramic electronic component 13.
- the chip-type ceramic electronic component 13 Since the chip-type ceramic electronic component 13 is connected to the via-hole conductor 12B of the ceramic multilayer body 11 only by the protruding electrode 12C, it is caused by the difference in thermal expansion coefficient between the ceramic multilayer body 11 and the chip-type ceramic electronic component 13.
- the thermal stress is absorbed by the protruding electrode 12C formed of Ag having high ductility, and the thermal stress acting directly on the chip-type ceramic electronic component 13 is relieved, so that the chip-type ceramic electronic component 13 is cracked, or the chip The mold ceramic electronic component 13 is not damaged.
- the void V is formed at the interface between the ceramic laminate 11 and the chip-type ceramic electronic component 13 when the ceramic green laminate 111 is sintered, the ceramic sintering of the ceramic laminate 11 and the chip-type ceramic electronic component 13 is performed. Interdiffusion of material components with the body 13A can be reliably prevented, and characteristic deterioration of the chip-type ceramic electronic component 13 after firing can be prevented.
- the protruding electrode portion 12C and the terminal electrode 13B of the chip-type ceramic electronic component 13 are integrated by the respective metal particles growing and sintering, and these 12C and 13B are firmly connected.
- the ceramic multilayer substrate 10 can be obtained by removing the upper and lower constraining layers 115 by blasting or ultrasonic cleaning.
- the ceramic green laminated body 111 in which the plurality of ceramic green layers 111A are laminated and has the conductor pattern portion 112, the ceramic sintered body 113A, the terminal electrode 113B, and the ceramic green A ceramic containing the chip-type ceramic electronic component 13 by simultaneously firing the chip-type ceramic electronic component 113 which is disposed inside the multilayer body 111 and in which the terminal electrode 113B is electrically connected to the conductor pattern portion 112.
- thermal stress acts on the chip-type ceramic electronic component 13 from the ceramic laminate 11 due to the difference in thermal expansion coefficient between the thermal expansion coefficient of the ceramic laminate 11 and the chip-type ceramic electronic component 13 during firing.
- the chip-type ceramic electronic component 13 Since this thermal stress is absorbed by the protruding electrode 12C and the thermal stress is relaxed and is not easily transmitted to the chip-type ceramic electronic component 13, the chip-type ceramic electronic component 13 is cracked or the chip-type ceramic electronic component 13 is damaged. There is nothing. Further, the void V formed at the interface between the ceramic layer 11A and the chip-type ceramic electronic component 13 during firing can reliably prevent mutual diffusion of material components between the ceramic laminate 11 and the ceramic sintered body 13A. In addition, it is possible to prevent deterioration of the characteristics of the chip-type ceramic electronic component 13 built in the ceramic multilayer substrate 10.
- the adhesion preventing agent layer 114 since the adhesion preventing agent layer 114 is formed on the ceramic green sheet 111A, the adhesion preventing agent layer 114 can be formed in the same printing process as the surface electrode portion 112A. The adhesion preventing agent layer 114 can be formed without introducing a special process or apparatus for 114. Further, since the adhesion preventive agent layers 114 are arranged on both surfaces of the chip-type ceramic electronic component 13, a void V is formed surrounding the entire surface of the chip-type ceramic electronic component 13, and the chip-type ceramic electronic component 13 is ceramic laminated only by the protruding electrode 12C. Since it is connected to the via-hole conductor 12B of the body 11, the ceramic multilayer substrate 10 having a structure resistant to thermal stress can be obtained.
- the adhesion preventing agent layer 114 is formed using a resin that burns out at a temperature lower than the firing temperature as the burned material, the voids V can be more reliably formed during firing.
- carbon is used as the burned-out material, the carbon remains when firing in a low-oxygen atmosphere to suppress the shrinkage of the ceramic green sheets 111A and 111A ′, thereby reliably ensuring a space to be a void V, The desired voids V can be reliably formed by completely burning and burning carbon in an oxygen atmosphere.
- the ceramic layer 11A is a low-temperature sintered ceramic layer, a low-resistance and inexpensive metal such as Ag can be used as the conductor pattern 12, which reduces manufacturing costs and has high frequency characteristics. It can contribute to improvement. Furthermore, since the ceramic multilayer substrate 10 is manufactured by a non-shrinkage method, there is almost no shrinkage in the plane direction. Therefore, the thermal stress acting on the chip-type ceramic electronic component 13 during firing can be remarkably reduced, and damage to the chip-type ceramic electronic component 13 can be more reliably prevented.
- a ceramic multilayer substrate 10A of the present embodiment is configured according to the first embodiment except that the type of chip-type ceramic electronic component 13 is different as shown in FIG. Therefore, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals and the characteristic parts of this embodiment will be described.
- the chip-type ceramic electronic component 13 in the present embodiment includes a ceramic sintered body 13A and a pair of terminal electrodes 13B formed on both upper and lower surfaces of the ceramic sintered body 13A. .
- the pair of terminal electrodes 13B are arranged apart from each other in the stacking direction (vertical direction) of the ceramic layer 11A, and the ceramic sintered body 13A is sandwiched from above and below by these terminal electrodes 13B.
- the upper and lower terminal electrodes 13B are electrically connected to via-hole conductors 12B formed through the upper and lower ceramic layers 11A via projecting electrodes 12C formed in the gaps V at the respective central portions.
- the upper and lower via-hole conductors 12B are electrically connected to the surface electrode 12A formed on the surface of each ceramic layer 11A.
- the upper and lower terminal electrodes 13B are each connected to one via-hole conductor 12B via a protruding electrode 12C.
- a plurality of protruding electrodes may be connected to a plurality of via-hole conductors. You may connect to a terminal electrode.
- the ceramic multilayer substrate 10A of the present embodiment is configured in accordance with the ceramic multilayer substrate 10 of the first embodiment except that the structure of the terminal electrode 13B of the chip-type ceramic electronic component 13 is different. It can be manufactured according to the ceramic multilayer substrate 10 of the embodiment, and the same effect as the ceramic multilayer substrate 10 can be expected.
- the ceramic multilayer substrate 10 ⁇ / b> B of the present embodiment is configured according to the first embodiment except that the form of the conductor pattern 12 is different. Therefore, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals and the characteristic parts of this embodiment will be described.
- the chip-type ceramic electronic component 13 in the present embodiment is configured substantially the same as the chip-type ceramic electronic component 13 in the first embodiment.
- the conductor pattern 12 is formed only on the upper ceramic layer 11A of the chip-type ceramic electronic component 13.
- the conductor pattern 12 is also formed on the lower ceramic layer 11A.
- the conductor patterns 12 formed on the upper and lower ceramic layers 11A are formed vertically symmetrical. Therefore, only the conductor pattern 12 of the upper ceramic layer 11A will be described.
- the conductor pattern 12 is a surface formed on the upper ceramic layer 11A facing the terminal electrode 13B of the chip-type ceramic electronic component 13 and the via-hole conductor 12B that vertically penetrates the upper ceramic layer 11A. It has an inner conductor 12D and a protruding electrode 12C that electrically connects the in-plane conductor 12D and the terminal electrode 13B.
- the conductor pattern 12 is formed corresponding to the left and right terminal electrodes 13B.
- the left and right protruding electrodes 12 ⁇ / b> C are each formed in a gap V formed at the interface between the ceramic laminate 11 and the chip-type ceramic electronic component 13.
- the protruding electrode 12C can form a protruding electrode portion by providing a through hole in a previously formed adhesion preventing agent layer (not shown) and filling the through hole with a conductive paste by screen printing.
- the in-plane conductor 12D can be directly formed on a ceramic green sheet (not shown) by screen printing.
- the conductor pattern 12 is formed on the lower ceramic layer 11A corresponding to the left and right terminal electrodes 13B of the chip-type ceramic electronic component 13 so as to be vertically symmetrical.
- the ceramic multilayer substrate 10B shown in FIG. 4 does not have a surface electrode, it goes without saying that a surface electrode may be provided if necessary.
- the ceramic multilayer substrate 10B of this embodiment can also be manufactured according to the ceramic multilayer substrate 20 of the first and second embodiments, and the same effect as the ceramic multilayer substrate 10 can be expected.
- Example 1 a ceramic multilayer substrate was prepared according to the procedure shown in FIGS. That is, the adhesion preventing layer was formed by screen printing the resin paste on the two first and second ceramic green sheets. Further, a via hole that also penetrates the adhesion preventive agent layer is formed on the first ceramic green sheet using a puncher, and then a conductive paste mainly composed of Ag is filled in the via hole to form a via hole conductor portion. And the surface electrode part was formed in the surface on the opposite side to an adhesion inhibitor layer.
- 100 multilayer capacitors are built in the ceramic green multilayer body. It was. A constraining layer was thermocompression bonded to the upper and lower surfaces of the ceramic green laminate to obtain a pressed body. After firing this pressure-bonded body at 900 ° C., the constraining layer was removed to obtain a ceramic multilayer substrate.
- the multilayer capacitor used had a size of 0402 and a capacitance of 10 ⁇ F.
- the thermal expansion coefficient of the ceramic multilayer body was 6 ppm / ° C., and the thermal expansion coefficient of the multilayer capacitor was 11 ppm / ° C.
- a ceramic green laminate without an adhesion prevention layer was prepared, and this ceramic green laminate was sandwiched between constraining layers and thermocompression bonded, and then fired in the same manner as in the examples to produce a comparative ceramic multilayer substrate. Obtained.
- the adhesion preventing layer is burned out by firing, and a gap is formed at the interface between the ceramic multilayer body and the multilayer capacitor, and the ceramic multilayer body and the multilayer capacitor are connected only by protruding electrodes. Even if the difference in thermal expansion coefficient between the capacitor and the multilayer capacitor is as large as 5 ppm / ° C, the projecting electrode having high ductility can cause thermal stress due to the difference in thermal expansion coefficient between the thermal expansion coefficient of the ceramic multilayer body and that of the multilayer capacitor.
- the multilayer capacitor could be built in the ceramic multilayer body without any cracks in the multilayer capacitor.
- Example 2 In this example, a chip coil (10 ⁇ H) is used instead of the multilayer capacitor used in Example 1, and the chip coil is built in the same manner as in Example 1, and there is a gap at the interface between the ceramic laminate and the chip coil.
- a ceramic multilayer substrate was produced.
- the thermal expansion coefficient of the ceramic multilayer body of this ceramic multilayer substrate was 10 ppm / ° C.
- the thermal expansion coefficient of the chip coil was 10.2 ppm / ° C.
- a ceramic multilayer substrate having a chip coil without voids was fabricated.
- the comparative ceramic multilayer substrate without voids has a large size in the chip coil during firing. It is considered that the characteristics of the chip coil using the ferrite having a large characteristic fluctuation with respect to the compressive stress greatly deteriorated due to the compressive stress. Since shrinkage in the thickness direction cannot be suppressed even by the non-shrinkage method that suppresses shrinkage in the planar direction, it is not possible to prevent compressive stress from acting on the chip coil in the comparative ceramic multilayer substrate without voids. For this reason, conventionally, a chip coil that is weak against compressive stress cannot be incorporated in the ceramic laminate as it is.
- the ceramic multilayer substrate of this example since a void is formed at the interface between the ceramic laminate and the chip coil by firing, even if shrinkage stress in the thickness direction acts on the ceramic laminate during firing, the ceramic multilayer substrate Compressive stress does not directly act on the chip coil due to the gap between the laminated body and the chip coil, and fluctuations in the characteristics of the chip coil can be suppressed. Therefore, even a chip coil that has not been incorporated in the ceramic multilayer substrate can be incorporated in the ceramic multilayer substrate in the same manner as the multilayer capacitor.
- Example 3 the ceramic multilayer substrate shown in FIG. 3 incorporating the chip-type ceramic electronic component having the terminal electrodes arranged vertically apart from each other in the thickness direction of the chip-type ceramic electronic component, that is, the stacking direction of the ceramic laminate. Produced.
- thermal stress is generated between the upper and lower terminal electrodes, but since the dimension between the terminal electrodes is small, the difference in thermal expansion between the terminal electrodes is small, and the chip-type ceramic electronic component is cracked. And chip-type ceramic electronic components are not damaged.
- the present invention is not limited to the above-described embodiments, and is included in the present invention unless it is contrary to the gist of the present invention.
- the case where the ceramic multilayer substrate is manufactured by the non-shrinking method has been described. It is only necessary to include a step of forming voids at the interface, and the present invention is not limited to the non-shrinkage method, and manufacturing methods other than the non-shrinkage method are also included in the present invention. In this case, it is necessary to appropriately adjust the size of the adhesion preventing agent layer according to the shrinkage difference between the ceramic green layer and the adhesion preventing agent layer.
- the adhesion preventive agent layer is formed of a resin, a void having a desired size cannot be formed unless the size of the adhesion preventive agent layer made of the resin is sufficiently increased.
- the adhesion preventing agent layer is formed on the upper and lower ceramic green sheets.
- the adhesion preventing agent layer may be formed only on one side.
- the terminal electrode of the chip-type ceramic electronic component may be directly connected to the surface electrode between the ceramic green layers or the via hole electrode formed in the ceramic green layer instead of the protruding electrode.
- the present invention can be suitably used for a ceramic multilayer substrate used in an electronic device or the like and a manufacturing method thereof.
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Abstract
Description
本発明は、セラミック多層基板の製造方法及びセラミック多層基板に関し、更に詳しくは、チップ型セラミック電子部品を内蔵するセラミック多層基板の製造方法及びセラミック多層基板に関するものである。 The present invention relates to a method for manufacturing a ceramic multilayer substrate and a ceramic multilayer substrate, and more particularly to a method for manufacturing a ceramic multilayer substrate incorporating a chip-type ceramic electronic component and a ceramic multilayer substrate.
従来のこの種の技術としては特許文献1に記載の電子部品内蔵多層セラミック基板や、特許文献2に記載の多層セラミック基板およびその製造方法がある。 Conventional technologies of this type include a multilayer ceramic substrate with built-in electronic components described in Patent Document 1, a multilayer ceramic substrate described in Patent Document 2, and a method for manufacturing the same.
特許文献1に記載された電子部品内蔵多層セラミック基板は、多層セラミック基板と、多層セラミック基板内の凹部または貫通孔から形成される空間内に収容されたチップ型セラミック電子部品と、多層セラミック基板の層間または空間内に設けられている上記チップ型電子部品を配線している導体と備えている。このように多層セラミック基板内の空間内にチップ型電子部品を収容するため、平面性を悪化させることなく、所望形状の多層セラミック基板が得られる。 An electronic component built-in multilayer ceramic substrate described in Patent Document 1 includes a multilayer ceramic substrate, a chip-type ceramic electronic component housed in a space formed by a recess or a through hole in the multilayer ceramic substrate, and a multilayer ceramic substrate. It is provided with the conductor which has wired the above-mentioned chip type electronic component provided in the interlayer or space. Thus, since the chip-type electronic component is accommodated in the space in the multilayer ceramic substrate, a multilayer ceramic substrate having a desired shape can be obtained without deteriorating the flatness.
特許文献2に記載された多層セラミック基板及びその製造方法の場合には、セラミック機能素子を予め焼成して得られた焼結体プレートをもって、コンデンサ素子、インダクタ素子及び抵抗素子等の機能素子を作製しておき、これらの機能素子を未焼結複合積層体内に内蔵させる。未焼結複合積層体は、基体用グリーン層と、難焼結性材料を含む拘束層と、配線導体とを備えており、これを焼成した時、拘束層の作用により、基体用グリーン層は主面方向での収縮が抑制される。拘束層を用いた無収縮工法によって焼成するため、機能素子を内蔵した状態で未焼結複合積層体を問題なく焼成することができると共に、機能素子と基体用グリーン層との間で成分の相互拡散が生じず、機能素子の特性が焼成後も維持される。 In the case of the multilayer ceramic substrate and the manufacturing method thereof described in Patent Document 2, functional elements such as a capacitor element, an inductor element, and a resistance element are produced using a sintered body plate obtained by firing the ceramic functional element in advance. In addition, these functional elements are built in the unsintered composite laminate. The unsintered composite laminate includes a base green layer, a constraining layer containing a hardly sinterable material, and a wiring conductor. When fired, the base green layer is formed by the action of the constraining layer. Shrinkage in the main surface direction is suppressed. Since it is fired by a non-shrinkage method using a constraining layer, the unsintered composite laminate can be fired without any problems in a state in which the functional element is incorporated, and the components are mutually exchanged between the functional element and the green layer for the substrate. Diffusion does not occur and the characteristics of the functional element are maintained after firing.
しかしながら、特許文献1及び特許文献2に記載の多層セラミック基板の場合には、チップ型セラミック電子部品を内蔵したセラミックグリーンシートの積層体を焼成して多層セラミック基板を得るため、焼成によって得られた多層セラミック基板に内蔵のチップ型セラミック電子部品にクラックが生じたり、場合によってはチップ型セラミック電子部品が破壊されることすらあった。この現象は、拘束層を用いた無収縮工法においても認められた。また、これらの多層セラミック基板は、チップ型電子部品とセラミックグリーンシートとが密着した状態で焼成されるため、チップ型電子部品とセラミック層との間における材料成分の相互拡散を防止することが難しく、特許文献2に記載の技術でさえもチップ型電子部品の特性が低下する虞があった。 However, in the case of the multilayer ceramic substrates described in Patent Document 1 and Patent Document 2, a multilayer ceramic substrate is obtained by firing a multilayer body of ceramic green sheets incorporating chip-type ceramic electronic components. Cracks were generated in the chip-type ceramic electronic component built in the multilayer ceramic substrate, and in some cases, the chip-type ceramic electronic component was even destroyed. This phenomenon was also observed in the non-shrinkage method using a constrained layer. In addition, since these multilayer ceramic substrates are fired in a state where the chip-type electronic component and the ceramic green sheet are in close contact, it is difficult to prevent mutual diffusion of material components between the chip-type electronic component and the ceramic layer. Even with the technique described in Patent Document 2, the characteristics of the chip-type electronic component may be deteriorated.
また、特許文献1に記載のように、チップ型電子部品を収納する凹部または貫通孔がキャビティ内に形成されている多層セラミック基板の場合には、基板強度がキャビティの部分で著しく低下するという問題もあった。 In addition, as described in Patent Document 1, in the case of a multilayer ceramic substrate in which a recess or a through hole for accommodating a chip-type electronic component is formed in the cavity, the problem is that the substrate strength is significantly reduced at the cavity portion. There was also.
本発明は、上記課題を解決するためになされたもので、チップ型セラミック電子部品にクラック等の損傷がなく、しかもチップ型セラミック電子部品の特性が低下することのない、信頼性の高いセラミック多層基板の製造方法及びセラミック多層基板を提供することを目的としている。 The present invention has been made in order to solve the above-described problems, and is a highly reliable ceramic multilayer in which chip-type ceramic electronic components are not damaged such as cracks and the characteristics of chip-type ceramic electronic components are not deteriorated. It is an object of the present invention to provide a substrate manufacturing method and a ceramic multilayer substrate.
本発明者は、セラミック多層基板に内蔵されたチップ型セラミック電子部品が損傷する原因について種々検討した結果、以下の知見を得た。
即ち、セラミック多層基板のセラミック層とチップ型セラミック電子部品との熱膨張係数が大きく異なる場合にチップ型セラミック電子部品にクラックが発生したり、破損したりすることが判った。無収縮工法を採用することによって基板の面方向の収縮を抑制すれば、収縮しないチップ型セラミック電子部品を内蔵させることができる。ところが、積層コンデンサ等のチップ型セラミック電子部品は高誘電率材料によって構成されていることが多く、高誘電率材料は一般に熱膨張係数が大きい。これに対して、セラミック層となるセラミックグリーン層の材料は、低誘電率材料によって構成されることが多く、低誘電率材料は一般に熱膨張係数が小さい。
As a result of various studies on the cause of damage to chip-type ceramic electronic components built in the ceramic multilayer substrate, the present inventor has obtained the following knowledge.
That is, it has been found that when the thermal expansion coefficients of the ceramic layer of the ceramic multilayer substrate and the chip-type ceramic electronic component are greatly different, the chip-type ceramic electronic component is cracked or damaged. If shrinkage in the surface direction of the substrate is suppressed by adopting a non-shrinkage construction method, a chip-type ceramic electronic component that does not shrink can be incorporated. However, chip-type ceramic electronic components such as multilayer capacitors are often made of a high dielectric constant material, and the high dielectric constant material generally has a large thermal expansion coefficient. On the other hand, the material of the ceramic green layer serving as the ceramic layer is often composed of a low dielectric constant material, and the low dielectric constant material generally has a small thermal expansion coefficient.
そのため、チップ型セラミック電子部品とセラミックグリーン層が密着した状態でこれらを焼成した後、常温まで冷却すると、冷却時にチップ型セラミック電子部品がセラミック層より大きく収縮し、セラミック層からチップ型セラミック電子部品に対して引っ張り力が働く。チップ型セラミック電子部品は、セラミック材料によって形成されているが、セラミック材料は引っ張り応力に対して弱いため、セラミック層からの引っ張り力によってクラックが発生したり、破損したりする。このため、セラミック多層基板に内蔵させるチップ型セラミック電子部品の構成材料が制限されることになる。換言すれば、チップ型セラミック電子部品とセラミック層とが密着していなければ、チップ型セラミック電子部品が損傷したり、チップ型セラミック電子部品の構成材料が制限されたりする不都合を解消することができる。 For this reason, after firing the chip-type ceramic electronic component and the ceramic green layer in close contact with each other and cooling to room temperature, the chip-type ceramic electronic component shrinks more than the ceramic layer during cooling, and the chip-type ceramic electronic component from the ceramic layer Pulling force works against. The chip-type ceramic electronic component is formed of a ceramic material. However, since the ceramic material is weak against tensile stress, the tensile force from the ceramic layer causes cracking or breakage. For this reason, the constituent material of the chip-type ceramic electronic component incorporated in the ceramic multilayer substrate is limited. In other words, if the chip-type ceramic electronic component and the ceramic layer are not in close contact with each other, it is possible to eliminate the disadvantage that the chip-type ceramic electronic component is damaged or that the constituent material of the chip-type ceramic electronic component is limited. .
本発明は、上記知見に基づいてなされたものである。
即ち、本発明のセラミック多層基板の製造方法は、複数のセラミックグリーン層が積層され且つ導体パターンを有するセラミックグリーン積層体と、セラミック焼結体と端子電極を有し且つ上記セラミックグリーン積層体の内部に配置されると共に上記端子電極が上記導体パターンと電気的に接続されるチップ型セラミック電子部品と、を同時に焼成することによって、チップ型セラミック電子部品を内蔵するセラミック多層基板を製造する方法であって、上記セラミックグリーン層の上記チップ型セラミック電子部品と接する箇所に密着防止剤層を形成する第1の工程と、上記セラミックグリーン積層体と上記チップ型セラミック電子部品を焼成して上記密着防止剤層を焼失させる第2の工程と、を含むことを特徴とするものである。
The present invention has been made based on the above findings.
That is, the method for producing a ceramic multilayer substrate according to the present invention includes a ceramic green laminate having a plurality of ceramic green layers laminated and having a conductor pattern, a ceramic sintered body, a terminal electrode, and an interior of the ceramic green laminate. And a ceramic ceramic substrate containing the chip-type ceramic electronic component by simultaneously firing the chip-type ceramic electronic component disposed at the same time and having the terminal electrode electrically connected to the conductor pattern. A first step of forming an adhesion preventive agent layer at a portion of the ceramic green layer in contact with the chip-type ceramic electronic component; and firing the ceramic green laminate and the chip-type ceramic electronic component to form the adhesion preventive agent. And a second step of burning out the layer.
また、本発明のセラミック多層基板の製造方法では、上記チップ型セラミック電子部品の両面に上記密着防止剤層を配置する工程を含むことが好ましい。 Further, the method for producing a ceramic multilayer substrate of the present invention preferably includes a step of disposing the adhesion preventive agent layer on both surfaces of the chip-type ceramic electronic component.
また、本発明のセラミック多層基板の製造方法では、上記密着防止剤は樹脂ペーストであって、上記第1の工程では、上記樹脂ペーストを上記セラミックグリーン層上に塗布することが好ましい。 In the method for producing a ceramic multilayer substrate of the present invention, it is preferable that the adhesion preventing agent is a resin paste, and in the first step, the resin paste is applied onto the ceramic green layer.
また、本発明のセラミック多層基板の製造方法では、上記密着防止剤は、低酸素雰囲気では焼失しないが、高酸素雰囲気で焼失する焼失材料を含み、上記第1の工程では、上記焼失材料からなるペーストを上記セラミックグリーン層上に塗布し、上記第2の工程では、上記セラミックグリーン積層体と上記チップ型セラミック電子部品を低酸素雰囲気で焼成した後、これら両者を高酸素雰囲気で再度焼成して上記焼失材料を焼失させることが好ましい。 In the method for producing a ceramic multilayer substrate of the present invention, the adhesion preventing agent does not burn out in a low oxygen atmosphere, but includes a burned material burned out in a high oxygen atmosphere. In the first step, the burnout material is composed of the burned material. In the second step, the ceramic green laminate and the chip-type ceramic electronic component are fired in a low oxygen atmosphere, and then both are fired again in a high oxygen atmosphere. It is preferable to burn off the burnout material.
また、本発明のセラミック多層基板の製造方法では、上記焼失材料は、カーボンであることが好ましい。 In the method for producing a ceramic multilayer substrate of the present invention, the burnout material is preferably carbon.
また、本発明のセラミック多層基板の製造方法では、上記密着防止剤層の上記チップ型セラミック電子部品の端子電極と重なる箇所にビアホールを形成し、上記ビアホールに導電性ペーストを充填する工程を含むことが好ましい。 Further, the method for producing a ceramic multilayer substrate of the present invention includes a step of forming a via hole at a position overlapping the terminal electrode of the chip-type ceramic electronic component of the adhesion preventive agent layer and filling the via hole with a conductive paste. Is preferred.
また、本発明のセラミック多層基板の製造方法では、上記セラミックグリーン積層体の少なくとも一方の主面に上記セラミックグリーン積層体の焼成温度では焼結しない無機材料からなる拘束層を配置した状態で上記セラミックグリーン積層体と上記チップ型セラミック電子部品とが焼成されることが好ましい。 Further, in the method for producing a ceramic multilayer substrate according to the present invention, the ceramic ceramic laminate with the constraining layer made of an inorganic material that is not sintered at the firing temperature of the ceramic green laminate is disposed on at least one main surface of the ceramic green laminate. The green laminate and the chip-type ceramic electronic component are preferably fired.
また、本発明のセラミック多層基板の製造方法では、上記セラミックグリーン積層体の焼結体の熱膨張係数と上記チップ型セラミック電子部品を構成するセラミック焼結体の熱膨張係数とが略等しいことが好ましい。 In the method for producing a ceramic multilayer substrate according to the present invention, the thermal expansion coefficient of the sintered body of the ceramic green laminate is substantially equal to the thermal expansion coefficient of the ceramic sintered body constituting the chip-type ceramic electronic component. preferable.
また、本発明のセラミック多層基板は、複数のセラミック層が積層され且つ導体パターンを有するセラミック積層体と、上下のセラミック層の界面に設けられ且つセラミック焼結体及び上記導体パターンと電気的に接続された端子電極を有するチップ型セラミック電子部品と、を備えたセラミック多層基板であって、上記セラミック層と上記チップ型セラミック電子部品との界面に空隙が存在すると共に、上記チップ型セラミック電子部品の端子電極と上記導体パターンとが、上記空隙に形成された突起電極によって電気的に接続されていることを特徴とするものである。 In addition, the ceramic multilayer substrate of the present invention is provided at the interface between a ceramic laminate in which a plurality of ceramic layers are laminated and have a conductor pattern, and upper and lower ceramic layers, and is electrically connected to the ceramic sintered body and the conductor pattern. A ceramic multilayer substrate comprising a chip-type ceramic electronic component having a terminal electrode, wherein a gap exists at an interface between the ceramic layer and the chip-type ceramic electronic component, The terminal electrode and the conductor pattern are electrically connected by a protruding electrode formed in the gap.
また、本発明のセラミック多層基板では、上記突起電極は、上記空隙に接するセラミック層に形成されたビアホール導体と直接接続されていることが好ましい。 In the ceramic multilayer substrate of the present invention, it is preferable that the protruding electrode is directly connected to a via-hole conductor formed in a ceramic layer in contact with the gap.
また、本発明のセラミック多層基板では、上記チップ型セラミック電子部品の端子電極が上記セラミック層の積層方向に離間して配置されていることが好ましい。 Further, in the ceramic multilayer substrate of the present invention, it is preferable that the terminal electrodes of the chip-type ceramic electronic component are arranged apart from each other in the stacking direction of the ceramic layers.
また、本発明のセラミック多層基板では、上記突起電極が延性に富む材料によって形成されていることが好ましい。 Further, in the ceramic multilayer substrate of the present invention, it is preferable that the protruding electrode is formed of a material having high ductility.
また、本発明のセラミック多層基板では、上記延性に富む材料が銀であることが好ましい。 In the ceramic multilayer substrate of the present invention, it is preferable that the material having high ductility is silver.
本発明によれば、チップ型セラミック電子部品にクラック等の損傷がなく、しかもチップ型セラミック電子部品の特性が低下することのない、信頼性の高いセラミック多層基板の製造方法及びセラミック多層基板を提供することができる。 According to the present invention, there is provided a highly reliable method for manufacturing a ceramic multilayer substrate and a ceramic multilayer substrate in which the chip-type ceramic electronic component is not damaged such as cracks and the characteristics of the chip-type ceramic electronic component are not deteriorated. can do.
10、10A、10B セラミック多層基板
11 セラミック積層体
11A セラミック層
12 導体パターン
13、113 チップ型セラミック電子部品
13A セラミック焼結体
13B 端子電極
111 セラミックグリーン積層体
111A セラミックグリーンシート(セラミックグリーン層)
114 密着防止剤層
115 拘束層
V 空隙
10, 10A, 10B
114
以下、図1~図4に示す実施形態に基づいて本発明を説明する。尚、各図中、図1の(a)、(b)はそれぞれ本発明のセラミック多層基板の一実施形態を示す図で、(a)はその全体を示す断面図、(b)は(a)の○で囲んだ部分を拡大して示す断面図、図2の(a)~(e)はそれぞれ図1に示すセラミック多層基板を製造する方法の要部を示す工程図、図3は本発明のセラミック多層基板の他の実施形態を示す図1の(b)に相当する断面図、図4は本発明のセラミック多層基板の更に他の実施形態を示す図1の(b)に相当する断面図である。 Hereinafter, the present invention will be described based on the embodiment shown in FIGS. 1A and 1B are diagrams showing an embodiment of the ceramic multilayer substrate of the present invention, FIG. 1A is a sectional view showing the whole of the ceramic multilayer substrate, and FIG. ) In FIG. 2 is an enlarged cross-sectional view, FIGS. 2A to 2E are process diagrams showing the main part of the method for manufacturing the ceramic multilayer substrate shown in FIG. 1, and FIG. sectional view corresponding to FIG. 1 (b) shows another embodiment of the ceramic multilayer substrate of the invention, corresponding to (b) of FIG. 1 FIG. 4 showing still another embodiment of the ceramic multilayer substrate of the present invention It is sectional drawing.
第1の実施形態
本実施形態のセラミック多層基板10は、例えば図1の(a)に示すように、複数のセラミック層11Aが積層され且つ導体パターン12を有するセラミック積層体11と、上下のセラミック層11Aの界面に設けられ、セラミック焼結体13Aを素体とし且つその両端部に端子電極13Bを有するチップ型セラミック電子部品13と、を備えている。また、セラミック積層体11の両主面(上下両面)にはそれぞれ表面電極14、14が形成されている。
First Embodiment A
セラミック積層体11の一方の主面(本実施形態では上面)には表面電極14を介して複数の表面実装部品20が実装されている。表面実装部品20としては、半導体素子、ガリウム砒素半導体素子等の能動素子やコンデンサ、インダクタ、抵抗等の受動素子等が半田や導電性樹脂を介して、あるいはAu、Al、Cu等のボンディングワイヤーを介してセラミック積層体11上面の表面電極14に電気的に接続されている。チップ型セラミック電子部品13と表面実装部品20は、表面電極14及び内部導体パターン12を介して互いに電気的に接続されている。このセラミック多層基板10は、他方の主面(本実施形態では、下面)の表面電極14を介してマザーボード等の実装基板に実装することができる。
A plurality of surface mount components 20 are mounted on one main surface (upper surface in the present embodiment) of the
而して、例えば図1の(b)に示すように、上下のセラミック層11A、11Aとチップ型セラミック電子部品13の界面には空隙Vが存在し、チップ型セラミック電子部品13の全面(6面)が空隙Vを介して上下のセラミック層11A、11Aの内面と対向している。上側のセラミック層11Aには導体パターン12が形成されている。この導体パターン12は、上側のセラミック層11Aの表面に所定のパターンで形成された表面電極12Aと、この表面電極12Aから上側のセラミック層11Aを上下に貫通して形成されたビアホール導体12Bと、ビアホール導体12Bから空隙Vに突出してチップ型セラミック電子部品13の端子電極13Bに電気的に接続された突起電極12Cと、を有する。
Thus, for example, as shown in FIG. 1B, a gap V exists at the interface between the upper and lower
突起電極12Cは、例えばビアホール導体12Bと一体的に形成されて、ビアホール導体12Bとチップ型セラミック電子部品13の端子電極13Bを互いに電気的に接続している。従って、チップ型セラミック電子部品13は、上下のセラミック層11A、11Aの間に形成された空間内であたかも突起電極12Cによって吊り下げられたようになっている。
The protruding
而して、セラミック積層体11を構成するセラミック層11Aの材料は、セラミック材料であれば特に制限されないが、例えば低温焼結セラミック(LTCC:Low Temperature Co-fired Ceramic)材料が好ましい。低温焼結セラミック材料とは、1050℃以下の温度で焼結可能であって、比抵抗の小さなAgやCu等と同時焼成が可能なセラミック材料である。低温焼結セラミックとしては、具体的には、アルミナやフォルステライト等のセラミック粉末にホウ珪酸系ガラスを混合してなるガラス複合系LTCC材料、ZnO-MgO-Al2O3-SiO2系の結晶化ガラスを用いた結晶化ガラス系LTCC材料、BaO-Al2O3-SiO2系セラミック粉末やAl2O3-CaO-SiO2-MgO-B2O3系セラミック粉末等を用いた非ガラス系LTCC材料等が挙げられる。
Thus, the material of the
セラミック積層体11の材料として低温焼結セラミック材料を用いることによって、導体パターン12としてAgまたはCu等の低抵抗で低融点をもつ低融点金属を用いることができる。その結果、セラミック積層体11と導体パターン12を1050℃以下の低温で同時焼成することができる。特に、ビアホール導体12Bに接続された突起電極12Cは、セラミック積層体11内でチップ型セラミック電子部品13を吊り下げているため、セラミック層11Aとチップ型セラミック電子部品13の熱膨張差を吸収し得るように延性に富むAgによって形成されていることが好ましい。
By using a low-temperature sintered ceramic material as the material of the
また、セラミック材料として、高温焼結セラミック(HTCC:High Temperature Co-fired Ceramic)材料を使用することもできる。高温焼結セラミック材料としては、例えば、アルミナ、窒化アルミニウム、ムライト、その他の材料にガラスなどの焼結助剤を加え、1100℃以上で焼結されたものが用いられる。このとき、導体パターン12としては、モリブデン、白金、パラジウム、タングステン、ニッケル及びこれらの合金から選択される金属を使用する。
Also, a high temperature sintered ceramic (HTCC) material can be used as the ceramic material. Examples of the high-temperature sintered ceramic material include alumina, aluminum nitride, mullite, and other materials added with a sintering aid such as glass and sintered at 1100 ° C. or higher. At this time, as the
チップ型セラミック電子部品13としては、特に制限されないが、例えばチタン酸バリウムやフェライト等の1050℃以上、更には1200℃以上で焼成されたセラミック焼結体13Aを素体としたもの、例えば図1に示す積層セラミックコンデンサの他、インダクタ、フィルタ、バラン、カップラ等のチップ型セラミック電子部品を用いることができる。これらのチップ型セラミック電子部品13は目的に応じて単数あるいは複数適宜選択してセラミック積層体11内に配置することができる。また、セラミック多層基板10に使用されるチップ型セラミック電子部品13の端子電極13Bは、導電性ペーストを塗布して焼き付けたものであっても、導電性ペーストを塗布して乾燥させて焼き付ける前のものであっても良い。
The chip-type ceramic
このようにチップ型セラミック電子部品13とセラミック積層体11の界面に空隙Vが介在しているため、セラミック積層体11に熱応力等の応力が面方向に作用しても、その応力がチップ型セラミック電子部品13に直接伝達されることがなく、突起電極12Cで吸収され、チップ型セラミック電子部品13に亀裂が発生したり、チップ型セラミック電子部品13が損傷したりすることがない。また、セラミック積層体11の熱膨張係数とチップ型セラミック電子部品13のセラミック焼結体13Aの熱膨張係数を略同一にすることによって、突起電極12Cに加えられる熱応力を軽減することができ、突起電極12Cの延性が乏しくても、突起電極12Cに対して大きな負荷が加わることを防止することができる。
As described above, since the gap V is interposed at the interface between the chip-type ceramic
図1の(b)では図1の(a)に示す一箇所のチップ型セラミック電子部品13に着目して説明したが、チップ型セラミック電子部品13は、目的に応じて上下のセラミック層11A、11Aの界面のいずれかの箇所に複数並べて配置されても良く、また、上下の異なる複数の界面に複数段に亘って配置されても良い。従って、複数のチップ型セラミック電子部品13は、目的に応じて、導体パターン12を介して互いに直列及び/または並列に電気的に接続して、セラミック多層基板10を多機能化、高性能化することができる。
In FIG. 1B, the description has been made by paying attention to the chip-type ceramic
次いで、図2の(a)~(e)を参照しながら図1の(a)、(b)に示すセラミック多層基板10の製造方法について説明する。
本実施形態では無収縮工法を用いてセラミック多層基板10を作製する場合について説明する。無収縮工法とは、セラミック積層体の焼成前後でセラミック積層体の平面方向の収縮を抑止あるいは防止し、平面方向の寸法が実質的に変化しない工法のことを云う。
Next, a method for manufacturing the
In this embodiment, the case where the
本実施形態では、低温焼結セラミック材料を含むスラリーを用いて、図2の(a)に示すようにセラミックグリーンシート111Aを必要枚数作製する。ここでは図1の(b)に示す上下二段のセラミック層11Aを有するセラミック多層基板10を試験的に作製する場合について説明する。そして、2枚のセラミックグリーンシート111Aを、それぞれ第1のセラミックグリーンシート111A、第2のセラミックグリーンシート111A’と定義する。尚、セラミックグリーンシートは、セラミックグリーン積層体ではセラミックグリーン層となるため、第1、第2のセラミックグリーンシート111A、111A’からなるセラミックグリーン層にもセラミックグリーンシートと同一符号を付して説明する。
In the present embodiment, a required number of ceramic
次いで、例えばスクリーン印刷法を用いて、第1、第2のセラミックグリーンシート111A、111A’の上面に図2の(a)に示すように焼失材料を主成分とするペーストからなる密着防止剤を印刷して密着防止剤層114を形成する。密着防止剤としては、焼成時にチップ型セラミック電子部品13と第1、第2のセラミックグリーンシート111A、111A’の間での材料成分の相互拡散を防止し、焼成後には焼失して上下のセラミック層11A、11Aとチップ型セラミック電子部品13の界面に空隙Vを形成する材料が用いられる。密着防止剤としては、上記機能を有するものであれば、特に制限されない。このような密着防止剤としては、例えば樹脂やカーボン等の焼失材料を用いることができる。
Next, using, for example, a screen printing method, an adhesion preventing agent made of a paste containing a burned-out material as a main component as shown in FIG. 2A is applied to the upper surfaces of the first and second ceramic
第1、第2のセラミックグリーンシート111A、111A’それぞれに密着防止剤層114を形成した後、例えばパンチャーを用いて、図2の(b)に示すように第1のセラミックグリーンシート111A及び密着防止剤層114を貫通するビアホールを形成した後、密着防止剤層114とは反対側の面から第1のセラミックグリーンシート111AにAgを主成分とする導電性ペーストをスクリーン印刷することによって、第1のセラミックグリーンシート111Aのビアホール内に導電性ペーストを充填してビアホール導体部112Bを形成すると共に表面電極部112Aを形成する。この際、密着防止剤層114の貫通孔には突起電極部112Cがビアホール導体部112Bと一体的に形成される。これらのビアホール導体部112B及び突起電極部112Cは、チップ型セラミック電子部品13の一対の端子電極13Bに対応して形成される(図2の(c)参照)。
After the adhesion
然る後、図2の(c)に示すように第2のセラミックグリーンシート111A’を、密着防止剤層114を上向きにして配置し、第2のセラミックグリーンシート111A’の密着防止剤層114上にチップ型セラミック電子部品113を配置した後、これらの上方に第1のセラミックグリーンシート111Aを、密着防止剤層114を下向きにして配置する。この際、第2のセラミックグリーンシート111A’の密着防止剤層114の所定箇所にチップ型セラミック電子部品113を接着剤で固定しておくことが好ましい。このように第2のセラミックグリーンシート111A’の上にチップ型セラミック電子部品113及び第1のセラミックグリーンシート111Aを積層し、圧着することにより、チップ型セラミック電子部品113を内蔵するセラミックグリーン積層体111を形成する。尚、セラミック多層基板10に内蔵させる前のチップ型セラミック電子部品には符号「113」を付して説明する。
Thereafter, as shown in FIG. 2C, the second ceramic
第1、第2のセラミックグリーンシート111A、111A’を圧着すると、図2の(d)に示すように第1、第2のセラミックグリーンシート111A、111A’がセラミックグリーン層111A、111A’として積層されてセラミックグリーン積層体111を形成し、セラミックグリーン積層体111内ではチップ型セラミック電子部品113が密着防止剤層114によって包み込まれた状態になる。次いで、このセラミッククリーン積層体111の上下両面に拘束層115を配置し、上下の拘束層115によってセラミックグリーン積層体111を挟み込んだ後、所定の温度及び圧力で熱圧着して、図2の(d)に示す圧着体110を得る。拘束層115としては、セラミックグリーン積層体111の焼結温度では焼結しない難焼結性粉末、例えばAl2O3を主成分として含むと共に有機バインダを副成分として含むスラリーから同図に示すようにシート状に形成されたものが用いられる。
When the first and second ceramic
更に、図2の(d)に示す圧着体110を、拘束層115は焼結しないがセラミックグリーン積層体111が焼結する温度で焼成する。この際、密着防止剤層114が樹脂ペーストで形成されている場合とカーボンペーストで形成されている場合とでは焼成条件が異なる。
2 is fired at a temperature at which the constraining
密着防止剤層114が樹脂ペーストで形成されている場合には、図2の(d)に示す圧着体110を例えば空気雰囲気中900℃で焼成して密着防止剤層114を完全に焼失させた後、拘束層115を除去することによって図2の(e)に示すセラミック多層基板10を得る。
When the adhesion preventing
また、密着防止剤層114がカーボンペーストで形成されている場合には、図2の(d)に示す圧着体110をカーボンが焼失せずに残留する大気よりも酸素分圧が低い低酸素雰囲気(例えば、酸素分圧を10-3~10-6atmとした場合)に調整して870℃で焼成した後、高酸素雰囲気(例えば、酸素分圧の高い大気)に調整して900℃にて再度焼成してカーボンペーストからなる密着防止剤層114を完全に焼失させて、図2の(e)に示すセラミック多層基板10を得る。低酸素雰囲気で焼成する時にはセラミックグリーン積層体111が焼成されてセラミック積層体11として焼結しても密着防止層114のカーボンは焼失せずに残留してその占有空間を保持し、高酸素雰囲気で再焼成する時にはカーボンが完全に燃焼して焼失する。
Further, when the adhesion preventing
焼成温度としては、低温焼結セラミック材料が焼結する温度、例えば800~1050℃の範囲が好ましい。焼成温度が800℃未満ではセラミックグリーン積層体111のセラミック成分が十分に焼結しない虞があり、1050℃を超えると表面電極12A等の金属粒子が溶融してセラミックグリーン層11内へ拡散する虞がある。
The firing temperature is preferably a temperature at which the low-temperature sintered ceramic material is sintered, for example, in the range of 800 to 1050 ° C. If the firing temperature is less than 800 ° C., the ceramic component of the ceramic
セラミックグリーン積層体111の焼成により、チップ型セラミック電子部品113を包み込む密着防止剤層114は、セラミックグリーン積層体111の焼成時に焼失し、図2の(e)に示すようにチップ型セラミック電子部品13とセラミック積層体11の界面に狭い空隙Vが形成されると共に空隙Vにはビアホール導体12Bと端子電極13Bを電気的に接続する突起電極12Cが形成される。この時、セラミック積層体11の熱膨張係数とチップ型セラミック電子部品13の熱膨張係数との差が大きくても、セラミック積層体11とチップ型セラミック電子部品13との間に空隙Vが介在し、チップ型セラミック電子部品13が突起電極12Cでのみセラミック積層体11のビアホール導体12Bに接続されているため、セラミック積層体11とチップ型セラミック電子部品13との間の熱膨張係数差に起因する熱応力は延性に富むAgによって形成された突起電極12Cにおいて吸収され、チップ型セラミック電子部品13に直接作用する熱応力が緩和されるため、チップ型セラミック電子部品13に亀裂が発生したり、チップ型セラミック電子部品13が損傷したりすることがない。
Due to the firing of the ceramic
更に、セラミックグリーン積層体111が焼結する段階でセラミック積層体11とチップ型セラミック電子部品13の界面に空隙Vが形成されるため、セラミック積層体11とチップ型セラミック電子部品13のセラミック焼結体13Aとの間における材料成分の相互拡散を確実に防止することができ、焼成後のチップ型セラミック電子部品13の特性低下を防止することができる。また、突起電極部12Cとチップ型セラミック電子部品13の端子電極13Bは、それぞれの金属粒子が粒成長して焼結して一体化し、これら両者12C、13Bが強固に接続される。
Further, since the void V is formed at the interface between the
焼成後には、ブラスト処理や超音波洗浄処理によって上下の拘束層115を除去して、セラミック多層基板10を得ることができる。
After firing, the
以上説明したように本実施形態によれば、複数のセラミックグリーン層111Aが積層され且つ導体パターン部112を有するセラミックグリーン積層体111と、セラミック焼結体113Aと端子電極113Bを有し且つセラミックグリーン積層体111の内部に配置されると共に端子電極113Bが導体パターン部112と電気的に接続されるチップ型セラミック電子部品113と、を同時に焼成することによって、チップ型セラミック電部品13を内蔵するセラミック多層基板10を製造する際に、セラミックグリーン層111A、111A’のチップ型セラミック電子部品113と接する箇所に密着防止剤層114を形成する工程と、セラミックグリーン積層体111とチップ型セラミック電子部品113を焼成して密着防止剤層114を焼失させる工程と、を含むため、焼成時に密着防止剤層114が焼失して、セラミック積層体11とチップ型セラミック電子部品13の界面に空隙Vができる。その結果、焼成時にセラミック積層体11の熱膨張係数とチップ型セラミック電子部品13の熱膨張係数との熱膨張係数差によってセラミック積層体11からチップ型セラミック電子部品13に熱応力が作用しても、この熱応力が突起電極12Cによって吸収され、熱応力が緩和されてチップ型セラミック電子部品13に伝わり難いため、チップ型セラミック電子部品13に亀裂が生じたり、チップ型セラミック電子部品13が損傷することがない。また、焼成時にセラミック層11Aとチップ型セラミック電子部品13の界面に形成される空隙Vは、セラミック積層体11とセラミック焼結体13Aとの間における材料成分の相互拡散を確実に防止することができ、セラミック多層基板10に内蔵されたチップ型セラミック電子部品13の特性の低下を防止することができる。
As described above, according to the present embodiment, the ceramic green
また、本実施形態によれば、密着防止剤層114をセラミックグリーンシート111Aに形成するため、密着防止剤層114を表面電極部112Aと同様の印刷工程で形成することができ、密着防止剤層114のための特別な工程または装置を導入することなく密着防止剤層114を形成することができる。また、チップ型セラミック電子部品13の両面に密着防止剤層114を配置するため、チップ型セラミック電子部品13全面を囲む空隙Vができて、チップ型セラミック電子部品13が突起電極12Cでのみセラミック積層体11のビアホール導体12Bに接続されているため、熱応力に強い構造のセラミック多層基板10を得ることができる。また、焼失材料として焼成温度よりも低い温度で焼失する樹脂を用いて密着防止剤層114を形成するため、焼成時に空隙Vをより確実に形成することができる。焼失材料としてカーボンを用いる場合には、低酸素雰囲気で焼成する時にはカーボンが残留してセラミックグリーンシート111A、111A’の収縮を抑制することにより、空隙Vとなるべき空間を確実に確保し、高酸素雰囲気でカーボンを完全に燃焼、焼失させて所望の空隙Vを確実に形成することができる。
Further, according to the present embodiment, since the adhesion preventing
また、本実施形態によれば、セラミック層11Aは低温焼結セラミック層であるため、導体パターン12としてAg等の低抵抗で安価な金属を用いることができ、製造コストの低減や高周波数特性の向上に寄与することができる。更に、セラミック多層基板10は無収縮工法によって製造されるため、平面方向の収縮が殆どない。従って、焼成時にチップ型セラミック電子部品13に作用する熱応力を格段に軽減することができ、チップ型セラミック電子部品13の損傷をより確実に防止することができる。
In addition, according to the present embodiment, since the
第2の実施形態
本実施形態のセラミック多層基板10Aは、図3に示すようにチップ型セラミック電子部品13の種類を異にする以外は、第1の実施形態に準じて構成されている。そこで、第1の実施形態と同一または相当部分には同一符号を付して本実施形態の特徴部分を説明する。
Second Embodiment A
本実施形態におけるチップ型セラミック電子部品13は、図3に示すように、セラミック焼結体13Aと、セラミック焼結体13Aの上下両面に形成された一対の端子電極13Bと、を有している。一対の端子電極13Bは、セラミック層11Aの積層方向(上下方向)に離間して配置され、これらの端子電極13Bでセラミック焼結体13Aを上下から挟んでいる。上下の端子電極13Bは、それぞれの中央部で空隙Vに形成された突起電極12Cを介して上下のセラミック層11Aを貫通して形成されたビアホール導体12Bに対して電気的に接続されている。上下のビアホール導体12Bは、それぞれのセラミック層11Aの表面に形成された表面電極12Aと電気的に接続されている。尚、図3では上下の端子電極13Bはそれぞれ一箇所のビアホール導体12Bに対して突起電極12Cを介して接続されているが、必要に応じて複数箇所のビアホール導体に対して複数の突起電極で端子電極に接続しても良い。
As shown in FIG. 3, the chip-type ceramic
本実施形態のセラミック多層基板10Aは、チップ型セラミック電子部品13の端子電極13Bの構造を異にする以外は第1の実施形態のセラミック多層基板10に準じて構成されているため、第1の実施形態のセラミック多層基板10に準じて製造することができ、セラミック多層基板10と同様の作用効果を期することができる。
The
第3の実施形態
本実施形態のセラミック多層基板10Bは、図4に示すように、導体パターン12の形態を異にする以外は第1の実施形態に準じて構成されている。そこで、第1の実施形態と同一または相当部分には同一符号を付して本実施形態の特徴部分を説明する。
Third Embodiment As shown in FIG. 4, the
本実施形態におけるチップ型セラミック電子部品13は、図4に示すように、第1の実施形態におけるチップ型セラミック電子部品13と実質的に同一に構成されている。第1の実施形態では導体パターン12がチップ型セラミック電子部品13の上側のセラミック層11Aにのみ形成されていたが、本実施形態では下側のセラミック層11Aにも導体パターン12が形成されている。上下のセラミック層11Aに形成された導体パターン12は上下対称に形成されている。そこで、上側のセラミック層11Aの導体パターン12についてのみ説明する。
As shown in FIG. 4, the chip-type ceramic
導体パターン12は、図4に示すように、上側のセラミック層11Aを上下に貫通するビアホール導体12Bと、チップ型セラミック電子部品13の端子電極13Bと対面する上側のセラミック層11Aに形成された面内導体12Dと、この面内導体12Dと端子電極13Bを電気的に接続する突起電極12Cと、を有している。この導体パターン12は、左右の端子電極13Bにそれぞれ対応して形成されている。左右の突起電極12Cは、いずれもセラミック積層体11とチップ型セラミック電子部品13の界面に形成された空隙Vに形成されている。突起電極12Cは予め形成された密着防止剤層(図示せず)に貫通孔を設け、スクリーン印刷により貫通孔に導電性ペーストを充填することによって突起電極部を形成することができる。面内導体12Dは、スクリーン印刷によりセラミックグリーンシート(図示せず)に直接形成することができる。
As shown in FIG. 4, the
また、上述したように導体パターン12は、上下対称になるように下側のセラミック層11Aにもチップ型セラミック電子部品13の左右の端子電極13Bに対応して形成されている。尚、図4に示すセラミック多層基板10Bは、表面電極を有していないが、必要に応じて表面電極を設けても良いことは云うまでもない。
Also, as described above, the
本実施形態のセラミック多層基板10Bにおいても第1、第2の実施形態のセラミック多層基板20に準じて製造することができ、セラミック多層基板10と同様の作用効果を期することができる。
The
次に、具体的な実施例について以下説明する。 Next, specific examples will be described below.
実施例1
本実施例では図2の(a)~(e)に示す手順に従ってセラミック多層基板を作成した。即ち、2枚の第1、第2のセラミックグリーンシートに樹脂ペーストをスクリーン印刷して密着防止層を形成した。また、第1のセラミックグリーンシートにはパンチャーを用いて密着防止剤層をも貫通するビアホールを形成した後、Agを主成分とする導電性ペーストをビアホール内に充填してビアホール導体部を形成すると共に密着防止剤層と反対側の面に表面電極部を形成した。
Example 1
In this example, a ceramic multilayer substrate was prepared according to the procedure shown in FIGS. That is, the adhesion preventing layer was formed by screen printing the resin paste on the two first and second ceramic green sheets. Further, a via hole that also penetrates the adhesion preventive agent layer is formed on the first ceramic green sheet using a puncher, and then a conductive paste mainly composed of Ag is filled in the via hole to form a via hole conductor portion. And the surface electrode part was formed in the surface on the opposite side to an adhesion inhibitor layer.
第1、第2のセラミックグリーンシートの密着防止剤層でチップ型セラミック電子部品として100個の積層コンデンサを配列して挟み込んで圧着することにより、セラミックグリーン積層体内に100個の積層コンデンサを内蔵させた。このセラミックグリーン積層体の上下両面に拘束層を熱圧着して圧着体を得た。この圧着体を900℃で焼成した後、拘束層を除去してセラミック多層基板を得た。使用した積層コンデンサは、サイズが0402であり、その容量が10μFであった。そして、セラミック積層体の熱膨張係数は6ppm/℃であり、積層コンデンサの熱膨張係数は11ppm/℃であった。 By arranging 100 multilayer capacitors as chip-type ceramic electronic components in the first and second ceramic green sheet adhesion preventing agent layers, and sandwiching and pressing them, 100 multilayer capacitors are built in the ceramic green multilayer body. It was. A constraining layer was thermocompression bonded to the upper and lower surfaces of the ceramic green laminate to obtain a pressed body. After firing this pressure-bonded body at 900 ° C., the constraining layer was removed to obtain a ceramic multilayer substrate. The multilayer capacitor used had a size of 0402 and a capacitance of 10 μF. The thermal expansion coefficient of the ceramic multilayer body was 6 ppm / ° C., and the thermal expansion coefficient of the multilayer capacitor was 11 ppm / ° C.
また、比較例として、密着防止層のないセラミックグリーン積層体を作製し、このセラミックグリーン積層体を拘束層で挟み込んで熱圧着した後、実施例と同一要領で焼成して比較用セラミック多層基板を得た。 In addition, as a comparative example, a ceramic green laminate without an adhesion prevention layer was prepared, and this ceramic green laminate was sandwiched between constraining layers and thermocompression bonded, and then fired in the same manner as in the examples to produce a comparative ceramic multilayer substrate. Obtained.
上述のようにして得られた本実施例のセラミック多層基板について亀裂の有無を調べた結果、セラミック積層体及び積層コンデンサのいずれにも亀裂が認められなかった。また、積層コンデンサの容量を測定した結果、9.8μFであり、内蔵前の10μFから殆ど低下していなかった。これに対して比較用のセラミック多層基板についても同様に亀裂の有無を調べた結果、積層コンデンサに亀裂が認められ、所望とする容量を得ることができなかった。 As a result of examining the presence or absence of cracks in the ceramic multilayer substrate of this example obtained as described above, no cracks were observed in either the ceramic multilayer body or the multilayer capacitor. Moreover, as a result of measuring the capacity of the multilayer capacitor, it was 9.8 μF, which was almost the same as 10 μF before incorporation. On the other hand, as a result of examining the presence or absence of cracks in the ceramic multilayer substrate for comparison as well, cracks were found in the multilayer capacitor, and a desired capacity could not be obtained.
上記結果によれば、焼成により密着防止層が焼失してセラミック積層体と積層コンデンサの界面に空隙が形成され、セラミック積層体と積層コンデンサは突起電極でのみ接続された構造であるため、セラミック積層体と積層コンデンサの熱膨張係数差が5ppm/℃と非常に大きくても、延性の富む突起電極がセラミック積層体の熱膨張係数と積層コンデンサの熱膨張係数との熱膨張係数差による熱応力を緩和し、積層コンデンサにおいて亀裂が発生することなく、セラミック積層体に積層コンデンサを内蔵させることができた。 According to the above results, the adhesion preventing layer is burned out by firing, and a gap is formed at the interface between the ceramic multilayer body and the multilayer capacitor, and the ceramic multilayer body and the multilayer capacitor are connected only by protruding electrodes. Even if the difference in thermal expansion coefficient between the capacitor and the multilayer capacitor is as large as 5 ppm / ° C, the projecting electrode having high ductility can cause thermal stress due to the difference in thermal expansion coefficient between the thermal expansion coefficient of the ceramic multilayer body and that of the multilayer capacitor. The multilayer capacitor could be built in the ceramic multilayer body without any cracks in the multilayer capacitor.
実施例2
本実施例では実施例1で用いられた積層コンデンサに代えてチップコイル(10μH)を用いて、実施例1と同一要領でチップコイルを内蔵させ、セラミック積層体とチップコイルの界面に空隙を有するセラミック多層基板を作製した。このセラミック多層基板のセラミック積層体の熱膨張係数は10ppm/℃であり、チップコイルの熱膨張係数は10.2ppm/℃であった。また、比較用として空隙のないチップコイルを内蔵するセラミック多層基板を作製した。
Example 2
In this example, a chip coil (10 μH) is used instead of the multilayer capacitor used in Example 1, and the chip coil is built in the same manner as in Example 1, and there is a gap at the interface between the ceramic laminate and the chip coil. A ceramic multilayer substrate was produced. The thermal expansion coefficient of the ceramic multilayer body of this ceramic multilayer substrate was 10 ppm / ° C., and the thermal expansion coefficient of the chip coil was 10.2 ppm / ° C. For comparison, a ceramic multilayer substrate having a chip coil without voids was fabricated.
上述のようにして得られた本実施例のセラミック多層基板についてチップコイルのインダクタンス値を測定した結果、9.8μHであり、内蔵前の10μHから殆ど低下していなかった。これに対して比較用のセラミック多層基板のインダクタンス値は10μHから7.5μHまで大きく低下していた。 As a result of measuring the inductance value of the chip coil for the ceramic multilayer substrate of the present example obtained as described above, it was 9.8 μH, which was hardly lowered from 10 μH before incorporation. In contrast, the inductance value of the ceramic multilayer substrate for comparison was greatly reduced from 10 μH to 7.5 μH.
上記結果によれば、セラミック積層体の熱膨張係数とチップコイルの熱膨張係数との間の熱膨張係数差を殆どなくしても、空隙のない比較用のセラミック多層基板では焼成時にチップコイルに大きな圧縮応力が作用し、圧縮応力に対して特性変動の大きなフェライトを用いたチップコイルの特性が大きく低下したものと考えられる。平面方向の収縮を抑制する無収縮工法によっても厚み方向の収縮は抑制できないため、空隙のない比較用のセラミック多層基板において、チップコイルに圧縮応力が作用することは防止することができない。このことから、従来は圧縮応力に弱いチップコイルをそのままセラミック積層体に内蔵させることはできなかった。 According to the above results, even when there is almost no difference in thermal expansion coefficient between the thermal expansion coefficient of the ceramic laminate and the thermal expansion coefficient of the chip coil, the comparative ceramic multilayer substrate without voids has a large size in the chip coil during firing. It is considered that the characteristics of the chip coil using the ferrite having a large characteristic fluctuation with respect to the compressive stress greatly deteriorated due to the compressive stress. Since shrinkage in the thickness direction cannot be suppressed even by the non-shrinkage method that suppresses shrinkage in the planar direction, it is not possible to prevent compressive stress from acting on the chip coil in the comparative ceramic multilayer substrate without voids. For this reason, conventionally, a chip coil that is weak against compressive stress cannot be incorporated in the ceramic laminate as it is.
これに対して、本実施例のセラミック多層基板は、焼成によりセラミック積層体とチップコイルの界面に空隙が形成されるため、焼成時にセラミック積層体に厚み方向の収縮応力が作用しても、セラミック積層体とチップコイルの間の空隙によってチップコイルに圧縮応力が直接作用することがなく、チップコイルの特性変動を抑制することができた。従って、従来セラミック多層基板内に内蔵させられなかったチップコイルでも積層コンデンサと同様にセラミック多層基板に内蔵させることができた。 In contrast, in the ceramic multilayer substrate of this example, since a void is formed at the interface between the ceramic laminate and the chip coil by firing, even if shrinkage stress in the thickness direction acts on the ceramic laminate during firing, the ceramic multilayer substrate Compressive stress does not directly act on the chip coil due to the gap between the laminated body and the chip coil, and fluctuations in the characteristics of the chip coil can be suppressed. Therefore, even a chip coil that has not been incorporated in the ceramic multilayer substrate can be incorporated in the ceramic multilayer substrate in the same manner as the multilayer capacitor.
実施例3
本実施形態では、チップ型セラミック電子部品の厚み方向、即ちセラミック積層体の積層方向に離間して上下に配置された端子電極を有するチップ型セラミック電子部品を内蔵する図3に示すセラミック多層基板を作製した。
Example 3
In the present embodiment, the ceramic multilayer substrate shown in FIG. 3 incorporating the chip-type ceramic electronic component having the terminal electrodes arranged vertically apart from each other in the thickness direction of the chip-type ceramic electronic component, that is, the stacking direction of the ceramic laminate. Produced.
本実施形態のセラミック多層基板では、上下の端子電極間で熱応力が発生するが、端子電極間の寸法が小さいため、端子電極間の熱膨張差が小さく、チップ型セラミック電子部品に亀裂が生じたり、チップ型セラミック電子部品が損傷することがない。 In the ceramic multilayer substrate of this embodiment, thermal stress is generated between the upper and lower terminal electrodes, but since the dimension between the terminal electrodes is small, the difference in thermal expansion between the terminal electrodes is small, and the chip-type ceramic electronic component is cracked. And chip-type ceramic electronic components are not damaged.
尚、本発明は、上記各実施形態に何等制限されるものではなく、本発明の趣旨に反しない限り、本発明に含まれる。例えば、上記各実施形態では無収縮工法でセラミック多層基板を製造する場合について説明したが、本発明のセラミック多層基板の製造方法は密着防止剤層を用いてセラミック積層体とチップ型セラミック電子部品の界面に空隙を形成する工程を含んでおれば良く、無収縮工法に限らず、無収縮工法以外の製造方法であっても本願発明に含まれる。この場合には、セラミックグリーン層と密着防止剤層との収縮差に応じて密着防止剤層の大きさを適宜調整する必要がある。例えば密着防止剤層が樹脂によって形成される場合には、樹脂による密着防止剤層の大きさを十分に大きくしなければ所望の大きさの空隙を形成することができない。また、上記各実施形態では密着防止剤層を上下のセラミックグリーンシートに形成したが、片面だけに密着防止剤層を形成しても良い。また、チップ型セラミック電子部品の端子電極は、突起電極ではなく、セラミックグリーン層間の表面電極やセラミックグリーン層に形成されたビアホール電極に直接接続されていても良い。 Note that the present invention is not limited to the above-described embodiments, and is included in the present invention unless it is contrary to the gist of the present invention. For example, in each of the embodiments described above, the case where the ceramic multilayer substrate is manufactured by the non-shrinking method has been described. It is only necessary to include a step of forming voids at the interface, and the present invention is not limited to the non-shrinkage method, and manufacturing methods other than the non-shrinkage method are also included in the present invention. In this case, it is necessary to appropriately adjust the size of the adhesion preventing agent layer according to the shrinkage difference between the ceramic green layer and the adhesion preventing agent layer. For example, when the adhesion preventive agent layer is formed of a resin, a void having a desired size cannot be formed unless the size of the adhesion preventive agent layer made of the resin is sufficiently increased. In each of the above embodiments, the adhesion preventing agent layer is formed on the upper and lower ceramic green sheets. However, the adhesion preventing agent layer may be formed only on one side. Further, the terminal electrode of the chip-type ceramic electronic component may be directly connected to the surface electrode between the ceramic green layers or the via hole electrode formed in the ceramic green layer instead of the protruding electrode.
本発明は、電子機器などに使用されるセラミック多層基板及びその製造方法に好適に利用することができる。 The present invention can be suitably used for a ceramic multilayer substrate used in an electronic device or the like and a manufacturing method thereof.
Claims (13)
上記セラミックグリーン層の上記チップ型セラミック電子部品と接する箇所に密着防止剤層を形成する第1の工程と、
上記セラミックグリーン積層体と上記チップ型セラミック電子部品を焼成して上記密着防止剤層を焼失させる第2の工程と、を含む
ことを特徴とするセラミック多層基板の製造方法。 A ceramic green laminate having a plurality of ceramic green layers and having a conductor pattern, a ceramic sintered body and a terminal electrode, disposed inside the ceramic green laminate, and the terminal electrode and the conductor pattern A method of manufacturing a ceramic multilayer substrate incorporating chip-type ceramic electronic components by simultaneously firing chip-type ceramic electronic components that are electrically connected,
A first step of forming an adhesion preventive agent layer at a portion of the ceramic green layer in contact with the chip-type ceramic electronic component;
And a second step of burning the ceramic green laminate and the chip-type ceramic electronic component to burn off the adhesion preventive agent layer.
上記第1の工程では、上記焼失材料からなるペーストを上記セラミックグリーン層上に塗布し、
上記第2の工程では、上記セラミックグリーン積層体と上記チップ型セラミック電子部品を低酸素雰囲気で焼成した後、これら両者を高酸素雰囲気で再度焼成して上記焼失材料を焼失させる
ことを特徴とする請求項1または請求項2に記載のセラミック多層基板の製造方法。 The adhesion preventing agent does not burn out in a low oxygen atmosphere, but includes a burned material that burns out in a high oxygen atmosphere,
In the first step, a paste made of the burned material is applied on the ceramic green layer,
In the second step, the ceramic green laminate and the chip-type ceramic electronic component are fired in a low oxygen atmosphere, and then both are fired again in a high oxygen atmosphere to burn down the burned material. The manufacturing method of the ceramic multilayer substrate of Claim 1 or Claim 2.
上記セラミック層と上記チップ型セラミック電子部品との界面に空隙が存在すると共に、
上記チップ型セラミック電子部品の端子電極と上記導体パターンとが、上記空隙に形成された突起電極によって電気的に接続されている
ことを特徴とするセラミック多層基板。 Chip-type ceramic electronic comprising a ceramic laminate having a plurality of ceramic layers laminated and having a conductor pattern, and a ceramic sintered body and a terminal electrode electrically connected to the conductor pattern provided at the interface between the upper and lower ceramic layers A ceramic multilayer board comprising components,
While there is a void at the interface between the ceramic layer and the chip-type ceramic electronic component,
A ceramic multilayer substrate, wherein a terminal electrode of the chip-type ceramic electronic component and the conductor pattern are electrically connected by a protruding electrode formed in the gap.
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| CN2009801039203A CN101933409B (en) | 2008-01-31 | 2009-01-23 | Ceramic multilayer substrate manufacturing method, and ceramic multilayer substrate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014216370A (en) * | 2013-04-23 | 2014-11-17 | 株式会社村田製作所 | Laminated inductor element and manufacturing method thereof |
| JPWO2015198870A1 (en) * | 2014-06-23 | 2017-04-20 | 株式会社村田製作所 | Component built-in substrate and method for manufacturing component built-in substrate |
| WO2019130912A1 (en) * | 2017-12-26 | 2019-07-04 | 株式会社村田製作所 | Ceramic layered body |
| US11749533B2 (en) * | 2020-04-21 | 2023-09-05 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing |
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|---|---|---|---|---|
| WO2012157436A1 (en) * | 2011-05-16 | 2012-11-22 | 株式会社村田製作所 | Ceramic electronic component and manufacturing method thereof |
| US9871325B2 (en) * | 2016-01-15 | 2018-01-16 | Te Connectivity Corporation | Circuit board having selective vias filled with lossy plugs |
| JP2017183653A (en) * | 2016-03-31 | 2017-10-05 | スナップトラック・インコーポレーテッド | Multi-layer wiring board for high frequency and its manufacturing method |
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| JPH0888470A (en) * | 1994-09-16 | 1996-04-02 | Taiyo Yuden Co Ltd | Ceramic multilayer substrate for mounting electronic parts and its manufacturing method |
| JPH11340634A (en) * | 1998-05-29 | 1999-12-10 | Kyocera Corp | Laminated body and method for manufacturing the same |
| JP2004247334A (en) * | 2003-02-10 | 2004-09-02 | Murata Mfg Co Ltd | Laminated ceramic electronic component, method of manufacturing the same, and ceramic green sheet laminated structure |
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| JPH0888470A (en) * | 1994-09-16 | 1996-04-02 | Taiyo Yuden Co Ltd | Ceramic multilayer substrate for mounting electronic parts and its manufacturing method |
| JPH11340634A (en) * | 1998-05-29 | 1999-12-10 | Kyocera Corp | Laminated body and method for manufacturing the same |
| JP2004247334A (en) * | 2003-02-10 | 2004-09-02 | Murata Mfg Co Ltd | Laminated ceramic electronic component, method of manufacturing the same, and ceramic green sheet laminated structure |
| WO2006046554A1 (en) * | 2004-10-29 | 2006-05-04 | Murata Manufacturing Co., Ltd. | Ceramic multilayer substrate and its producing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014216370A (en) * | 2013-04-23 | 2014-11-17 | 株式会社村田製作所 | Laminated inductor element and manufacturing method thereof |
| JPWO2015198870A1 (en) * | 2014-06-23 | 2017-04-20 | 株式会社村田製作所 | Component built-in substrate and method for manufacturing component built-in substrate |
| WO2019130912A1 (en) * | 2017-12-26 | 2019-07-04 | 株式会社村田製作所 | Ceramic layered body |
| JPWO2019130912A1 (en) * | 2017-12-26 | 2019-12-26 | 株式会社村田製作所 | Ceramic laminate |
| US11749533B2 (en) * | 2020-04-21 | 2023-09-05 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101933409A (en) | 2010-12-29 |
| CN101933409B (en) | 2013-03-27 |
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