WO2009093171A1

WO2009093171A1 - Improved phase control in hf- or zr-based high-k oxides

Info

Publication number: WO2009093171A1
Application number: PCT/IB2009/050195
Authority: WO
Inventors: Andreas R. A. Zauner; Markus G. A. Muller
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2008-01-23
Filing date: 2009-01-20
Publication date: 2009-07-30
Anticipated expiration: 2010-07-23

Abstract

The present invention relates to a method for fabricating a crystalline layer containing a Hafnium or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride and having a tetragonal crystal structure and a thickness above a critical thickness for an onset of a formation of a non-tetragonalcrystalphase in the oxide layer. The method comprises a first deposition step of an amorphous first layer of either a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride layer with a thickness below a critical thickness value. Subsequently, a first annealing step under annealing conditions suitable for letting the first layer take on a tetragonal crystal structure is performed. Subsequently a sequence of a second deposition and a second annealing step is repeated until a desired total thickness larger than the critical thickness of the oxide layer is reached.

Description

Improved phase control in Hf- or Zr-based High-k oxides

FIELD OF THE INVENTION

The present invention relates to a method for fabricating an oxide layer containing a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride and having a tetragonal crystal structure on a substrate surface with a silicon-type lattice structure.

BACKGROUND OF THE INVENTION

In current semiconductor devices, metal-oxide-semiconductor (MOS) field effect transistors (FETs) use silicon dioxide, or its Si-O-N analogue, as the material for the transistor gate dielectric.

The development of new semiconductor device generations aims at achieving smaller and smaller geometrical parameters. This process is referred to as scaling. In future processing technologies, which are being developed today, the most advanced scaling leads to the requirement of a reduction in thickness of the transistor gate dielectric layer to a value that cannot avoid tunneling of charge carriers and other leakage process across the gate dielectric. The presence of these effects would be prohibitive for the introduction of such highly scaled MOSFETs.

The industry has addressed this issue by looking for alternative dielectric materials with higher dielectric constant than SiO₂, so-called high-k dielectrics. The idea behind using high-k dielectrics is that they allow increasing the physical thickness of the gate dielectric layer while maintaining a given capacitance and at the same time reducing tunneling and leakage effects. As is well known, the capacitance is proportional to the dielectric constant of the capacitor dielectric, but inversely proportional to the thickness of the dielectric. Therefore, high-k materials are promising candidates for the transistor gate dielectric layer in future highly scaled semiconductor devices.

The most serious candidates for use as high-k materials are Hafnium-based materials, such as HfO₂, HfZrO_x and HfSiO(N).

These high-k materials have the disadvantage of occurring in many different crystalline phases, which have different properties. In other words, they are polymorph. The dielectric constant strongly depends on the crystal structure. For HfO₂, a calculation of the dielectric constant in different crystal phases was performed by Zhao et al., Phys. Rev. B65 (2002), 233106. This document is incorporated herein by reference. Zhao et al. calculated the dielectric constant Of HfO₂ for the cubic, tetragonal and monoclinic phases. The dielectric constant is expected to be respectively 29, 70, and 16.

Accordingly, the tetragonal phase is the preferred phase for application in highly scaled semiconductor devices due to its high dielectric constant in comparison with that of the other crystal phases.

A known technique for fabricating Zr- and Hf-based high-k oxides is described in H. Kim et al., Microstructural Evolution OfZrO₂-HfO₂ Nanolaminate Structures Grown by Atomic Layer Deposition, J. Mater. Res., Vol. 19, No. 2, 2004, pp. 643 to 650.

For HfO₂ it has been observed that current processing technology usually leads to a layer with the monoclinic phase for the gate oxide thickness needed in transistor devices (about 2 to 4 nm). It would, therefore, be desirable to provide a method for fabricating Hafnium- and/or Zirconium based high-k oxide layers in the tetragonal phase at any desired thickness.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, a method is provided for fabricating a crystalline oxide layer containing a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate nitride and having a tetragonal crystal structure and a thickness above a critical thickness for an onset of a formation of a non- tetragonal crystal phase in the oxide layer. The method comprises: depositing, in a first deposition step, an amorphous first layer of either a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride layer, the first layer being deposited with a thickness below a critical thickness value, which marks an onset of a formation of a non-tetragonal crystal phase in the oxide layer in subsequent processing; subsequently annealing, in a first annealing step, the first layer under annealing conditions suitable for letting the first layer take on a tetragonal crystal structure; subsequently depositing, in a second deposition step, a second layer of either ra Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate nitride with a thickness below the critical thickness on the first layer, annealing, in a subsequent second annealing step after the second deposition step, the deposited layer structure under annealing conditions suitable for letting also the second layer take on the tetragonal crystal structure, repeating the sequence of the second deposition and the second annealing steps until a desired total thickness larger than the critical thickness of the oxide layer is reached.

The method is based on the recognition that the formation of a purely tetragonal oxide layer is limited, subject to a critical thickness of about 20 Angstrom, which marks an onset of a formation of one or more non-tetragonal crystal phases in the oxide layer in subsequent processing after the deposition, i.e., during an annealing. In the processing technology known today, a purely tetragonal layer with a thickness beyond this thickness is prohibited by the existence of the critical oxide layer thickness. It has been observed that non-tetragonal crystal phases are formed to an undesirable extent not necessarily immediately in the deposition of the oxide layer, but during subsequent processing steps, which include annealing steps typical for semiconductor device fabrication.

The method of the present invention overcomes the limitations of the critical thickness for applications in the semiconductor industry, which require high-k oxide layer thicknesses larger than the critical thickness.

With the method of the first aspect of the present invention, it becomes possible to fabricate purely tetragonal Hafnium oxide or Zirconium oxide or Hafnium- Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride mono laminate or heterolaminate layers with a desired thickness above the critical thickness.

Note that the method of the invention implies a link between deposition steps and the respective subsequent annealing steps. For the critical thickness to be considered as an upper limit in the respective deposition step is dependent on the post-deposition annealing temperature, which is to be used in the annealing steps.

In the following, embodiments of the method of the first aspect of the invention will be described. The additional features of the embodiments can be combined with each other to form additional embodiments of the method of the first aspect of the invention unless the embodiments are described as forming alternatives to each other.

In some embodiments, a substrate is provided for the first deposition step, which substrate has a surface layer, which is also referred to as an interfacial layer. The first layer is subsequently deposited onto the interfacial layer. A suitable material of the interfacial layer is silicon oxide or silicon oxynitride. The thickness of this layer is in some embodiments in the range between 0.2 and 1.5 nm, suitably between 0.4 and 1.0 nm.

For the mentioned materials of the interfacial layer, substrates, which can be advantageously used for an application of the method of the invention are made of Si or SiGe. These substrate materials are also most interesting for industrial application. SiGe is preferably used with a moderate Ge content of less than 30%. The substrate may also contain carbon, but preferably at a low concentration. A certain crystalline orientation of the substrate surface used for deposition is not a requirement for the applicability of the invention. The use of the mentioned substrate materials has the advantage, that the interfacial layer can be fabricated easily by performing a wet chemical process such as an ozone rinse or a thermal process known to result in such an interfacial layer.

Other substrate materials could be used as well in embodiments using the interfacial layer. For such substrates, for example Ge or GaAs, the interfacial layer would have to be engineered in a different manner. For Ge, e.g., a few monolayers of Si can be deposited, for instance by an epitaxial deposition process, which is then transformed into the desired interfacial layer. Of course, the material of the interfacial layer could also be deposited directly, where a suitable process exists.

In one embodiment of the method of the invention, repeating the sequence of the second deposition and annealing steps comprises depositing the same material as that of the underlying, previously deposited and annealed layer. In this embodiment, a mono laminate with tetragonal crystal structure is thus fabricated. That is, the oxide material is the same throughout the full thickness of the oxide layer.

In an alternative embodiment, two or more layers in a row are deposited from the same material before changing to another material for a further layer. This way, the oxide layer will comprise larger thickness ranges with identical materials while exhibiting an overall heterolaminate structure.

As another alternative, performing or repeating the sequence of the second deposition and annealing steps may comprise depositing a different material of the group formed by a Hafnium oxide, a Zirconium oxide and a Hafnium-Zirconium oxide or a

Hafnium silicate or a Hafnium silicate nitride on the first layer or on a subsequently grown oxide layer. In this embodiment, the material changes from layer to layer of the heterolaminate. The Zirconium oxide is in one embodiment ZrO₂. The Hafnium oxide is in one embodiment HfO₂. The critical thickness may vary slightly with the individual processing conditions used for the oxide layer fabrication. In embodiments used by the inventors, the first layer and the at least one second layer are each deposited with a thickness of no more than 2 nm. In order to be safely below the critical thickness for the onset of non-tetragonal crystal phase formation in the oxide layer, the first layer and/or the at least one second layer can be deposited with a thickness of up to 1 nm. As will be shown in more detail in the context of the description of the enclosed Figures, these thickness ranges have been successfully used in the deposition of hetero stacks and mono laminate stacks with tetragonal crystal structure.

Preferably, the first and the at least one second layer are each deposited at a temperature between 300 and 450 ⁰C. These rather low temperatures typically result in the initial formation of an amorphous layer, which is subsequently crystallized to assume the tetragonal crystal structure in a post-deposition annealing step. The annealing in the first and/or second annealing step is preferably performed at a temperature of between 500 and 1000 ⁰C. This temperature range allows densifying the initially amorphous oxide material and effecting a crystallization where necessary. The temperature range between 500 and 700 ⁰C seems most suitable for these purposes.

In a second aspect of the invention, a method for fabricating a semiconductor device is provided. The method comprises a step of fabricating an oxide layer according to the method of claim 1, i.e. a crystalline oxide layer containing a Hafnium oxide or a Zirconium oxide, or a Hafnium-Zirconium oxide, and having a tetragonal crystal structure and a thickness above a critical thickness for an onset of a formation of a non-tetragonal crystal phase in the oxide layer. Embodiments of the method of the second aspect of the invention contain the additional features of the embodiments of the method of the first aspect of the invention, or a combination thereof, where not excluded due to the alternative nature of the different embodiments.

With the present invention, high-k dielectrics finally become a serious alternative for use in modern CMOS technology. The method of the second aspect of the invention allows integrating high-k dielectric phases of Hafnium oxide, Zirconium oxide or Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride in a semiconductor device, such as a MOSFET, with a thickness required at advanced technology nodes, such as the CMOS process technology at the 45 nm node and below. The method fulfils a long-felt need to produce the mentioned oxide materials with the crystalline phase that provides the highest dielectric constant at a desired and suitable thickness for device applications. This invention therefore boosts the integration of high-k dielectrics into the industrial processing technology. Technological difficulties have so far delayed the integration of these materials and triggered the application of techniques that extended the use of SiO₂ to the advanced technology nodes currently used.

According to a third aspect of the invention, a semiconductor device is provided that comprises an oxide layer on a substrate, the oxide layer containing a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide, the oxide layer being of a tetragonal crystal structure and having a thickness larger than 2 nm. The semiconductor device of the third aspect of the invention for the first time provides a Hafnium oxide or a Zirconium oxide or a mixed Hafnium- Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride layer, which at the same time has a tetragonal crystal structure and a thickness that exceeds the critical thickness for the onset of the formation of non-tetragonal crystal phases as described earlier. The semiconductor device thus represents a major advance in the present technology field.

Embodiments of the semiconductor device of the present invention incorporate the processing results achieved with the method embodiments described hereinbefore and hereinafter. In particular, the oxide layer may take the form of a mono laminate or of a heterolaminate layer structure. Major device applications are MOSFETs and other semiconductor devices containing capacitive structures, such as semiconductor memory devices having a MIM (metal-insulator-metal), MIS (metal-insulator-semiconductor) or SIS (semiconductor- insulator-semiconductor) structure. The semiconductor device is typically provided in an integrated circuit. However, an application as a stand-alone semiconductor device is not excluded.

Preferred embodiments of the invention are also defined in the dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. In the following drawings

Figs. 1 to 3 show illustrations of a cubic, tetragonal and monocline crystal structure; Fig. 4 shows a schematic phase diagram illustrating crystal phases taken on by Hafnium-based oxide materials in dependence on the layer thickness t of the oxide layer and on the post-deposition annealing temperature Ta.

Fig. 5 shows X-ray diffraction patterns of four different HfSiON layers with a Hf-content of 70 % with different thicknesses;

Fig. 6 shows a flow diagram of an embodiment of a method for forming an oxide layer according to the first aspect of the invention; and

Fig. 7 shows a schematic cross-sectional view of a capacitive layer structure for use in device applications.

DETAILED DESCRIPTION OF EMBODIMENTS

Figs. 1 to 3 show illustrations of a cubic, tetragonal and monocline crystal structure. Hafnium-based high-k dielectrics such as HfO₂, HfZrO_x, HfSiO(N) are often polymorph, typically exhibiting a cubic phase, labelled C in Fig. 1 , a tetragonal phase T as well as a monoclinic phase M, possibly in combination with amorphous regions, in a single layer. As mentioned in the introductory description, theses phases have different dielectric constants. In all these materials, the dielectric constant of the tetragonal phase is highest. For the case OfHfO₂, the dielectric constant reported for the tetragonal phase is as high as 70, compared to values of 29 and 16 for the cubic and monoclinic phases, respectively. Therefore, purely tetragonal layers of these materials would be preferred for use in highly scaled CMOS devices for integrated circuits.

Fig. 4 shows a schematic phase diagram illustrating crystal phases taken on by Hafnium-based oxide materials in dependence on the layer thickness t of the oxide layer and on the post-deposition annealing temperature T_a. In the diagram of Fig. 4, the thickness t of the oxide layer is shown on the abscissa (x-axis), while the post-deposition annealing temperature T_a is plotted on the ordinate (y-axis). Absence of an additional anneal is to be read as a level of T_a, which coincides with the abscissa.

The phase diagram is purely schematic. The abscissa and ordinate represent arbitrary linear units of the thickness and the annealing temperature, respectively. Three different regions A, M and T are identified in the phase diagram of Fig. 4 and illustrate respective (t,Ta)-parameter intervals, which give rise to a layer with a crystal structure of the corresponding phases. The different regions are labeled A, M and T represent thickness and post-deposition annealing-temperature domains, in which the amorphous (A), monoclinic (M) and tetragonal (T) phases are created. Limits between the different regions are indicated as dashed lines AM, TM, and AT. The line AM represents the phase border between the amorphous and the monoclinic phases. The line TM represents the phase border between the tetragonal and the monoclinic phases. The line AT represents the phase border between the amorphous and the tetragonal phases. Crossing a dashed line corresponds to a change of phase. At a "triple point" ATM, all three phase regions A, T, and M are immediately adjacent to each other in the phase diagram.

As can be deduced from the schematic phase diagram of Fig. 4, the amorphous structure is favored at all layer thicknesses for lower annealing temperatures. In the absence of an anneal, a critical thickness tc3 exists for a transition from the amorphous to the monoclinic phase. Increasing the annealing temperature at given thickness values between critical thickness values tci and tc₂ eventually results in the formation of a tetragonal crystal phase in a certain temperature range. As can be seen from the phase diagram of Fig. 4, fabricating a layer with the tetragonal phase requires very specific combinations of layer thickness and annealing temperatures in order to avoid the presence of monoclinic or amorphous phases in the layer. For each annealing temperature above the range leading to amorphous structures, there is a certain critical layer thickness between the values tci and tc₂, at which the incorporation of a monoclinic crystal phase begins. The critical layer thickness decreases with increasing annealing temperature Ta. With layer thicknesses above the critical thickness tc₂, no tetragonal phase can be fabricated, but only an amorphous or monoclinic phase, depending on the annealing temperature used in correspondence with the phase border indicated by AM.

Increasing the annealing temperature for a given layer thickness below the critical thickness to an annealing temperature that is higher than the temperature values suitable for fabricating the tetragonal structure will also lead to a monoclinic crystal structure. For higher layer thicknesses, a tetragonal crystal structure is not present for any annealing temperature Ta. The structure of the fabricated layer is either amorphous for lower annealing temperatures used, or monoclinic for higher annealing temperatures. With increasing thickness towards a thickness t2, the annealing temperature, at which the phase switches from amorphous to monoclinic decreases with increasing layer thickness. Fig. 5 shows X-ray diffraction measurements of Hafnium silicate nitride (HfSiON) films with a Hf-content of 70 %, which were all subjected to a post-deposition annealing step at T_a = 900 ⁰C for about 7 minutes. The temperature T_a and the layer thickness are the major parameters determining the result. Typically, the annealing atmosphere is is an inert N₂ ambient atmosphere. It is also possible to include a small partial pressure of O₂ of the order of less than 1%, suitably 0.1% to 1% of the N₂ partial pressure. This will cure defaults in the High-K material, but is not expected to change recrystallization behavior. An alternative to a N₂ ambient if nitridation of the film is wanted, is a NH₃ ambient. It should be noted that in the latter case, the incorporation of N can modify the crystallization behavior. For instance for HfSiO_x, N it is used to prevent segregation of SiO₂ and HfO₂.

Typical further process parameters for the post-deposition anneal after High-K deposition are: Temperature 500-800⁰C, Pressure: 0.1-10 Torr, Flow: 0.1 to 10 slm (standard liter per minutes), Time: 10s to several minutes The layers used in these experiments were fabricated with thicknesses in the range between t = 10 A to t = 100 A. It is well known in the art that a monoclinic phase of this material exhibits an X-ray diffraction peak at slightly above 30°, whereas the tetragonal phase exhibits a dominating peak at between 25 and 30°. Other peaks shown in the diffraction measurements need not be discussed in the present context.

The relative intensities of the different peaks are an indicator for the proportions of the different phases in the layer volume, which was monitored by the X-ray beam. As can be seen from a comparison of the diffraction measurements obtained from samples with different thicknesses, the tetragonal phase is very strongly dominating at a thickness of 10 A. It has lost its dominance already at a thickness of 20 A, where the peak of the monoclinic phase is stronger than that of the tetragonal phase. The diffraction pattern of the oxide layer with a thickness of 20 A is repeated for layers with higher thicknesses with only minor modifications.

This experiment clearly demonstrates the presence of a critical thickness for the onset of the formation of a non-tetragonal phase in the oxide layer. The critical thickness has a value between 10 and 20 A. It appears at if the tetragonal phase is energetically more favorable below the critical layer thickness, and as if the layer will therefore preferably crystallize in this phase during the annealing step.

This crystallization behavior was confirmed by observations on hetero laminates consisting of 10 A interfacial layer Of HfO₂ and a 15 and 20 A ZrO₂ layer on top. It should be noted that a monoclinic phase would have been expected for a monolithic layer of the same total thickness between 25 and 30 A. Thus, with the method of the present invention it becomes possible to generate thicker oxide layer films in the desired tetragonal phase. Theoretical predications of the dielectric values for pure ZrO₂ (but not for mixed HfZrO_x films) have been made and resulted in values of 37, 47 and 20 for the cubic, tetragonal, and monoclinic phases, respectively. In ZrO₂ as well as in HfO₂ZZrO₂ mixtures, the tetragonal phase has a lower dielectric constant than in pure HfO₂. In other words, pure HfO₂ in the tetragonal phase has the highest dielectric constant in the range of materials considered in the present context. However, a bilayer of HfO₂/ZrO₂ has advantageous properties concerning the Jg verses equivalent oxide thickness trade-off in comparison with HfZrO_x. Therefore, in device application a HfO₂/ZrO₂ stack is preferred over a HfZrO_x mixture at present. The following description refers to Figs. 6 and 7 in parallel.

Fig. 6 shows a flow diagram of a method for fabrication an oxide layer 104 containing a Hafnium oxide or Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium Silicate Nitride (HfSiON) film. Fig. 7 shows a schematic cross- sectional view of a capacitive layer structure 100 for use in device applications. The method is started in a step SlO.At this point, a substrate 102 is provided for the first deposition step. The substrate may have a surface layer (not shown), which is also referred to as an interfacial layer. A suitable material of the interfacial layer is silicon oxide or silicon oxynitride. The thickness of this layer is in some embodiments in the range between 0.2 and 1.5 nm, suitably between 0.4 and 1.0 nm. In a subsequent step S 12, which forms a first deposition step, a first layer

104.1 of either a Hafnium oxide, or a Zirconium oxide, or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium Silicate Nitride is deposited at a thickness below the critical thickness value. In particular, the thickness of the first layer 104.1 is below 20 A. In a particular embodiment, a thickness of 10 A is used. The first layer is deposited at a temperature and thickness that results in an amorphous structure. A suitable deposition temperature for the first deposition step S12 is in the range of 300 to 450 ⁰C.

The oxide layer 104.1 is deposited on the substrate 102. Where the interfacial layer is present, the first layer 104.1 is deposited onto the interfacial layer. The substrate 102 may be a silicon substrate, for instance a silicon wafer, as used in the semiconductor industry for the fabrication of integrated circuits. Other substrate materials may be used. The invention does not rely on a particular substrate material.

Subsequently, in a first annealing step S14, the first layer 104.1 is subjected to an annealing at a temperature between 500 and 1000 ⁰C, suitably between 500 ⁰C and 700 ⁰C. Further suitable parameters for this post-deposition annealing step have been specified previously within this specification. This leads to a densification and crystallization of the initially amorphous film 104.1 in the tetragonal crystal structure. Suitable annealing times range between 5 and 20 minutes. The oxide layer 104 a (pure) tetragonal crystal structure and a thickness above a critical thickness for an onset of a formation of a non-tetragonal crystal phase in the oxide layer.

Subsequently, in a second deposition step S16, a second layer 104.2 of either a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium Silicate Nitride with a thickness below the critical thickness is deposited on the first layer 104.1. This is followed by a second annealing step S 18, in which the deposited layer structure is subjected to annealing conditions suitable for letting also the second layer take on the tetragonal crystal structure. The second deposition step may result in either an amorphous film or a tetragonal- like film.

After the second annealing step S18, both deposited layers 104.1 and 104.2 are in a purely tetragonal or at least strongly dominant tetragonal phase. In a subsequent step S20, it is checked whether the desired layer thickness has been reached by the previous first and second deposition steps S 12 and S 16. Obviously, this step S20 can be omitted if the desired layer thickness is known and the thickness deposited with each deposition step is known as well. However, the step S20 is shown in Fig. 7 mainly for the purpose of illustrating the possibility of repeatedly performing the sequence of the second deposition step S16 and the second annealing step S 18, in order to achieve a desired layer thickness of the oxide layer. The processing stops with the annealing of the final layer of the laminate structure, which in the embodiment of Fig. 8 is a layer 104.3. Subsequently, further layers can be deposited, such as a gate layer 106 fabricated of polysilicon or other suitable materials. With the described method, mono laminates as well as hetero laminates can be fabricated.

The processing is then continued with the deposition of further functional layers. In a MOSFET, a layer 106 of metal or doped polysilicon is deposited.

Fig. 7 also represents the structure of other capacitive structures such as a MIM or MIS structure, which are for instance used for semiconductor memory applications. In such an embodiment, the substrate 102 and the layer 106 form capacitor electrodes. The processing according to the embodiment of Fig. 6 can be summarized in table form as follows:

SlO Start

S 12 First deposition step of oxide layer below critical thickness

S 14 First post-deposition annealing step

S 16 Second deposition step of oxide layer below critical thickness

S 18 Second post-deposition annealing step

S20 Check if desired thickness has been reached

S22 End

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.

Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A method for fabricating a crystalline oxide layer (104) containing a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride and having a tetragonal crystal structure (T) and a thickness above a critical thickness (tci, tc₂) for an onset of a formation of a non-tetragonal crystal phase (M) in the oxide layer, the method comprising: depositing, in a first deposition step (S 12), an amorphous first layer (104.1) of either a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride layer on a substrate (102) , the first layer being deposited with a thickness below a critical thickness value (tci, to), which marks an onset of a formation of a non-tetragonal crystal phase in the oxide layer in subsequent processing; subsequently annealing, in a first annealing step (S14), the first layer (104.1) under annealing conditions suitable for letting the first layer take on a tetragonal crystal structure; subsequently depositing, in a second deposition step (S 16), a second layer (!04.2) of either a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride with a thickness below the critical thickness (tci, t_C2) on the first layer (104.1); annealing, in a subsequent second annealing step (S 18) after the second deposition step (S 16), the deposited layer structure under annealing conditions suitable for letting also the second layer take on the tetragonal crystal structure (T); and repeating the sequence of the second deposition (S 16) and the second annealing (S 18) steps until a desired total thickness larger than the critical thickness (tci, tc₂) of the oxide layer is reached.

2. The method of claim 1, wherein performing or repeating the sequence of the second deposition and annealing steps comprises depositing the same material as that of the underlying, previously deposited and annealed layer.

3. The method of claim 1, wherein performing or repeating the sequence of the second deposition and annealing steps comprises depositing a different material of the group of a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride on the first layer or on a subsequently grown oxide layer.

4. The method of claim 1 , wherein the Zirconium dioxide is ZrO₂.

5. The method of claim 1, wherein the Hafnium dioxide is HfO₂.

6. The method of claim 1 , wherein the first layer and the at least one second layer are each deposited with thickness of no more than 2 nanometer.

7. The method of claim 1, wherein the first layer and the at least one second layer are each deposited with thickness of up to 1 nanometer.

8. The method of claim 1, wherein the first layer and the at least one second layer are each deposited at a temperature between 300 and 450 ⁰C.

9. The method of claim 1 , wherein the first or second annealing step is performed at a temperature of between 500 and 1000 ⁰C.

10. The method of claim 8, wherein the first or second annealing step is performed at a temperature between 500 and 700 ⁰C.

11. The method of claim 1, further comprising, before the first deposition step, a step of providing a substrate that has a surface layer of silicon oxide or silicon oxynitride.

12. A method for fabricating an semiconductor device, comprising a step of fabricating on a substrate (102) a crystalline oxide layer (104) containing a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride and having a tetragonal crystal structure and a thickness above a critical thickness (tci, tc₂) for an onset of a formation of a non-tetragonal crystal phase in the oxide layer, according to claim 1.

13. A semiconductor device (100) comprising an oxide layer (104) on a substrate (102), the oxide layer containing a Hafnium oxide or a Zirconium oxide or a Hafnium- Zirconium oxide, the oxide layer being of a tetragonal crystal structure (T) and having a thickness (t) larger than 2 nanometers.

14. The semiconductor device of claim 13, wherein the oxide layer (104) is a heterolaminate layer (104.1 to 104.3) comprising a layer sequence made of at least two different materials, each layer being made of either a Hafnium oxide or a Zirconium oxide or a Hafnium-Zirconium oxide or a Hafnium silicate or a Hafnium silicate nitride layer.

15. The semiconductor device (100) of claim 13, which is a metal-oxide- semiconductor field-effect transistor, and wherein the oxide layer forms a gate insulation layer.

16. The semiconductor device (100) of claim 13, which is a capacitor, and wherein the oxide layer forms a dielectric layer arranged between two capacitor electrodes.

17. An electronic circuit comprising a semiconductor device according to claim

13.