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WO2009079179A3 - Placement of an integrated circuit - Google Patents

Placement of an integrated circuit Download PDF

Info

Publication number
WO2009079179A3
WO2009079179A3 PCT/US2008/084766 US2008084766W WO2009079179A3 WO 2009079179 A3 WO2009079179 A3 WO 2009079179A3 US 2008084766 W US2008084766 W US 2008084766W WO 2009079179 A3 WO2009079179 A3 WO 2009079179A3
Authority
WO
WIPO (PCT)
Prior art keywords
geometrical elements
integrated circuit
geometrical
elements
placement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/084766
Other languages
French (fr)
Other versions
WO2009079179A2 (en
Inventor
Czeslaw Andrzej Ruszowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PL384063A external-priority patent/PL218258B1/en
Priority claimed from US12/195,441 external-priority patent/US7851255B2/en
Application filed by Individual filed Critical Individual
Publication of WO2009079179A2 publication Critical patent/WO2009079179A2/en
Publication of WO2009079179A3 publication Critical patent/WO2009079179A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10W70/65—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H10W72/00—
    • H10W72/851—
    • H10W90/701—
    • H10W99/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/168—Wrong mounting prevention
    • H10W72/07227—
    • H10W72/07236—
    • H10W72/07327—
    • H10W72/07336—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.
PCT/US2008/084766 2007-12-17 2008-11-26 Placement of an integrated circuit Ceased WO2009079179A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
PL384063A PL218258B1 (en) 2007-12-17 2007-12-17 The manner of positioning of enclosure of an electronic element, especially integrated system with single- or multi-layer or package structure on silicone or ceramic substrate type IC, SiP or MCM
PLP384063 2007-12-17
US12/195,441 US7851255B2 (en) 2008-08-21 2008-08-21 Placement of an integrated circuit
US12/195,441 2008-08-21

Publications (2)

Publication Number Publication Date
WO2009079179A2 WO2009079179A2 (en) 2009-06-25
WO2009079179A3 true WO2009079179A3 (en) 2009-08-13

Family

ID=40796077

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/084766 Ceased WO2009079179A2 (en) 2007-12-17 2008-11-26 Placement of an integrated circuit

Country Status (1)

Country Link
WO (1) WO2009079179A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121654A (en) * 1982-01-12 1983-07-20 Seiko Epson Corp Package ic
JPS6218722A (en) * 1985-07-18 1987-01-27 Toshiba Corp Semiconductor device
US20010016435A1 (en) * 2000-02-23 2001-08-23 Takuma Fujimura IC socket for surface-monuting semiconductor device
US20060118971A1 (en) * 2003-02-06 2006-06-08 David Gracias Fabricating stacked chips using fluidic templated-assembly

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121654A (en) * 1982-01-12 1983-07-20 Seiko Epson Corp Package ic
JPS6218722A (en) * 1985-07-18 1987-01-27 Toshiba Corp Semiconductor device
US20010016435A1 (en) * 2000-02-23 2001-08-23 Takuma Fujimura IC socket for surface-monuting semiconductor device
US20060118971A1 (en) * 2003-02-06 2006-06-08 David Gracias Fabricating stacked chips using fluidic templated-assembly

Also Published As

Publication number Publication date
WO2009079179A2 (en) 2009-06-25

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