[go: up one dir, main page]

WO2009067381A1 - Procédé de commande d'un micro chargement de gravure pour une couche contenant du tungstène - Google Patents

Procédé de commande d'un micro chargement de gravure pour une couche contenant du tungstène Download PDF

Info

Publication number
WO2009067381A1
WO2009067381A1 PCT/US2008/083412 US2008083412W WO2009067381A1 WO 2009067381 A1 WO2009067381 A1 WO 2009067381A1 US 2008083412 W US2008083412 W US 2008083412W WO 2009067381 A1 WO2009067381 A1 WO 2009067381A1
Authority
WO
WIPO (PCT)
Prior art keywords
component
recited
features
etch
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/083412
Other languages
English (en)
Inventor
Wonchul Lee
Qian Fu
Shenjian Liu
Bryan Pu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Priority to US12/744,012 priority Critical patent/US8518282B2/en
Priority to CN200880117545.3A priority patent/CN101952944B/zh
Publication of WO2009067381A1 publication Critical patent/WO2009067381A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10P50/267
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32138Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H10P50/269

Definitions

  • the present invention relates to etching a conductive layer having features of different aspect ratios. More specifically, the present invention relates to reducing microloading during the etching of a conductive layer having both open and dense features.
  • a semiconductor device may have both open and dense features. The open features have wider widths, while the dense features have narrower widths. As a result, the semiconductor device may have features of different aspect ratios.
  • the aspect ratio of a feature is the ratio between the height and the width of the feature. Thus, if the heights of all the features of a semiconductor device are approximately the same, then the open features have relatively low aspect ratios, while the dense features have relatively high aspect ratios.
  • a method for controlling etch rate microloading for a tungsten-containing layer masked by both narrow and wide features is provided.
  • An etch gas with a tungsten etch component and a deposition component which produces non conformal deposition is provided.
  • a plasma is formed from the provided etch gas.
  • a tungsten containing layer is etched with the plasma formed from the provided etch gas.
  • a method for etching a tungsten containing layer through a mask with wide and narrow features is provided.
  • An etch gas with a tungsten etch component and a deposition component which produces non conformal deposition is provided, wherein the deposition component comprises a silicon containing component and an oxygen containing component.
  • a plasma is formed from the provided etch gas.
  • a tungsten containing layer is etched with the plasma formed from the provided etch gas.
  • An apparatus for etching a tungsten containing layer through a mask with wide and narrow features comprising a plasma reactor and computer readable code for providing a tungsten etch gas and a deposition gas, transforming the gas mixture into a plasma, and for stopping the etch gas mixture gas flow.
  • FIG. 1 is a high level flow chart of an embodiment of the invention.
  • FIG. 2 is a schematic view of a plasma processing chamber that may be used for etching.
  • FIGS. 3A-B illustrate a computer system, which is suitable for implementing a controller used in embodiments of the present invention.
  • FIGS. 4A-C are schematic views of a stack processed according to an embodiment of the invention.
  • etch rate microloading is becoming a common problem. Due to diffusion limitations, the etching chemicals are able to go into the wider open features faster than into the narrower dense features. Similarly, the byproducts of the etch process go out of the wider open features faster than the out of narrower dense features. As a result, open features, i.e., features with wider widths, etch faster than dense features, i.e., features with narrow widths.
  • FIG. 1 is a high level flow chart of a process used in an embodiment of the invention.
  • a mask layer patterned with features of different aspect ratios i.e., open and dense features
  • the open and dense features will eventually be etched into the tungsten containing layer.
  • the open (wider) and dense (narrower) features are patterned using a mask over a tungsten layer.
  • An etch gas is provided (step 110) which contains a tungsten etch component and a deposition component.
  • a plasma is formed from this etch gas (step 120), and is used to etch the wider and narrower features into the tungsten-containing layer (step 130).
  • the etching of the tungsten containing layer is aspect ratio dependent because the open (wider) features are etched into the tungsten containing layer faster than the dense (narrower) features due, in part, to etch component diffusion limitations.
  • the deposition of the depositing component is also aspect ratio dependent, so the deposition component deposits more thickly on the bottom surfaces of wide features than the bottom of narrow features due, in part, to depositing component diffusion limitations. This selective deposition in the wide features inhibits etching of the tungsten containing layer in the wide features relative to the narrow features. The etch rate between the wide and narrow features may thus be balanced and etch rate microloading may be eliminated or even reversed.
  • FIG. 2 is a schematic view of a plasma processing system 200, including a plasma processing tool 201.
  • the plasma processing tool 201 is an inductively coupled plasma etching tool and includes a plasma reactor 202 having a plasma processing chamber 204 therein.
  • TCP transformer coupled power
  • the TCP power controller 250 sets a set point for TCP power supply
  • An RF transparent window 254 is provided to separate TCP coil 253 from plasma chamber 204 while allowing energy to pass from TCP coil 253 to plasma chamber 204.
  • An optically transparent window 265 is provided by a circular piece of sapphire having a diameter of approximately 2.5 cm (1 inch) located in an aperture in the RF transparent window 254.
  • the bias power controller 255 sets a set point for bias power supply
  • a chuck electrode 208 located within the plasma chamber 204 creating a direct current (DC) bias above electrode 208 which is adapted to receive a substrate 206, such as a semiconductor wafer work piece, being processed.
  • DC direct current
  • a gas supply mechanism or gas source 210 includes sources of gases attached via a gas manifold 217 to supply the proper chemistry required for the processes to the interior of the plasma chamber 204.
  • One source of gas may be the etch gas source 215 that supplies the proper chemistry for etching the tungsten containing layer.
  • Another source of gas may be the deposition gas source 216 that supplies the proper chemistry for depositing onto the tungsten containing layer.
  • a gas exhaust mechanism 218 includes a pressure control valve 219 and exhaust pump 220 and removes particles from within the plasma chamber 204 and maintains a particular pressure within plasma chamber 204.
  • a temperature controller 280 controls the temperature of heaters 282 provided within the chuck electrode 208 by controlling a heater power supply 284.
  • the plasma processing system 200 also includes electronic control circuitry 270.
  • the plasma processing system 200 may also have an end point detector 260.
  • Figures 3A and 3B illustrate a computer system, which is suitable for implementing the control circuitry 270 used in one or more embodiments of the present invention.
  • Figure 3A shows one possible physical form of the computer system 300.
  • the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer.
  • Computer system 300 includes a monitor 302, a display 304, a housing 306, a disk drive 308, a keyboard 310, and a mouse 312.
  • Disk 314 is a computer-readable medium used to transfer data to and from computer system 300.
  • Figure 3B is an example of a block diagram for computer system 300.
  • Processor(s) 322 are coupled to storage devices, including memory 324.
  • Memory 324 includes random access memory (RAM) and read-only memory (ROM).
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • Both of these types of memories may include any suitable of the computer-readable media described below.
  • a fixed disk 326 is also coupled bi-directionally to CPU 322; it provides additional data storage capacity and may also include any of the computer-readable media described below.
  • Fixed disk 326 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 326 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 324.
  • Removable disk 314 may take the form of any of the computer-readable media described below.
  • CPU 322 is also coupled to a variety of input/output devices, such as display 304, keyboard 310, mouse 312, and speakers 330.
  • an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch- sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers.
  • CPU 322 optionally may be coupled to another computer or telecommunications network using network interface 340. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above- described method steps.
  • embodiments of the present invention may execute solely upon CPU 322 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
  • embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer- implemented operations.
  • the media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts.
  • Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto- optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application- specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices.
  • Examples of computer code include machine code, such as produced by a compiler, and files containing higher level of code that are executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
  • FIGS. 4A-C are schematic views of a stack processed according to an embodiment of the invention.
  • a mask layer patterned with features of different aspect ratios i.e., open and dense features
  • FIG. 4A is a schematic cross-sectional illustration of a stack 400 with a substrate 410, over which an etch layer 420 is provided.
  • the etch layer 420 is a tungsten-containing layer, preferably tungsten (W).
  • a mask layer 430 is present over the tungsten-containing layer 420.
  • the mask layer 430 may be a carbon-based mask, such as a mask containing CH, CF, amorphous carbon, or the like.
  • the mask layer 430 may be an inorganic hard mask, such as silicon dioxide, silicon nitride, or the like.
  • the mask layer is SiO-based, such as thermal oxide or TEOS.
  • the mask layer 430 is patterned with both open features 440 and dense features 450.
  • the widths 441 of the open features 440 are relatively greater than the widths 451 of the dense features 450.
  • the open features 440 have wider openings than the dense features 450.
  • the open features 440 may also be referred to as the "wider” or “wide” features
  • the dense features 450 may also be referred to as the "narrower" or “narrow” features.
  • the open or wider features 440 are at least 2 times wider than the dense or narrower features 450. More preferably, the open or wider features 440 are at least 5 times wider than the dense or narrower features 450. Most preferably, the open or wider features 440 are at least 10 times wider than the dense or narrower features 450.
  • An etch gas is provided comprising a mixture of a tungsten etch component and a deposition component (step 110).
  • the deposition component comprises a silicon-containing component and an oxygen containing component.
  • the silicon-containing component of the etch gas may be any gaseous chemical containing silicon.
  • the silicon-containing component may be an organic siloxane; that is, a chemical compound of silicon, oxygen, and carbon based on the structural unit R 2 SiO where R is an alkyl group such as methyl, ethyl, propyl, or the like, and which has a boiling point at or below 150 degrees Celsius.
  • suitable siloxane compounds include but are not limited to tetramethyldisiloxane [((CHs) 2 SiH) 2 O], pentamethyldisiloxane, and hexamethyldisiloxane.
  • the silicon- containing compound may also be a chemical compound similar to siloxane but where the bridging oxygen is replaced with a nitrogen (as in the examples of tetramethyldisilazane, hexamethyldisilazane, or N-methyl-N-silyl-Silanamine), or compounds of silicon, carbon, and hydrogen such as disilylacetylene [C 2 H 6 Si 2 ] .
  • the silicon-containing component may be an organosilicon compound based on the structural unit SiA x Z (4 _ x) where A is selected from the group H, F, Cl, Br, or I, where Z is an alkyl group such as methyl, ethyl, propyl, or the like, where x may vary from zero to four, and which has a boiling point at or below 150 degrees Celsius.
  • the silicon-containing component may be dimethylsilane [(CH 3 ) 2 SiH 2 ] where x equals two, A is hydrogen, and Z is a methyl group.
  • the silicon-containing component may be dichlorodimethylsilane [(CH 3 ) 2 SiCl 2 ] where x equals two, A is chlorine, and Z is a methyl group.
  • the silicon-containing component may be tetramethylsilane [(CH 3 ) 4 Si] where x equals zero and Z is an methyl group.
  • the silicon containing component is silane-based; that is, a silane, or a halogenated silane.
  • a silane is comprised of SiH 4 or higher silanes with the empirical formula Si x Hp x+2) where x has a minimum value of one.
  • a halogenated silane is comprised of a compound with the empirical formula Si x A y H (2x+2 _ y) , where A is selected from the group F, Cl, Br, or I, and x and y may each have a minimum value of one. More preferably, the silane-based silicon containing component is a halogenated silane. Most preferably, the silane-based silicon containing component is silicon tetrachloride (SiCU).
  • the oxygen containing component of the deposition component may be provided via the silicon containing component process gas.
  • the oxygen containing component of the deposition component may be the oxygen from the siloxane.
  • the oxygen containing component of the deposition component may be supplied separately from the silicon containing component. That is, the oxygen containing component may contain elemental oxygen but not silicon.
  • the oxygen containing component may be CO, CO 2 , O 3 , H 2 O, or O 2 .
  • the oxygen for the oxygen containing component of the deposition component may be from both silicon containing process gas, such as a siloxane, and a separate oxygen containing component, which does not contain silicon.
  • the oxygen containing component of the deposition component is from a separate oxygen containing component, which contains elemental oxygen but not silicon.
  • the oxygen containing component is O 2 .
  • a plasma is formed from the provided etch gas mixture (step 120) and a tungsten containing layer is etched (step 130).
  • FIG. 4B shows a schematic cross- sectional illustration of the stack 400 during the etch process (step 130).
  • the etching of the tungsten containing layer 420 is aspect ratio dependent due, in part, to the etch components being diffusion limited.
  • the open (wider, low aspect ratio) features 440 are etched faster than the dense (narrower, high aspect ratio) features 450.
  • deposition on the tungsten containing layer from the deposition component is selective to the open features due, in part, to the deposition component being diffusion limited.
  • Deposition 443 inside, and especially on the bottom of the open (wider, low aspect ratio) features 440 is more than deposition 453 inside the dense (narrower, high aspect ratio) features 450 because deposition chemicals go inside the open features 440 more readily than the dense features 450.
  • the deposition is also aspect ratio dependent.
  • the etch and deposition processes occur at the same time in both the open 440 and the dense 450 features.
  • the greater deposition on the bottom of the open features 440 compensates for the faster etching of the open features 440, resulting in substantially the same depth 460 of conductive layer 420 etched away for both open 440 and narrow 450 features during the etch step. That is, the lower etch rate in the open features 440 resulting from the selective deposition in those features 443 results in zero microloading.
  • Reverse or positive microloading can also be achieved by modifying the deposition component in the etch step 130 to produce even more deposition in the open features 440 relative to the narrow features 450.
  • the deposition is non-conformal, such that there is little deposition on the sidewalls of the features in comparison to the deposition on the bottom of the features. Having little or no deposition over the sidewalls of the features may prevent narrowing the opening of the features.
  • deposition 446, 456 there may also be some amount of deposition 446, 456 on top of the mask layer 430. Etching of the mask layer 430 also occurs in the etch step 130. Deposition 446 and 456 on top of the mask layer 430 reduces the etch rate (i.e. erosion and/or corrosion) of the mask layer 430. [0037] When the etch component and the deposition component are reasonably balanced, i.e. when the etch rate of layer 420 is substantially the same in both the open 440 and dense 450 features, the thickness of deposition layer 443 in the open features 440 and deposition layers 446 and 456 on mask layer 430 may be very small, e.g. monolayer or sub-monolayer. The relative thicknesses of the deposition layers in Figure 4B are therefore exaggerated so as to illustrate the selective deposition process.
  • the etch component and the deposition component are provided in a single step (step 130) as the tungsten containing layer is etched, until the tungsten containing layer is completely etched (i.e. endpoint is achieved for the etch step).
  • An example of an etch recipe in which the deposition component and etch components are reasonably balanced so as to eliminate etch rate microloading is as follows: a process pressure of 4 milliTorr, plasma power of 900 watts, wafer bias power of 90 watts, Cl 2 gas flow of 30 standard cubic centimeters per minute ("seem"), NF 3 gas flow of 25 seem, O 2 gas flow of 30 seem, N 2 gas flow of 70 seem, SiCU gas flow of 13 seem, wafer substrate temperature setpoint of 60 degrees Celsius.
  • FIG. 4C shows a schematic cross-sectional illustration of the stack 400 after the tungsten containing layer 420 has been completely etched.
  • the features 440 and 450 have reached the bottom of the tungsten containing layer 420 in both the wide features 441 and the narrow features 451. That is, there is no tungsten containing layer remaining in the narrow features 450 when the tungsten containing layer has been completely removed from the bottom of the wide features 440.
  • the non-conformal deposition has prevented narrowing of the openings in the wide features 441 and the narrow features 451, and deposition deposited on top of the features during the etch has reduced the erosion of the mask 430.
  • the aspect ratios of the open (wider) features 440 are relatively lower or smaller than the aspect ratios of the dense (narrower) features 450.
  • the aspect ratios of the narrow features in the tungsten containing layer 420 may be greater than 1:1, such as when the widths of the dense (narrower) features are approximately 80 nanometers (nm) and the heights of the features are 110 nm. In another example, the aspect ratios of the narrow features in the tungsten containing layer 420 may be greater than 7:1.
  • the aspect ratios of the narrow features in the tungsten containing layer 420 may be greater than 15:1.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé permettant de graver des caractéristiques ayant différents rapports d'aspect dans une couche contenant du tungstène. Un gaz de gravure est transmis, lequel contient un composant de gravure du tungstène et un composant de dépôt. Un plasma est formé à partir du gaz de gravure transmis. Une couche contenant du tungstène munie d'un motif ayant des caractéristiques larges et étroites est gravée à l'aide du plasma transmis.
PCT/US2008/083412 2007-11-21 2008-11-13 Procédé de commande d'un micro chargement de gravure pour une couche contenant du tungstène Ceased WO2009067381A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/744,012 US8518282B2 (en) 2007-11-21 2008-11-13 Method of controlling etch microloading for a tungsten-containing layer
CN200880117545.3A CN101952944B (zh) 2007-11-21 2008-11-13 控制对含钨层的蚀刻微负载的方法及其设备

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98959707P 2007-11-21 2007-11-21
US60/989,597 2007-11-21

Publications (1)

Publication Number Publication Date
WO2009067381A1 true WO2009067381A1 (fr) 2009-05-28

Family

ID=40667822

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/083412 Ceased WO2009067381A1 (fr) 2007-11-21 2008-11-13 Procédé de commande d'un micro chargement de gravure pour une couche contenant du tungstène

Country Status (5)

Country Link
US (1) US8518282B2 (fr)
KR (1) KR101564473B1 (fr)
CN (2) CN101952944B (fr)
TW (1) TWI451496B (fr)
WO (1) WO2009067381A1 (fr)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129270B1 (en) 2008-12-10 2012-03-06 Novellus Systems, Inc. Method for depositing tungsten film having low resistivity, low roughness and high reflectivity
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US8377632B2 (en) * 2011-05-29 2013-02-19 Nanya Technology Corp. Method of reducing microloading effect
WO2013148444A1 (fr) * 2012-03-27 2013-10-03 Novellus Systems, Inc. Remplissage d'entités par du tungstène avec inhibition de la nucléation
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR102131581B1 (ko) 2012-03-27 2020-07-08 노벨러스 시스템즈, 인코포레이티드 텅스텐 피처 충진
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
JP2014086500A (ja) * 2012-10-22 2014-05-12 Tokyo Electron Ltd 銅層をエッチングする方法、及びマスク
US9230825B2 (en) * 2012-10-29 2016-01-05 Lam Research Corporation Method of tungsten etching
US9418869B2 (en) 2014-07-29 2016-08-16 Lam Research Corporation Method to etch a tungsten containing layer
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9633867B2 (en) * 2015-01-05 2017-04-25 Lam Research Corporation Method and apparatus for anisotropic tungsten etching
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
CN105355587B (zh) * 2015-10-14 2018-09-04 上海华力微电子有限公司 一种避免浅沟槽隔离结构出现深度负载效应的方法
US9673058B1 (en) * 2016-03-14 2017-06-06 Lam Research Corporation Method for etching features in dielectric layers
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
JP6725176B2 (ja) * 2016-10-31 2020-07-15 株式会社日立ハイテク プラズマエッチング方法
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
CN108695235B (zh) * 2017-04-05 2019-08-13 联华电子股份有限公司 改善钨金属层蚀刻微负载的方法
JP6913569B2 (ja) * 2017-08-25 2021-08-04 東京エレクトロン株式会社 被処理体を処理する方法
US10847374B2 (en) 2017-10-31 2020-11-24 Lam Research Corporation Method for etching features in a stack
US10361092B1 (en) 2018-02-23 2019-07-23 Lam Research Corporation Etching features using metal passivation
US10515821B1 (en) 2018-06-26 2019-12-24 Lam Research Corporation Method of achieving high selectivity for high aspect ratio dielectric etch
CN109110726B (zh) * 2018-07-03 2021-06-29 北京大学 一种提高高深宽比钨合金刻蚀均匀性的方法
US10741407B2 (en) 2018-10-19 2020-08-11 Lam Research Corporation Reduction of sidewall notching for high aspect ratio 3D NAND etch
KR20250109239A (ko) 2018-12-05 2025-07-16 램 리써치 코포레이션 보이드 프리 (void free) 저응력 (low stress) 충진
US12261081B2 (en) 2019-02-13 2025-03-25 Lam Research Corporation Tungsten feature fill with inhibition control
US11289402B2 (en) 2019-02-22 2022-03-29 Samsung Electronics Co., Ltd. Semiconductor device including TSV and method of manufacturing the same
WO2020008703A1 (fr) 2019-04-19 2020-01-09 株式会社日立ハイテクノロジーズ Procédé de traitement par plasma
KR102729079B1 (ko) 2019-08-07 2024-11-14 삼성전자주식회사 반도체 소자
JP7720282B2 (ja) * 2022-06-22 2025-08-07 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
WO2024043082A1 (fr) * 2022-08-22 2024-02-29 東京エレクトロン株式会社 Procédé de gravure et système de traitement au plasma

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283378A (ja) * 1992-03-30 1993-10-29 Nec Yamaguchi Ltd 半導体装置の製造方法
JP2001053145A (ja) * 1999-07-20 2001-02-23 United Microelectronics Corp 集積回路製造工程における同深の狭いコンタクトホールと広いトレンチとを同時に形成する方法
US20070199657A1 (en) * 2006-02-28 2007-08-30 Naoyuki Kofuji Apparatus and method for plasma etching

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4778563A (en) 1987-03-26 1988-10-18 Applied Materials, Inc. Materials and methods for etching tungsten polycides using silicide as a mask
JP2918892B2 (ja) 1988-10-14 1999-07-12 株式会社日立製作所 プラズマエッチング処理方法
US5201993A (en) * 1989-07-20 1993-04-13 Micron Technology, Inc. Anisotropic etch method
US5338398A (en) 1991-03-28 1994-08-16 Applied Materials, Inc. Tungsten silicide etch process selective to photoresist and oxide
US5705433A (en) 1995-08-24 1998-01-06 Applied Materials, Inc. Etching silicon-containing materials by use of silicon-containing compounds
US6527968B1 (en) * 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
US20030092280A1 (en) * 2001-11-09 2003-05-15 Applied Materials, Inc. Method for etching tungsten using NF3 and Cl2
US20030235995A1 (en) * 2002-06-21 2003-12-25 Oluseyi Hakeem M. Method of increasing selectivity to mask when etching tungsten or tungsten nitride
US6911399B2 (en) * 2003-09-19 2005-06-28 Applied Materials, Inc. Method of controlling critical dimension microloading of photoresist trimming process by selective sidewall polymer deposition
US7235492B2 (en) 2005-01-31 2007-06-26 Applied Materials, Inc. Low temperature etchant for treatment of silicon-containing surfaces
US7413992B2 (en) 2005-06-01 2008-08-19 Lam Research Corporation Tungsten silicide etch process with reduced etch rate micro-loading
US7629255B2 (en) * 2007-06-04 2009-12-08 Lam Research Corporation Method for reducing microloading in etching high aspect ratio structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283378A (ja) * 1992-03-30 1993-10-29 Nec Yamaguchi Ltd 半導体装置の製造方法
JP2001053145A (ja) * 1999-07-20 2001-02-23 United Microelectronics Corp 集積回路製造工程における同深の狭いコンタクトホールと広いトレンチとを同時に形成する方法
US20070199657A1 (en) * 2006-02-28 2007-08-30 Naoyuki Kofuji Apparatus and method for plasma etching

Also Published As

Publication number Publication date
TW200933744A (en) 2009-08-01
CN102969240A (zh) 2013-03-13
US8518282B2 (en) 2013-08-27
CN101952944B (zh) 2013-01-02
CN101952944A (zh) 2011-01-19
KR20100088157A (ko) 2010-08-06
TWI451496B (zh) 2014-09-01
CN102969240B (zh) 2016-11-09
KR101564473B1 (ko) 2015-10-29
US20110151670A1 (en) 2011-06-23

Similar Documents

Publication Publication Date Title
US8518282B2 (en) Method of controlling etch microloading for a tungsten-containing layer
US8609546B2 (en) Pulsed bias plasma process to control microloading
CN113785381B (zh) 用于极紫外光刻抗蚀剂改善的原子层蚀刻及选择性沉积处理
US9018098B2 (en) Silicon etch with passivation using chemical vapor deposition
CN102792428B (zh) 用于硅蚀刻的无机快速交变处理
US7629255B2 (en) Method for reducing microloading in etching high aspect ratio structures
CN102646585B (zh) 对伪硬掩膜的扭曲控制
JP2021512504A (ja) マルチプルパターンニング処理での原子層堆積を使用するスペーサプロファイル制御
US20230118701A1 (en) Selective etch using deposition of a metalloid or metal containing hardmask
US11450532B2 (en) Deposition of self assembled monolayer for enabling selective deposition and etch
CN105321816A (zh) 蚀刻含钨层的方法
CN101371336B (zh) 鳍结构成形
TW202407129A (zh) 共沉積及蝕刻製程

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880117545.3

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08852848

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20107013605

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 08852848

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12744012

Country of ref document: US