WO2009049808A1 - Depfet transistor having a large dynamic range - Google Patents

Abstract

The invention relates to a DEPFET transistor (1) for detecting a radio-generated signal charge (2) and for generating an electronic output signal in a manner dependent on the detected signal charge (2) according to a predetermined characteristic curve. The invention provides for the characteristic curve to have a degressive characteristic curve profile in order to combine a high measurement sensitivity in the case of small signal charges (2) with a large measurement range through to large signal charges (2).

Description

 DESCRIPTION

DEPFET transistor with high dynamic range

The invention relates to a DEPFET transistor according to the main claim.

In semiconductor detectors for high-sensitivity radiation detection, DEPFET transistors (DEPFET: Depleted Field Effect Transistor) are used as readout element, which were invented in 1984 by J. Kemmer and G. Lutz and, for example, in Gerhard Lutz: "Semiconductor Radiation Detectors". , 2nd edition, Springer-Verlag 2001, 234-253.

In this case, the radiation to be detected generates signal charge carriers in the semiconductor detector which are detected by the DEPFET transistor serving as a readout element. Of the

The DEPFET transistor then generates an output signal (e.g., source voltage) in response to the radiation-generated signal charge carriers in accordance with a particular characteristic which provides a measure of the radiation to be detected.

In such semiconductor detectors, a non-linear characteristic is desirable with a large characteristic slope for small signal charges and a small characteristic slope for large signal charges.

The large characteristic slope for small signal charges is advantageous because then small signal charges and correspondingly weak radiation can be measured with a high sensitivity. The small characteristic slope for large signal charges, however, is advantageous because otherwise the measuring range has been exceeded by large signal charges.

Such a nonlinear characteristic curve thus advantageously combines a high measuring sensitivity with small signal charges with a large measuring range.

This non-linear characteristic is achieved in the conventional semiconductor detectors by a suitable electrical wiring of the semiconductor detector, such as by a non-linearity in the feedback branch or an amplifier area switching in response to the detected signal. Such a semiconductor detector is known from DE 10 2005 025 641 Al.

A disadvantage of the known semiconductor detectors with a DEPFET transistor as a readout element is therefore the fact that the desired non-linear Kennlmiencharakteris ^¬ tik must be achieved by a separate electrical wiring, which is associated with an additional circuit complexity.

Furthermore, WO 2007/077287 A1 discloses a semiconductor detector which, however, does not have a DEPFET transistor.

Finally, the general state of the art should be pointed to US 2005/0167771 Al.

The invention is therefore based on the object to reduce the effort to realize the desired non-linear characteristic curve in a semiconductor detector. This object is achieved by a DEPFET transistor according to the main claim.

The invention comprises the general technical teaching of not achieving the desired non-linear characteristic of the semiconductor detector by a separate electrical connection of the semiconductor detector, but by a suitable design of the DEPFET transistor used as a readout element.

This advantageously makes it possible to dispense with the previously required circuit for generating the desired nonlinear characteristic of the semiconductor detector, but the invention also claims protection for semiconductor detectors, in which a circuit is additionally provided in order to influence the characteristic curve.

The invention therefore provides a DEPFET transistor which serves to detect a radiation-generated signal charge and generates an electrical output signal (eg source voltage) as a function of the detected signal charge in accordance with a predetermined characteristic curve, wherein the characteristic curve has a degressive characteristic curve to a high Sensitivity to be combined with small signal charges with a large measuring range up to large signal charges.

The term degressive characteristic curve used in the context of the invention preferably means that the characteristic slope (ie the differential quotient of output signal and signal charge) decreases from small signal charges to large signal charges. However, the invention is not limited to such embodiments in which the characteristic slope over the entire measuring range with the Sig. nalladung decreases. Rather, the invention also encompasses those embodiments in which the characteristic gradient has local maxima within the measuring range, provided that the characteristic gradient has a trend within the measuring range which decreases with the signal charge.

Furthermore, the term used in the invention of the output signal is not limited to the source voltage of the DEPFET transistor. Rather, other electrical variables are possible as output signal, such as the drain current.

In one variant of the invention, the characteristic curve is essentially kink-free within the measuring range, so that the characteristic gradient changes continuously within the measuring range. For example, the characteristic curve can show a wurzelförmige or logarithmic dependence on the signal charge.

In contrast, in another variant of the invention, the characteristic curve has a plurality of, preferably linear characteristic curve sections with different characteristic gradient slopes, wherein the characteristic gradient of the individual characteristic curve sections decreases with the signal charge. This means that the individual characteristic sections each have a lower characteristic slope than the preceding characteristic section in a region with a smaller signal charge.

The DEPFET transistor may be formed in a conventional manner, apart from the present invention provided degressive characteristic curve, so that reference is made to the already mentioned publication Gerhard Lutz: "Semiconductor Radiation Detectors", 2nd edition, Springer-Verlag 2001, 234-253. The content of this publication is therefore to the full extent attributable to the present description with respect to the structure and operation of a DEPFET transistor.

The DEPFET transistor according to the invention therefore preferably has a semiconductor substrate with a front side and a rear side, wherein a source and a drain are arranged on the front side of the semiconductor substrate, between which extends a controllable line channel.

First, the conductivity of the conduction channel may be conventionally controlled by an external gate disposed at the front of the semiconductor substrate over the conduction channel.

On the other hand, in the case of the DEPFET transistor, the conduction of the conduction channel can be controlled by an internal gate, which is arranged in the semiconductor substrate at least partially under the conduction channel and doped with a specific doping strength, whereby the radiation-generated signal charge accumulates in the internal gate and thereby controlling the conductivity of the duct.

It should be noted that in practice the internal gate is spatially not sharply demarcated from the surrounding semiconductor substrate. Rather, the doping strength within the semiconductor substrate usually changes continuously, the internal gate being formed by a spatial area within which the doping intensity exceeds a certain limit.

Furthermore, the DEPFET transistor according to the invention preferably also has a back contact, which at the back of the Semiconductor substrate is arranged to deplete the semiconductor substrate.

As a special feature over the conventional DEPFET transistors, the invention preferably provides that the internal gate extends in the lateral direction beyond the line channel to below the source. The signal charge then accumulates initially in the region of the internal gate which lies below the conduction channel, where the accumulated signal charge strongly influences the conductivity of the conduction channel, resulting in a large slope of the DEPFET transistor. With increasing signal charge in the internal gate, a part of the signal charge accumulated in the internal gate is no longer in the area under the line channel, but in the area below the source, where the signal charge influences the conductivity of the line channel to a much lesser extent , which leads to a correspondingly smaller slope.

Here, the doping strength can be varied within the internal gate in the lateral direction in order to influence the characteristic curve in the desired manner. In this case, the doping strength in the internal gate is preferably greater under the conduction channel than under the source, in order to achieve the desired degressive characteristic curve.

In addition, within the scope of the invention, there is also the possibility that the vertical extent of the internal gate is varied in the lateral direction in order to influence the characteristic curve. For example, the internal gate may have a greater vertical extent under the conduction channel than under the source such that the vertical extent of the internal gate decreases from the region below the conduction channel in a lateral direction toward the source. In this case, the doping intensity or the vertical extent of the internal gate can be changed continuously in the lateral direction in order to achieve a correspondingly continuous characteristic curve.

Alternatively, there is the possibility that the doping intensity or the vertical extent of the internal gate is changed stepwise in the lateral direction in order to achieve a characteristic curve progression with a plurality of linear characteristic sections with different characteristic slope.

In the context of the invention, therefore, the doping profile of the internal gate can be set as a function of the depth in the semiconductor substrate and / or the lateral position with respect to the duct so that the desired degressive characteristic is achieved.

Furthermore, it is within the scope of the invention, the possibility that extends the internal gate in the lateral direction beyond the duct beyond the drain, but this is not absolutely necessary.

It is also possible within the scope of the invention for the internal gate in the semiconductor substrate to extend increasingly far downwards into the semiconductor substrate from the region under the source to the region under the conduction channel. In this case, the internal gate extends deeper into the semiconductor substrate in the area below the line channel than in the area below the source. Preferably, the internal gate extends only on its upper side in the lateral direction beyond the line channel to below the source, while the internal gate on its underside in the lateral direction of the area under the Conduit is limited and does not extend to below the source. In this case, the internal gate preferably forms a potential well which fills with radiation-generated signal charge during radiation detection, the accumulated signal charge also extending as far as below the source as the degree of filling of the potential well increases.

In contrast, in another variant of the invention, the internal gate extends from the region under the source, starting in the lateral direction towards the region below the conduction channel, increasingly far upwards into the semiconductor substrate. In this case, the internal gate preferably extends on its underside in the lateral direction beyond the line channel to below the source, while the internal gate does not extend on its upper side in the lateral direction to below the source, but limited to the area below the line channel is.

It is also possible within the scope of the invention for the internal gate in the semiconductor substrate m to run at a certain depth, the depth decreasing from the area under the line channel to the area below the source. In this case, the internal gate runs under the conduction channel at a greater depth than under the source, whereby the desired non-linear characteristic curve is achieved.

The DEPFET transistor according to the invention is therefore distinguished by the fact that the measuring sensitivity (ie the differential quotient of signal charge or incident radiation on the one hand and the resulting electrical output signal on the other hand) decreases with the accumulated signal charge. This combines a high measurement sensitivity with small signal charges with a large measuring range up to large signal charges. It should also be mentioned that the same possibilities exist with respect to the doping ratios as with the conventional DEPFET transistors mentioned above. The semiconductor substrate and the internal gate are thus doped according to a first doping type, while the source, the drain and the back contact are doped in accordance with a second doping type. The first doping type is preferably an n-type doping, while the second doping type is preferably a p-type doping. However, it is alternatively also possible that the first doping type has a p-type doping, while the second doping type has an n-type doping.

In addition, it should be mentioned that the erfmdungsgemaße

DEPFET transistor may optionally be constructed linear or annular, which is well known in the prior art in itself and therefore need not be described in more detail.

Finally, the invention also encompasses a semiconductor detector for radiation detection with the above-described DEPFET transistor according to the invention, wherein the DEPFET transistor can be used in the semiconductor detector as a read-out element and / or as a radiation-detecting detector element.

In this case, the semiconductor detector preferably has numerous detector elements which are arranged in matrix form, wherein the individual detector elements each form a pixel (pixel) and preferably consist of a DEPFET transistor according to the invention with a degressive characteristic. Other advantageous developments of the invention are characterized in the subclaims or are explained in more detail below together with the description of the preferred embodiments of the invention with reference to FIGS. Show it:

FIG. 1 shows a simplified plan view of a DEPFET transistor according to the invention,

FIG. 2 shows a simplified cross-sectional view of the DEPFET transistor according to FIG. 1 along the section line

A-A,

FIG. 3 shows a modification of the cross-sectional view from FIG. 1, wherein the internal gate extends further upwards below the line channel than under the source,

FIG. 4 shows a modification of the cross-sectional view from FIG. 3, wherein the internal gate does not extend in a lateral direction as far as below the drain,

5 shows a modification of the cross-sectional view from FIG. 2, wherein the internal gate does not extend in the lateral direction as far as below the drain,

FIG. 6 is a cross-sectional view of an alternative embodiment wherein the depth of the internal gate varies laterally and is greatest below the conduit.

Figure 7 is a simplified and idealized representation of a characteristic curve in the above-described embodiments of a DEPFET transistor according to the invention and FIG. 8 shows alternative characteristic curves of DEPFET transistors according to the invention.

Figures 1 and 2 show in simplified and idealized form a DEPFET transistor 1 in a plan view and in a cross-sectional view.

The DEPFET transistor 1 serves as a readout element in a semiconductor detector, wherein the remaining structure of the semiconductor detector is not shown for simplicity.

The DEPFET transistor 1 has a weakly n-doped semi-conductor substrate ^¬ HS VS having a front and a rear side RS.

At the rear side RS of the semiconductor substrate HS, there is a planar back contact RK, which consists of a heavily p-doped region and forms a reversely poled diode with the n-doped semiconductor substrate HS and serves to deplete the semiconductor substrate HS. In operation of the DEPFET transistor 1, therefore, a positive electric potential is applied to the back contact RK to deplete the semiconductor substrate HS.

At the front side VS, the semiconductor substrate HS is covered and insulated by an oxide layer Ox, which is known per se from the prior art. However, the oxide layer Ox has interruptions to contact the source S and the drain D electrically, which is not apparent from this cross-sectional drawing.

Furthermore, a heavily p-doped source S and a likewise heavily p-doped drain D are located on the front side VS of the semiconductor substrate HS, wherein between the source ce S and the drain D extends a conduction channel LK whose conductivity can be controlled.

On the one hand, the conductivity of the conduction channel LK can be controlled by an external gate G, which is arranged on the front side VS over the oxide layer Ox.

On the other hand, the conductivity of the conduction channel LK can be controlled by an internal gate IG, which is arranged in the semiconductor substrate HS and consists of a buried, n-doped region in which radiation-generated signal charge carriers 2 accumulate.

A special feature of the DEPFET transistor 1 according to the invention is that the internal gate IG is not limited in the lateral direction to the area below the line channel, but extends in the lateral direction to below the source S and also to below the drain D. This is important because the signal charge carriers 2, which are located in the internal gate IG below the source S, contribute to a much lesser extent to the control of the conductivity of the line channel LK than the signal charge carriers 2, which are located in the internal gate IG below are located in the duct LK.

The internal gate IG extends deeper below the line channel LK than below the source S, so that the internal gate IG has a greater vertical extent under the line channel LK than under the source S. As a result, the radiation-generated Signal charge carrier 2 in the internal gate IG first accumulate in the area under the line channel LK and contribute there to a relatively large extent to the control of the conductivity of the duct LK. Only with increasing signal charge quantity are then in the internal gate IG in the area below the source S signal charge carrier 2, but there contribute to a much lesser extent to control the conductivity of the line channel LK.

The internal gate IG in this case has three areas in the lateral direction, which are each separated by a step, which leads to a characteristic curve 3 shown in FIG. Thus, the characteristic curve 3 shows the dependence of the source voltage U _SOURCE of the radiation-generated Signalalla- fertil Q. From the drawing it can be seen that the characteristic curve 3 has several characteristic sections 4, 5, 6 with different characteristic slopes, the characteristic _slope with the signal charge Q decreases, so that the characteristic curve 3 has a total degressive characteristic curve. This is advantageous because, in the case of small signal charges Q <Q1 in the characteristic section 4, a large characteristic slope with a correspondingly high measuring sensitivity is available, while the characteristic slope decreasing towards larger signal charges enables a large measuring range.

From the plan view in FIG. 1, it can further be seen that the DEPFET transistor 1 has a linear structure and additionally has a clear gate CLG which is arranged laterally next to the line channel LK or the external gate G.

In addition, the DEPFET transistor 1 has two clear contacts CL, which subtract the accumulated in the internal gate IG signal carrier 2 in an erase process via the clear gate CLG.

However, in the case of the DEPFET transistor 1 according to the invention, the erase process can also be carried out by other techniques, which are known from the prior art per se and therefore need not be described in detail.

Figure 3 shows a cross-sectional view of an alternative embodiment of the DEPFET transistor 1, which is broadly similar to the embodiment described above, so reference is made to the above description to avoid repetition, the same reference numerals being used for corresponding details.

A special feature of this exemplary embodiment is that the internal gate IG extends from the area under the source S in the lateral direction towards the area below the line channel LK increasingly far up to the front side VS. The vertical extension of the internal gate IG is thus the largest in the area under the duct LK and decreases in the lateral direction to the source S out.

FIG. 4 shows a modification of FIG. 3, so that reference is made to the above description to avoid repetition, the same reference numerals being used for corresponding details.

A special feature of this embodiment is that the internal gate IG does not extend in the lateral direction to below the drain D.

FIG. 5 shows a modification of the cross-sectional view from FIG. 2, so that reference is made to the above description to avoid repetition, the same reference numerals being used for corresponding details. A special feature of this embodiment is also that the internal gate IG does not extend in the lateral direction to below the drain D.

FIG. 6 shows a cross-sectional view of a further exemplary embodiment of a DEPFET transistor 1 according to the invention, which largely corresponds to the exemplary embodiments described above, so that reference is made to the above description to avoid repetition, the same reference numerals being used for corresponding details.

A peculiarity of this embodiment is that the internal gate IG runs at a certain depth T in the semiconductor substrate HS, wherein the depth T varies in the lateral direction and is maximum in the area below the line channel LK.

The depth T then decreases in a lateral direction toward the source S, as a result of which the characteristic curve of the DEPFET transistor 1 is likewise influenced in the desired manner.

Finally, FIG. 8 shows two alternative digressive characteristic curves 7, 8 of a DEPFET transistor according to the invention. The characteristic curve 7 in this case has a wurzelförmige dependence of the source voltage U _SOURCE of the signal _charge Q, while the characteristic curve 8 shows a logarithmic dependence of the source voltage U _SOURCE of the signal _charge Q.

The invention is not limited to the preferred embodiments described above. Rather, a variety of variants and modifications is possible, which also make use of the inventive idea and therefore fall within the scope. Reference sign list:

1 DEPFET transistor

2 signal charge carriers

3 characteristic

4-6 characteristic sections

7 Worm-shaped characteristic

8 Logarithmic characteristic CL extinguishing contacts

CLG Clear-Gate

D drain

G External

HS semiconductor substrate

LK line channel

Ox oxide layer

RK back contact

RS backside

S Source

VS front side

Claims

1. DEPFET transistor (1) for detecting a radiation-generated signal charge (2, Q) and for generating an electrical output signal (U _SOURCE ) as a function of the _{detected signal charge} (2, Q) corresponding to a predetermined characteristic curve (3, 7, 8), characterized in that the characteristic curve (3, 7, 8) has a degressive characteristic curve in order to achieve a high measuring sensitivity for small signal charges (2, Q) with a large measuring range up to large signal charges (2, Q ) to combine. 2. DEPFET transistor (1) according to claim 1, characterized in that the characteristic curve (7, 8) is substantially kink-free within the measuring range. 3. DEPFET transistor (1) according to one of the preceding claims, characterized in that a) that the characteristic (7) has a wurzelförmige dependence on the signal charge (2, Q), or b) that the characteristic (8) a logarithmic dependence on the signal charge (2, Q). 4. DEPFET transistor (1) according to claim 1, characterized in a) that the characteristic curve (3) has several characteristic sections (4, 5, 6) with different characteristic slopes, and b) that the characteristic slope of the characteristic sections (4, 5, 6) decreases with the signal charge (2, Q). 5. DEPFET transistor (1) according to claim 4, characterized in that the individual characteristic sections (4, 5, 6) each have a substantially linear characteristic curve. 6. DEPFET transistor (1) according to one of the preceding claims, characterized by a) a semiconductor substrate (HS) with a front side (VS) and a back side (RS), b) a source (S), which at the front (VS c) a drain (D) which is arranged at the front side (VS) of the semiconductor substrate (HS) at a distance from the source (S), d) a conduction channel (LK), the extends at the front side (VS) of the semiconductor substrate (HS) between the source (S) and the drain (D) and has a controllable conductivity, e) an internal gate (IG), which in the semiconductor substrate (HS) at least partially under the conduction channel (LK) is arranged and doped with a certain doping strength, wherein the radiation-generated signal charge (2, Q) accumulates in the internal gate (IG) and thereby controls the conductivity of the duct (LK), f) one at the front ( VS) of the semiconductor substrate (HS) over the line Channel (LK) arranged external gate (G) for controlling the conductivity of the line channel (LK), and / or g) a back contact (RK), which at the back (RS) of the semiconductor substrate (HS) is arranged to the semiconductor substrate ( HS) to impoverish. 7. DEPFET transistor (1) according to claim 6, characterized in that the internal gate (IG) extends in the lateral direction beyond the line channel (LK) to below the source (S). 8. DEPFET transistor (1) according to claim 6 or 7, characterized in that a) that the internal gate (IG) under the line channel (LK) has a greater doping strength than under the source (S), and / or b) that the internal gate (IG) has a greater vertical extent under the line channel (LK) than under the source (S). 9. DEPFET transistor (1) according to claim 8, characterized in that a) that the doping strength in the internal gate (IG) in the lateral direction from the area under the duct (LK) to the area under the source (S) down - takes, and / or b) that the vertical extent of the internal gate (IG) decreases in the lateral direction from the area under the duct (LK) to the area below the source (S). 10. DEPFET transistor (1) according to claim 9, characterized in that a) that the doping strength and / or the vertical extent of the internal gate (IG) changes continuously in the lateral direction, or b) that the doping strength and / or or the vertical extent of the internal gate (IG) in the lateral direction changed stepwise. 11. DEPFET transistor (1) according to one of claims 6 to 10, characterized in that: a) that the internal gate (IG) extends laterally beyond the duct (LK) to below the drain (D) extends, or b) that the internal gate (IG) does not extend in the lateral direction to below the drain (D). 12. DEPFET transistor (1) according to any one of claims 6 to 11, characterized in that a) that the internal gate (IG) from the region under the source (S), starting towards the area under the duct (LK) increasing extends far down into the semiconductor substrate (HS), and / or b) that extends the internal gate (IG) on its upper side in a lateral direction beyond the duct (LK) to below the source (S), and / or c ) that the internal gate (IG) on its underside in the lateral direction does not extend below the source (S). 13. DEPFET transistor (1) according to one of claims 6 to 11, characterized in that a) that the internal gate (IG) from the region under the source (S), starting in the lateral direction towards the area under the duct ( LK) extends increasingly far upwards into the semiconductor substrate (HS), and / or b) that the internal gate (IG) extends on its underside in a lateral direction beyond the line channel (LK) to below the source (S), and /or c) that the internal gate (IG) on its upper side in the lateral direction does not extend below the source (S). 14. DEPFET transistor (1) according to claim 6 or 11, characterized in that the internal gate (IG) in the semiconductor substrate (HS) at a certain depth (T), wherein the depth (T) of the area under the Conduit (LK) to the area under the source (S) decreases. 15. DEPFET transistor (1) according to one of claims 6 to 14, characterized in that a) that the semiconductor substrate (HS) and the internal gate (IG) is doped according to a first doping type (n), and / or b) that the source (S), the drain (D) and the back contact (RK) are doped in accordance with a second doping type (p). 16. DEPFET transistor (1) according to claim 15, characterized in that a) that the first doping type has an n-doping, while the second doping type has a p-type doping, or b) that the first doping type has a p-type doping, while the second doping type has an n-type doping. 17. DEPFET transistor (1) according to one of claims 6 to 16, characterized in that the internal gate (IG) has a specific doping profile, which is selected so that the characteristic curve is degressive. 18. A semiconductor detector for radiation detection, characterized by at least one DEPFET transistor (1) according to one of the preceding claims. 19. A semiconductor detector according to claim 18, characterized in that the DEPFET transistor (1) a) forms a read-out element and / or b) a radiation-detecting detector element. 20. A semiconductor detector according to claim 19, characterized in that a plurality of detector elements are arranged in a matrix. * * * * *