[go: up one dir, main page]

WO2008139897A1 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

Info

Publication number
WO2008139897A1
WO2008139897A1 PCT/JP2008/058098 JP2008058098W WO2008139897A1 WO 2008139897 A1 WO2008139897 A1 WO 2008139897A1 JP 2008058098 W JP2008058098 W JP 2008058098W WO 2008139897 A1 WO2008139897 A1 WO 2008139897A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
silicon substrate
arranging
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/058098
Other languages
French (fr)
Japanese (ja)
Inventor
Masaru Takaishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2009514084A priority Critical patent/JP5443978B2/en
Publication of WO2008139897A1 publication Critical patent/WO2008139897A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0293—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Provided is a semiconductor device manufacturing method wherein complication of manufacturing process is suppressed. The method for manufacturing a semiconductor device (1) is provided with a step of forming trenches (2a, 2b) on a silicon substrate (2) so that the width (W1) of the trench (2a) is larger than the width (W2) of the trench (2b); a step of arranging electrodes (3, 4); a step of arranging an oxide film (14 (14a)); a step of removing the oxide film (14 (14a)) so that at least a part of the upper surfaces of the silicon substrate (2) and the electrode (3) are exposed and that the upper surface of the electrode (4) is not exposed; and a step of arranging a wiring layer (6) on the upper surface side of the silicon substrate (2).
PCT/JP2008/058098 2007-04-27 2008-04-25 Semiconductor device manufacturing method and semiconductor device Ceased WO2008139897A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009514084A JP5443978B2 (en) 2007-04-27 2008-04-25 Semiconductor device manufacturing method and semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-118928 2007-04-27
JP2007118928 2007-04-27

Publications (1)

Publication Number Publication Date
WO2008139897A1 true WO2008139897A1 (en) 2008-11-20

Family

ID=40002113

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/058098 Ceased WO2008139897A1 (en) 2007-04-27 2008-04-25 Semiconductor device manufacturing method and semiconductor device

Country Status (3)

Country Link
JP (1) JP5443978B2 (en)
TW (1) TW200910429A (en)
WO (1) WO2008139897A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104900703A (en) * 2015-05-12 2015-09-09 上海格瑞宝电子有限公司 Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof
EP4246595A4 (en) * 2020-11-12 2024-05-29 Chongqing Alpha and Omega Semiconductor Limited Trench power device and manufacturing method therefor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373988A (en) * 2001-06-14 2002-12-26 Rohm Co Ltd Semiconductor device and manufacturing method thereof
JP2004179277A (en) * 2002-11-26 2004-06-24 New Japan Radio Co Ltd Method for manufacturing semiconductor device
JP2004207476A (en) * 2002-12-25 2004-07-22 Mitsubishi Electric Corp Power semiconductor device and method for manufacturing power semiconductor device
JP2004311547A (en) * 2003-04-03 2004-11-04 Seiko Instruments Inc Method of manufacturing vertical MOS transistor
JP2005191487A (en) * 2003-12-26 2005-07-14 Seiko Instruments Inc Semiconductor device and manufacturing method for the same
JP2006100404A (en) * 2004-09-28 2006-04-13 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP2006100317A (en) * 2004-09-28 2006-04-13 Nec Electronics Corp Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373988A (en) * 2001-06-14 2002-12-26 Rohm Co Ltd Semiconductor device and manufacturing method thereof
JP2004179277A (en) * 2002-11-26 2004-06-24 New Japan Radio Co Ltd Method for manufacturing semiconductor device
JP2004207476A (en) * 2002-12-25 2004-07-22 Mitsubishi Electric Corp Power semiconductor device and method for manufacturing power semiconductor device
JP2004311547A (en) * 2003-04-03 2004-11-04 Seiko Instruments Inc Method of manufacturing vertical MOS transistor
JP2005191487A (en) * 2003-12-26 2005-07-14 Seiko Instruments Inc Semiconductor device and manufacturing method for the same
JP2006100404A (en) * 2004-09-28 2006-04-13 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP2006100317A (en) * 2004-09-28 2006-04-13 Nec Electronics Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104900703A (en) * 2015-05-12 2015-09-09 上海格瑞宝电子有限公司 Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof
EP4246595A4 (en) * 2020-11-12 2024-05-29 Chongqing Alpha and Omega Semiconductor Limited Trench power device and manufacturing method therefor

Also Published As

Publication number Publication date
JPWO2008139897A1 (en) 2010-07-29
JP5443978B2 (en) 2014-03-19
TW200910429A (en) 2009-03-01

Similar Documents

Publication Publication Date Title
WO2008042732A3 (en) Recessed sti for wide transistors
WO2009075244A1 (en) Method for manufacturing solar cell
TW200504933A (en) Method for manufacturing semiconductor device
WO2005101100A3 (en) Method and apparatus for in-situ film stack processing
WO2009011185A1 (en) Solar cell manufacturing method
WO2006095566A8 (en) Nitride semiconductor light-emitting device and method for fabrication thereof
WO2008087763A1 (en) Semiconductor device and process for manufacturing the same
WO2007130729A3 (en) Method of forming a semiconductor device and structure thereof
TW200607094A (en) Semiconductor device and method of manufacturing thereof
JP2007513517A5 (en)
WO2005057663A3 (en) Method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices
EP2031653A3 (en) Semiconductor device having multiple element formation regions and manufacturing method thereof
TW200725745A (en) Method for forming semiconductor device having fin structure
WO2006074175A3 (en) Method and structure for forming an integrated spatial light modulator
TW200701371A (en) Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same
US8754532B2 (en) Semiconductor device and manufacturing method thereof
TW200729409A (en) Method for fabricating semiconductor device
TW200744162A (en) Method for fabricating semiconductor device having capacitor
WO2008139898A1 (en) Semiconductor device manufacturing method and semiconductor device
WO2009013849A1 (en) Semiconductor device and its manufacturing method
WO2008139897A1 (en) Semiconductor device manufacturing method and semiconductor device
WO2007133604A3 (en) Method for forming a semiconductor on insulator structure
TW200746391A (en) Embedded capacitor in semiconductor device and methods for fabricating the same
TW200608459A (en) Method for fabricating semiconductor device and semiconductor device
WO2007106814A3 (en) Semiconductor device fabricated using a carbon-containing film as a contact etch stop layer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08740887

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2009514084

Country of ref document: JP

122 Ep: pct application non-entry in european phase

Ref document number: 08740887

Country of ref document: EP

Kind code of ref document: A1