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WO2008136813A3 - Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement - Google Patents

Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement Download PDF

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Publication number
WO2008136813A3
WO2008136813A3 PCT/US2007/024544 US2007024544W WO2008136813A3 WO 2008136813 A3 WO2008136813 A3 WO 2008136813A3 US 2007024544 W US2007024544 W US 2007024544W WO 2008136813 A3 WO2008136813 A3 WO 2008136813A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile
semiconductor memory
operating
floating gate
functionality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/024544
Other languages
English (en)
Other versions
WO2008136813A2 (fr
Inventor
Yuniarto Widjaja
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of WO2008136813A2 publication Critical patent/WO2008136813A2/fr
Publication of WO2008136813A3 publication Critical patent/WO2008136813A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une mémoire à semi-conducteurs présentant deux modes de fonctionnement (mémoire volatile et mémoire non volatile) et ses procédés de fonctionnement. Une cellule mémoire à semi-conducteurs comprend : une première région incorporée à un premier emplacement dans le substrat et possédant un second type de conductivité; une seconde région incorporée à un second emplacement dans le substrat et possédant le second type de conductivité, de sorte qu'au moins une partie du substrat possédant le premier type de conductivité est située entre le premier et le second emplacement, et fonctionne comme un corps flottant pour stocker des données dans la mémoire volatile; une grille flottante ou une couche de piégeage positionnée entre le premier et le second emplacement et au-dessus d'une surface du substrat et isolée de cette dernière par une couche d'isolation; la grille flottante ou la couche de piégeage étant configurées pour recevoir un transfert de données stockées dans la mémoire volatile et stocker les données sous forme de mémoire non volatile dans la grille flottante ou la couche de piégeage lors d'une interruption d'alimentation de la cellule mémoire; et une grille de commande positionnée au-dessus de la grille flottante ou de la couche de piégeage et une seconde couche d'isolation positionnée entre la grille flottante ou la couche de piégeage et la grille de commande.
PCT/US2007/024544 2006-11-29 2007-11-29 Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement Ceased WO2008136813A2 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US86177806P 2006-11-29 2006-11-29
US60/861,778 2006-11-29
US98237407P 2007-10-24 2007-10-24
US98238207P 2007-10-24 2007-10-24
US60/982,374 2007-10-24
US60/982,382 2007-10-24

Publications (2)

Publication Number Publication Date
WO2008136813A2 WO2008136813A2 (fr) 2008-11-13
WO2008136813A3 true WO2008136813A3 (fr) 2008-12-31

Family

ID=39944139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/024544 Ceased WO2008136813A2 (fr) 2006-11-29 2007-11-29 Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement

Country Status (1)

Country Link
WO (1) WO2008136813A2 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519831A (en) * 1991-06-12 1996-05-21 Intel Corporation Non-volatile disk cache
US20050024968A1 (en) * 2003-07-31 2005-02-03 Brocade Communications Systems, Inc. Apparatus for reducing data corruption in a non-volatile memory
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519831A (en) * 1991-06-12 1996-05-21 Intel Corporation Non-volatile disk cache
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
US20050024968A1 (en) * 2003-07-31 2005-02-03 Brocade Communications Systems, Inc. Apparatus for reducing data corruption in a non-volatile memory

Also Published As

Publication number Publication date
WO2008136813A2 (fr) 2008-11-13

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