WO2008135874A1 - Power supply concept with no grey area´s - Google Patents
Power supply concept with no grey area´s Download PDFInfo
- Publication number
- WO2008135874A1 WO2008135874A1 PCT/IB2008/051500 IB2008051500W WO2008135874A1 WO 2008135874 A1 WO2008135874 A1 WO 2008135874A1 IB 2008051500 W IB2008051500 W IB 2008051500W WO 2008135874 A1 WO2008135874 A1 WO 2008135874A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- reset
- voltage
- digital core
- power
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
Definitions
- the present invention relates to a circuit arrangement in which a reset of a digital core is achieved via Power On Reset. Furthermore the invention relates to a method for resetting a digital core via Power On Reset using a circuit arrangement.
- Circuit arrangements of the a. m. type are known and common to the skilled in the art. Circuit arrangements of the type initially mentioned are used to eliminate grey areas in a current supply design of integrated circuits (IC), especially in automotive products used for safety critical applications (e. g. FlexRay applications).
- IC integrated circuits
- a digital core in a mixed signal IC needs a defined state and if this cannot be guaranteed, the digital core must be reset. This is normally depicted with Power On Reset.
- the aim of the invention is to design a circuit arrangement of the a. m. type according to the preamble of claim 1 in such a way that a mechanism is defined for the analog part in a mixed signal IC in the case of an under-running voltage at the current supply connection.
- the circuit arrangement comprises a detection circuit for under voltage detection on the power supply connection/connections and a detection circuit for the detection of a Power On Reset which is required for the digital core.
- This invention describes a new state of a mixed signal IC in case of an under voltage at the supply pins.
- the advantage of the present invention is that an undefined state is overcome.
- the invention provides two types of detection circuits. One to detect with high accuracy an under voltage on the power supply pin(s) and one to detect a necessary Power On Reset for the digital core. The accuracy of the latter circuit can be much lower and therefore it is possible to design a circuit that will have the right functionality even if the power supply voltage is very low.
- an under voltage is detected on supply voltages Vcc and Vbat according to the invention it will be signaled to the digital core that will set the analog blocks and the outputs of the digital core in a defined state. If the voltage on Vdig becomes lower that the Power On Reset level, the complete digital core will be switched in reset state. If an under voltage is detected on supply voltages Vcc according to the invention it will be signaled to the digital core that will set the analog blocks and the outputs of the digital core in a defined state. If the voltage on Vcc becomes lower that the Power On Reset level, the complete digital core will be switched in reset state.
- the digital core comprises a voltage, whereby the digital core can be set into a reset state if the voltage is lower that the Power On Reset value and the voltage can be generated from at least two different supply voltages.
- the digital core comprises analog blocks and outputs and the digital core sets the analog blocks and the outputs into a defined state when an under voltage is determined.
- Fig. 1 shows a circuit arrangement according to the invention with a single supply voltage
- Fig. 2 shows a circuit arrangement according to the invention with a supply voltage and with a further supply voltage.
- a Power On Reset in which the arrangement has a detection circuit 11 for the detection of an under-running voltage at the current supply connect ion(s), and a detection circuit 12 for the detection of a necessary Power On Reset for the digital core
- the circuit arrangement 100 has in addition analog blocks 13, inputs 14 and outputs 15.
- the digital core 10 sets the analog blocks 13 and its outputs into a defined state as soon as an under-running voltage is detected. All the analog blocks 13 are at a voltage Vcc.
- the circuit 11 is provided to detect the under-running voltage, which is coupled to the digital core 10 via an input 17.
- the further circuit 12 is provided, which lies at a supply voltage Vcc and has the necessary Power On Reset for the digital core 10.
- the entire core is set into a reset state by means of the circuit 12 when the under-running voltage is lower than the Power On Reset level measured on the circuit 12.
- the digital core 10 has a voltage here in which the digital core 10 is able to be reset into a reset state when the voltage V is lower than an adjustment reset value which is generated on the circuit 12.
- the voltage range of the circuit arrangement 100 according to the invention which is present in the form of an integrated circuit lies between 4.75 and 5.25 V.
- the detection of the under-running voltage on the circuit 11 can take place in a voltage range between 4.5 and 4.75 V, whereas the Power On Reset on the circuit 12 is between 3 and 4 V.
- circuit arrangement 100 also exists again here in the form of an integrated circuit.
- a resetting of the digital core 10 also takes place with a Power
- the arrangement has a detection circuit 11 for the detection of an under-running voltage at the power supply connection(s) and a detection circuit 12 for the detection of a necessary Power On Reset for the digital core 10.
- the voltage V of the digital core 10 is able to be produced from at least two different supply voltages Vcc and
- Vbat by a generator 16 which has a voltage V core at its output.
- Vcc related specification points guarantied from 4.5 to 5.25 V
- all Vbat related specification points guaranteed from 4.5 to 60V.
- Vcc Operating range of the integrated circuit from 4.75 to 5.25 V; Vbat Operating range of the integrated circuit from 4.75 to 60V; Under voltage detection on Vcc from 4.5 to 4.75V;
- an extra state of the integrated circuit is defined, in which all the outputs of the digital core 10 and equally the outputs of the analog blocks 13 have a defined value in the case of an under-running voltage at the current supply connection(s). This value is to be the same as the value which is applied when the Power On Reset is applied to the digital core 10. In this case, all the data which is stored for example in memory elements such as RAM, signal memory, flip-flops, is not reset to zero.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
Abstract
This invention overcomes an undefined state of a mixed signal IC in case of an under voltage at the supply pin(s). It is almost undoable to design a circuit to detect an under voltage as well as a Power On Reset that works for the whole power supply voltage range that can be applied and is also very accurate to eliminate grey areas. In this invention two kinds of detection circuits (11, 12) are used. One to detect with high accuracy an under voltage on the power supply pin(s) and one to detect a necessary Power On Reset for the digital core (10). The accuracy of the latter circuit (12) can be much lower and therefore it is possible to design a circuit that will have the right functionality even if the power supply voltage is very low.
Description
POWER SUPPLY CONCEPT WITH NO GREY AREA'S
FIELD OF THE INVENTION
The present invention relates to a circuit arrangement in which a reset of a digital core is achieved via Power On Reset. Furthermore the invention relates to a method for resetting a digital core via Power On Reset using a circuit arrangement.
BACKGROUND OF THE INVENTION
Circuit arrangements of the a. m. type are known and common to the skilled in the art. Circuit arrangements of the type initially mentioned are used to eliminate grey areas in a current supply design of integrated circuits (IC), especially in automotive products used for safety critical applications (e. g. FlexRay applications).
In these applications it must be guaranteed that the IC is in a defined state regardless of the voltage(s) that is (are) present on the power supply pin(s). A digital core in a mixed signal IC needs a defined state and if this cannot be guaranteed, the digital core must be reset. This is normally depicted with Power On Reset.
The circuit arrangements known from the prior art, however, have the disadvantage that no mechanism is defined for the analog part in a mixed signal IC in the case of an under-running voltage at the current supply connections.
OBJECT AND SUMMARY OF THE INVENTION
Starting from the explained disadvantages as well as by considering the explained prior art for circuit arrangements of the a. m. art, the aim of the invention is to design a circuit arrangement of the a. m. type according to the preamble of claim 1 in such a way that a mechanism is defined for the analog part in a mixed signal IC in the case of an under-running voltage at the current supply connection.
This aim is achieved according to the invention by claim 1.
Advantageous refinements and further developments of the invention are characterized in the subclaims.
According to the invention the circuit arrangement comprises a detection circuit for under voltage detection on the power supply connection/connections and a detection circuit for the detection of a Power On Reset which is required for the digital core.
This invention describes a new state of a mixed signal IC in case of an under voltage at the supply pins. The advantage of the present invention is that an undefined state is overcome. As it is almost impossible to design a circuit to detect an under voltage as well as
a Power On Reset that works for the whole power supply voltage range that can be applied (mostly from O V to maximum voltage that may be applied to this pin) and is also very accurate to eliminate grey areas, the invention provides two types of detection circuits. One to detect with high accuracy an under voltage on the power supply pin(s) and one to detect a necessary Power On Reset for the digital core. The accuracy of the latter circuit can be much lower and therefore it is possible to design a circuit that will have the right functionality even if the power supply voltage is very low.
It is possible, within the scope of the invention, that all mixed signals are used. The invention is also able to apply to individual integrated circuits, supplied with current several times.
In the scope of the invention all analogue specifications points for a power supply range that includes the under voltage detection voltage at the supply pin(s) are guaranteed. Further it is defined an extra state of the integrated circuit in which all outputs of the digital core are as well as the output of the analog blocks of a mixed signal integrated circuit have a defined value in case of an under voltage on the power supply pin(s). This value should be the same as the value it got when a Power On Reset is applied to the digital core. In this case all information that is stored in memory elements (e. g. RAM, Latches, Flip-flops) will not be reset. If the power supply voltage of the digital core (V dig) becomes below a certain value at which it can't be guarantied that the memory elements memorize the data, the memory elements will be reset by an Power On rest of the complete digital core.
If an under voltage is detected on supply voltages Vcc and Vbat according to the invention it will be signaled to the digital core that will set the analog blocks and the outputs of the digital core in a defined state. If the voltage on Vdig becomes lower that the Power On Reset level, the complete digital core will be switched in reset state. If an under voltage is detected on supply voltages Vcc according to the invention it will be signaled to the digital core that will set the analog blocks and the outputs of the digital core in a defined state. If the voltage on Vcc becomes lower that the Power On Reset level, the complete digital core will be switched in reset state.
Therefore according to an advantageous development of the present invention the digital core comprises a voltage, whereby the digital core can be set into a reset state if the voltage is lower that the Power On Reset value and the voltage can be generated from at least two different supply voltages.
According to a further advantageous development of the present invention the digital core comprises analog blocks and outputs and the digital core sets the analog blocks and the outputs into a defined state when an under voltage is determined.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described in further detail below with the aid of example embodiments with reference to the figures, in which:
Fig. 1 shows a circuit arrangement according to the invention with a single supply voltage, and
Fig. 2 shows a circuit arrangement according to the invention with a supply voltage and with a further supply voltage.
DESCRIPTION OF EMBODIMENTS
In Figures 1 and 2, circuit arrangements according to the invention are shown, which are marked by reference number 100.
In the circuit arrangement 100 shown in Figure 1, a resetting of a digital core
10 takes place by means of a Power On Reset, in which the arrangement has a detection circuit 11 for the detection of an under-running voltage at the current supply connect ion(s), and a detection circuit 12 for the detection of a necessary Power On Reset for the digital core
10.
The circuit arrangement 100 has in addition analog blocks 13, inputs 14 and outputs 15. The digital core 10 sets the analog blocks 13 and its outputs into a defined state as soon as an under-running voltage is detected. All the analog blocks 13 are at a voltage Vcc. The circuit 11 is provided to detect the under-running voltage, which is coupled to the digital core 10 via an input 17. The further circuit 12 is provided, which lies at a supply voltage Vcc and has the necessary Power On Reset for the digital core 10.
The entire core is set into a reset state by means of the circuit 12 when the under-running voltage is lower than the Power On Reset level measured on the circuit 12. The digital core 10 has a voltage here in which the digital core 10 is able to be reset into a reset state when the voltage V is lower than an adjustment reset value which is generated on the circuit 12. The voltage range of the circuit arrangement 100 according to the invention which is present in the form of an integrated circuit lies between 4.75 and 5.25 V. The
detection of the under-running voltage on the circuit 11 can take place in a voltage range between 4.5 and 4.75 V, whereas the Power On Reset on the circuit 12 is between 3 and 4 V.
A further variant of the circuit arrangement 100 according to the invention can be seen from Figure 2, in which the circuit arrangement 100 also exists again here in the form of an integrated circuit. In the embodiment of the circuit arrangement 100 according to the invention shown in Figure 2, a resetting of the digital core 10 also takes place with a Power
On Reset, in which also in the embodiment shown in Figure 2 the arrangement has a detection circuit 11 for the detection of an under-running voltage at the power supply connection(s) and a detection circuit 12 for the detection of a necessary Power On Reset for the digital core 10. However, unlike the embodiment shown in Figure 1, the voltage V of the digital core 10 is able to be produced from at least two different supply voltages Vcc and
Vbat by a generator 16 which has a voltage Vcore at its output. In the circuit arrangement 100 all Vcc related specification points guarantied from 4.5 to 5.25 V, all Vbat related specification points guaranteed from 4.5 to 60V.
In addition, the following voltage ranges are provided in the circuit arrangement shown in Figure 2:
Vcc Operating range of the integrated circuit from 4.75 to 5.25 V; Vbat Operating range of the integrated circuit from 4.75 to 60V; Under voltage detection on Vcc from 4.5 to 4.75V;
Under voltage detection on Vbat from 4.5 to 4.75V; Power On Reset on Vdig from 3 to 4V;
Furthermore, an extra state of the integrated circuit is defined, in which all the outputs of the digital core 10 and equally the outputs of the analog blocks 13 have a defined value in the case of an under-running voltage at the current supply connection(s). This value is to be the same as the value which is applied when the Power On Reset is applied to the digital core 10. In this case, all the data which is stored for example in memory elements such as RAM, signal memory, flip-flops, is not reset to zero.
List of reference numbers
100 circuit arrangement 10 digital core
11 detection circuit
12 detection circuit
13 analog block
14 input 15 output
16 generator
17 input
Claims
1. A circuit arrangement (100) in which a reset of a digital core (10) is achieved via a Power On reset, characterized in that the arrangement comprises a detection circuit (11) for under voltage detection on the power supply connection/connections and a detection circuit (12) for the detection of a Power On reset which is required for the digital core (10).
2. A circuit arrangement according to claim 1, characterized in that the digital core (10) comprises analog blocks (13) and outputs.
3. A circuit arrangement according to claim 2, characterized in that the digital core (10) sets the analog blocks (13) and the outputs into a defined state when an under voltage is determined.
4. A circuit arrangement according to claim 3, characterized in that the entire core can be set into a reset state when the under voltage is lower than the Power On reset level.
5. A circuit arrangement according to any one of the above claims, character- ized in that the digital core (10) comprises a voltage V, whereby the digital core (10) can be set into a reset state if the voltage V is lower than the Power On reset value.
6. A circuit arrangement according to claim 5, characterized in that the voltage V can be generated from at least two different supply voltages.
7. A method for resetting a digital core (10) via a Power On reset using a circuit arrangement according to claim 1, characterized in that via a first detection circuit (11), an under voltage is detected on the power supply connection/connections, and via a second detection circuit (12), a Power On reset which is required for the digital core (10) is detected.
8. A method according to claim 7, characterized in that a determined under voltage of a supply voltage is indicated to the digital core (10), which sets analog blocks (13) and outputs of the digital core (10) into a defined state.
9. A method according to claim 8, characterized in that the entire digital core (10) is set into a reset state if the under voltage is lower than a Power On reset level.
10. A method according to claim 7, characterized in that the voltage of the digi- tal core (10) is generated from at least two different supply voltages, whereby the digital core
(10) sets analog blocks (13) and outputs of the digital core (10) into a defined state when an under voltage is determined on the supply voltages.
11. A method according to claim 10, characterized in that the entire digital core (10) is switched to the reset state if the voltage V is lower than the Power On reset value.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP07107623 | 2007-05-07 | ||
| EP07107623.6 | 2007-05-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008135874A1 true WO2008135874A1 (en) | 2008-11-13 |
Family
ID=39638981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2008/051500 Ceased WO2008135874A1 (en) | 2007-05-07 | 2008-04-18 | Power supply concept with no grey area´s |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2008135874A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6097225A (en) * | 1998-07-14 | 2000-08-01 | National Semiconductor Corporation | Mixed signal circuit with analog circuits producing valid reference signals |
| US6141764A (en) * | 1996-02-28 | 2000-10-31 | Dallas Semiconductor Corporation | Method for initializing an electronic device using a dual-state power-on-reset circuit |
| US20050198547A1 (en) * | 2004-03-05 | 2005-09-08 | Morse Douglas C. | Powering-up a device having digital and analog circuitry |
-
2008
- 2008-04-18 WO PCT/IB2008/051500 patent/WO2008135874A1/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6141764A (en) * | 1996-02-28 | 2000-10-31 | Dallas Semiconductor Corporation | Method for initializing an electronic device using a dual-state power-on-reset circuit |
| US6097225A (en) * | 1998-07-14 | 2000-08-01 | National Semiconductor Corporation | Mixed signal circuit with analog circuits producing valid reference signals |
| US20050198547A1 (en) * | 2004-03-05 | 2005-09-08 | Morse Douglas C. | Powering-up a device having digital and analog circuitry |
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