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WO2008123049A1 - 被膜形成方法及びそれに用いる樹脂組成物、絶縁膜を有する構造体及びその製造方法並びに電子部品 - Google Patents

被膜形成方法及びそれに用いる樹脂組成物、絶縁膜を有する構造体及びその製造方法並びに電子部品 Download PDF

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Publication number
WO2008123049A1
WO2008123049A1 PCT/JP2008/054916 JP2008054916W WO2008123049A1 WO 2008123049 A1 WO2008123049 A1 WO 2008123049A1 JP 2008054916 W JP2008054916 W JP 2008054916W WO 2008123049 A1 WO2008123049 A1 WO 2008123049A1
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Prior art keywords
film
resin composition
coating
film formation
pore
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Ceased
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PCT/JP2008/054916
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English (en)
French (fr)
Inventor
Ryuichi Okuda
Takayoshi Tanabe
Hirofumi Goto
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JSR Corp
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JSR Corp
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Priority claimed from JP2007307985A external-priority patent/JP2009133924A/ja
Application filed by JSR Corp filed Critical JSR Corp
Publication of WO2008123049A1 publication Critical patent/WO2008123049A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/022—Quinonediazides
    • G03F7/023—Macromolecular quinonediazides; Macromolecular additives, e.g. binders
    • G03F7/0233—Macromolecular quinonediazides; Macromolecular additives, e.g. binders characterised by the polymeric binders or the macromolecular additives other than the macromolecular quinonediazides
    • G03F7/0236—Condensation products of carbonyl compounds and phenolic compounds, e.g. novolak resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Formation Of Insulating Films (AREA)
  • Materials For Photolithography (AREA)

Abstract

　本発明の目的は、段差シリコン基板等に設けられた微細な有底の孔部や溝部における内壁面や底面に対して、均一な被膜を高精度且つ容易に形成することができる被膜形成方法及びそれに用いる樹脂組成物、絶縁膜を有する構造体及びその製造方法並びに電子部品を提供することである。本発明の被膜形成方法は、［１］（ａ）開口部の面積が２５～１００００μｍ２であり且つ深さが１０～２００μｍである孔部１１及び（ｂ）開口部の線幅が５～２００μｍであり且つ深さが１０～２００μｍである溝部１２のうちの少なくとも一方を有する段差基板１に、溶剤１３を塗布する溶剤塗布工程と、［２］ポジ型感光性樹脂組成物を、孔部１１及び溝部１２内の溶剤１３と接触するように、段差基板１に塗布する樹脂組成物塗布工程と、［３］塗膜１４を乾燥する乾燥工程と、を備えており、且つ、孔部１１並びに溝部１２における内壁面及び底面に樹脂成分を含む被膜１６を形成する。
PCT/JP2008/054916 2007-03-30 2008-03-17 被膜形成方法及びそれに用いる樹脂組成物、絶縁膜を有する構造体及びその製造方法並びに電子部品 Ceased WO2008123049A1 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007094364 2007-03-30
JP2007-094364 2007-03-30
JP2007307985A JP2009133924A (ja) 2007-11-28 2007-11-28 被膜形成方法及びそれに用いるポジ型感光性樹脂組成物
JP2007-307985 2007-11-28

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009150918A1 (ja) * 2008-06-11 2009-12-17 Jsr株式会社 絶縁性被膜を有する構造体及びその製造方法、ポジ型感光性樹脂組成物並びに電子部品
WO2010047264A1 (ja) * 2008-10-20 2010-04-29 住友ベークライト株式会社 スプレー塗布用ポジ型感光性樹脂組成物及びそれを用いた貫通電極の製造方法
WO2012036000A1 (ja) * 2010-09-16 2012-03-22 日立化成工業株式会社 ポジ型感光性樹脂組成物、レジストパターンの製造方法及び電子部品
NL2014598A (en) * 2015-04-08 2016-10-12 Suss Microtec Lithography Gmbh Method for coating a substrate.
CN110461085A (zh) * 2019-07-24 2019-11-15 沪士电子股份有限公司 一种可实现在阶梯槽内压接元器件的线路板及其制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103309152B (zh) * 2012-03-13 2018-08-28 东京应化工业株式会社 抗蚀图形的形成方法、图形形成方法、太阳能电池以及正型抗蚀组合物
JP6420793B2 (ja) * 2016-06-09 2018-11-07 株式会社タムラ製作所 硬化塗膜の形成方法

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JPS6458375A (en) * 1987-08-28 1989-03-06 Matsushita Electric Industrial Co Ltd Method for applying resist
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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009150918A1 (ja) * 2008-06-11 2009-12-17 Jsr株式会社 絶縁性被膜を有する構造体及びその製造方法、ポジ型感光性樹脂組成物並びに電子部品
JP5246259B2 (ja) * 2008-06-11 2013-07-24 Ｊｓｒ株式会社 絶縁性被膜を有する構造体及びその製造方法、ポジ型感光性樹脂組成物並びに電子部品
JP5545217B2 (ja) * 2008-10-20 2014-07-09 住友ベークライト株式会社 スプレー塗布用ポジ型感光性樹脂組成物及びそれを用いた貫通電極の製造方法
WO2010047264A1 (ja) * 2008-10-20 2010-04-29 住友ベークライト株式会社 スプレー塗布用ポジ型感光性樹脂組成物及びそれを用いた貫通電極の製造方法
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CN103097954A (zh) * 2010-09-16 2013-05-08 日立化成株式会社 正型感光性树脂组合物、抗蚀图形的制造方法和电子部件
WO2012036000A1 (ja) * 2010-09-16 2012-03-22 日立化成工業株式会社 ポジ型感光性樹脂組成物、レジストパターンの製造方法及び電子部品
JP5915532B2 (ja) * 2010-09-16 2016-05-11 日立化成株式会社 ポジ型感光性樹脂組成物、レジストパターンの製造方法及び電子部品
NL2014598A (en) * 2015-04-08 2016-10-12 Suss Microtec Lithography Gmbh Method for coating a substrate.
US9799554B2 (en) 2015-04-08 2017-10-24 Suss Microtec Lithography Gmbh Method for coating a substrate
AT516988A3 (de) * 2015-04-08 2018-04-15 Suss Microtec Lithography Gmbh Verfahren zum Beschichten eines Substrats
AT516988B1 (de) * 2015-04-08 2022-10-15 Suss Microtec Lithography Gmbh Verfahren zum Beschichten eines Substrats
CN110461085A (zh) * 2019-07-24 2019-11-15 沪士电子股份有限公司 一种可实现在阶梯槽内压接元器件的线路板及其制作方法
CN110461085B (zh) * 2019-07-24 2021-05-11 沪士电子股份有限公司 一种可实现在阶梯槽内压接元器件的线路板及其制作方法

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