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WO2008120333A1 - 可変抵抗メモリ及びそのデータ書込み方法 - Google Patents

可変抵抗メモリ及びそのデータ書込み方法 Download PDF

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Publication number
WO2008120333A1
WO2008120333A1 PCT/JP2007/056712 JP2007056712W WO2008120333A1 WO 2008120333 A1 WO2008120333 A1 WO 2008120333A1 JP 2007056712 W JP2007056712 W JP 2007056712W WO 2008120333 A1 WO2008120333 A1 WO 2008120333A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
data
storage state
memory cells
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/056712
Other languages
English (en)
French (fr)
Inventor
Masaki Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2009507325A priority Critical patent/JP5062251B2/ja
Priority to PCT/JP2007/056712 priority patent/WO2008120333A1/ja
Publication of WO2008120333A1 publication Critical patent/WO2008120333A1/ja
Priority to US12/561,797 priority patent/US7924601B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

　本発明のＲｅＲＡＭは、それぞれ複数の抵抗変化素子が配設されてなる高速書き込み領域（１）と主メモリ領域（２）とを備えており、データの書き込みに際して、高速書き込み領域（１）において、メモリセルアレイ（１１）における全てのメモリセル（１０）が無記憶状態にリセットされた初期状態とされており、高速書き込み領域（１）において、データに対応したメモリセル（１０）のうちで記憶状態に指定されたもののみを記憶状態にセットし、メモリセルアレイ（１１）に書き込まれたデータを主メモリ領域（２）に転送し、主メモリ領域（２）において、高速書き込み領域（１）から転送されたデータに対応したメモリセルアレイ（２１）のメモリセル（１０）を無記憶状態にリセットした後、メモリセル（１０）のうちで記憶状態に指定されたもののみをセットし、高速書き込み領域（１）において、全てのメモリセル（１０）を無記憶状態にリセットして初期状態とする。この構成により、データの高速書き込み機能及び不揮発状態でデータを保持する機能を、ＳＲＡＭのような別のメモリチップを組み合わせることなく、ＲｅＲＡＭのみで実現し、一回の書き込み命令によりデータの高速書き込みを行なう用途の要求に応えることができる。
PCT/JP2007/056712 2007-03-28 2007-03-28 可変抵抗メモリ及びそのデータ書込み方法 Ceased WO2008120333A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009507325A JP5062251B2 (ja) 2007-03-28 2007-03-28 可変抵抗メモリ及びそのデータ書込み方法
PCT/JP2007/056712 WO2008120333A1 (ja) 2007-03-28 2007-03-28 可変抵抗メモリ及びそのデータ書込み方法
US12/561,797 US7924601B2 (en) 2007-03-28 2009-09-17 Resistive memory and data write-in method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056712 WO2008120333A1 (ja) 2007-03-28 2007-03-28 可変抵抗メモリ及びそのデータ書込み方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/561,797 Continuation US7924601B2 (en) 2007-03-28 2009-09-17 Resistive memory and data write-in method

Publications (1)

Publication Number Publication Date
WO2008120333A1 true WO2008120333A1 (ja) 2008-10-09

Family

ID=39807926

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056712 Ceased WO2008120333A1 (ja) 2007-03-28 2007-03-28 可変抵抗メモリ及びそのデータ書込み方法

Country Status (3)

Country Link
US (1) US7924601B2 (ja)
JP (1) JP5062251B2 (ja)
WO (1) WO2008120333A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018151088A1 (ja) * 2017-02-14 2018-08-23 国立大学法人東北大学 メモリ装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8000127B2 (en) * 2009-08-12 2011-08-16 Nantero, Inc. Method for resetting a resistive change memory element
US9588888B2 (en) * 2010-07-30 2017-03-07 Hewlett Packard Enterprise Development Lp Memory device and method for altering performance characteristic based on bandwidth demand
US9312002B2 (en) 2014-04-04 2016-04-12 Sandisk Technologies Inc. Methods for programming ReRAM devices
KR102646755B1 (ko) 2017-01-06 2024-03-11 삼성전자주식회사 저항 변화 물질을 포함하는 메모리 장치 및 그 구동 방법
KR102684082B1 (ko) 2017-01-13 2024-07-10 삼성전자주식회사 저항 변화 물질을 포함하는 메모리 장치 및 그 구동 방법
TWI698876B (zh) * 2019-09-11 2020-07-11 華邦電子股份有限公司 資料寫入方法及非揮發性記憶體
TWI751537B (zh) 2020-04-24 2022-01-01 華邦電子股份有限公司 電阻式記憶體儲存裝置及其操作方法
US12131777B2 (en) 2021-09-30 2024-10-29 Weebit Nano Ltd. Resistive random-access memory (ReRAM) cell optimized for reset and set currents

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000003596A (ja) * 1998-06-15 2000-01-07 Hitachi Ltd 半導体記憶装置
WO2007023569A1 (ja) * 2005-08-26 2007-03-01 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0433029A (ja) 1990-05-24 1992-02-04 Matsushita Electric Ind Co Ltd メモリ装置とその駆動方法
JPH11306073A (ja) 1998-04-23 1999-11-05 Sharp Corp 情報処理装置
JP2003015954A (ja) 2001-06-28 2003-01-17 Sharp Corp 半導体記憶装置および情報機器、半導体記憶装置のアクセス期間設定方法
JP2004185755A (ja) * 2002-12-05 2004-07-02 Sharp Corp 不揮発性半導体記憶装置
KR100558548B1 (ko) * 2003-11-27 2006-03-10 삼성전자주식회사 상변화 메모리 소자에서의 라이트 드라이버 회로 및라이트 전류 인가방법
US7330369B2 (en) * 2004-04-06 2008-02-12 Bao Tran NANO-electronic memory array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000003596A (ja) * 1998-06-15 2000-01-07 Hitachi Ltd 半導体記憶装置
WO2007023569A1 (ja) * 2005-08-26 2007-03-01 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018151088A1 (ja) * 2017-02-14 2018-08-23 国立大学法人東北大学 メモリ装置
JPWO2018151088A1 (ja) * 2017-02-14 2019-12-12 国立大学法人東北大学 メモリ装置
US10957371B2 (en) 2017-02-14 2021-03-23 Tohoku University Memory device that enables direct block copying between cell configurations in different operation modes
JP6995377B2 (ja) 2017-02-14 2022-02-04 国立大学法人東北大学 メモリ装置

Also Published As

Publication number Publication date
US20100157655A1 (en) 2010-06-24
JPWO2008120333A1 (ja) 2010-07-15
US7924601B2 (en) 2011-04-12
JP5062251B2 (ja) 2012-10-31

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