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WO2008105101A1 - 貼り合わせ基板の製造方法および貼り合わせ基板 - Google Patents

貼り合わせ基板の製造方法および貼り合わせ基板 Download PDF

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Publication number
WO2008105101A1
WO2008105101A1 PCT/JP2007/053839 JP2007053839W WO2008105101A1 WO 2008105101 A1 WO2008105101 A1 WO 2008105101A1 JP 2007053839 W JP2007053839 W JP 2007053839W WO 2008105101 A1 WO2008105101 A1 WO 2008105101A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
laminated substrate
oxide film
laminated
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053839
Other languages
English (en)
French (fr)
Inventor
Shoji Akiyama
Atsuo Ito
Yoshihiro Kubota
Koichi Tanaka
Makoto Kawai
Yuuji Tobisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Priority to PCT/JP2007/053839 priority Critical patent/WO2008105101A1/ja
Priority to EP07737557.4A priority patent/EP2128891B1/en
Priority to KR1020097018013A priority patent/KR101335713B1/ko
Publication of WO2008105101A1 publication Critical patent/WO2008105101A1/ja
Priority to US12/550,340 priority patent/US8765576B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10P90/1916—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/139—Manufacture or treatment of devices covered by this subclass using temporary substrates
    • H10P90/1914—
    • H10P95/00—
    • H10P95/06—
    • H10W10/181—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Landscapes

  • Engineering & Computer Science (AREA)
  • Element Separation (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

　貼り合わせ基板の製造方法であって、少なくとも、ヤング率で１５０ＧＰａ以上の硬度を有する第１の基板表面に酸化膜を形成した後、該酸化膜を平坦化する工程と、第２の基板表面から水素イオンまたは希ガスイオンあるいはこれらの混合ガスイオンをイオン注入して基板内部にイオン注入層を形成する工程と、前記第１の基板および第２の基板を少なくとも前記酸化膜を介して貼り合わせた後、前記第２の基板を前記イオン注入層で剥離して貼り合わせ基板を得る工程と、該貼り合わせ基板を熱処理して前記酸化膜を外方拡散する工程とを有する。
PCT/JP2007/053839 2007-02-28 2007-02-28 貼り合わせ基板の製造方法および貼り合わせ基板 Ceased WO2008105101A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/053839 WO2008105101A1 (ja) 2007-02-28 2007-02-28 貼り合わせ基板の製造方法および貼り合わせ基板
EP07737557.4A EP2128891B1 (en) 2007-02-28 2007-02-28 Process for producing laminated substrate
KR1020097018013A KR101335713B1 (ko) 2007-02-28 2007-02-28 접합 기판의 제조방법 및 접합 기판
US12/550,340 US8765576B2 (en) 2007-02-28 2009-08-28 Process for producing laminated substrate and laminated substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053839 WO2008105101A1 (ja) 2007-02-28 2007-02-28 貼り合わせ基板の製造方法および貼り合わせ基板

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/550,340 Continuation US8765576B2 (en) 2007-02-28 2009-08-28 Process for producing laminated substrate and laminated substrate

Publications (1)

Publication Number Publication Date
WO2008105101A1 true WO2008105101A1 (ja) 2008-09-04

Family

ID=39720945

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053839 Ceased WO2008105101A1 (ja) 2007-02-28 2007-02-28 貼り合わせ基板の製造方法および貼り合わせ基板

Country Status (4)

Country Link
US (1) US8765576B2 (ja)
EP (1) EP2128891B1 (ja)
KR (1) KR101335713B1 (ja)
WO (1) WO2008105101A1 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010278338A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 界面近傍における欠陥密度が低いｓｏｓ基板
JP2010278337A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 表面欠陥密度が少ないｓｏｓ基板
JP2014003319A (ja) * 2013-08-22 2014-01-09 Shin Etsu Chem Co Ltd 表面欠陥密度が少ないｓｏｓ基板
JP2014003320A (ja) * 2013-08-22 2014-01-09 Shin Etsu Chem Co Ltd 界面近傍における欠陥密度が低いｓｏｓ基板
WO2014020906A1 (ja) * 2012-07-30 2014-02-06 住友化学株式会社 複合基板の製造方法および半導体結晶層形成基板の製造方法
JPWO2014080874A1 (ja) * 2012-11-22 2017-01-05 信越化学工業株式会社 複合基板の製造方法及び複合基板

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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US8546238B2 (en) * 2009-04-22 2013-10-01 Commissariat A L'energie Atomique Et Aux Energies Method for transferring at least one micro-technological layer
US8357974B2 (en) * 2010-06-30 2013-01-22 Corning Incorporated Semiconductor on glass substrate with stiffening layer and process of making the same
US9947688B2 (en) 2011-06-22 2018-04-17 Psemi Corporation Integrated circuits with components on both sides of a selected substrate and methods of fabrication
US20130154049A1 (en) * 2011-06-22 2013-06-20 George IMTHURN Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology
EP2736065B1 (en) * 2012-07-18 2017-09-06 NGK Insulators, Ltd. Composite wafer and manufacturing method therefor
WO2015125770A1 (ja) * 2014-02-18 2015-08-27 日本碍子株式会社 半導体用複合基板のハンドル基板および半導体用複合基板
EP3993018B1 (en) * 2017-07-14 2024-09-11 Sunedison Semiconductor Limited Method of manufacture of a semiconductor on insulator structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1083962A (ja) 1996-09-06 1998-03-31 Asahi Chem Ind Co Ltd Ｓｏｓ基板の形成方法およびそれを用いた半導体装置
JP2002164520A (ja) * 2000-11-27 2002-06-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
JP2003066427A (ja) * 2001-08-30 2003-03-05 Seiko Epson Corp 電気光学装置用基板の製造方法、電気光学装置用基板、電気光学装置及び電子機器
JP2004087768A (ja) * 2002-08-27 2004-03-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
JP2004221198A (ja) * 2003-01-10 2004-08-05 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP2006043281A (ja) 2004-08-06 2006-02-16 Olympia:Kk 遊技システム
JP2006517734A (ja) * 2003-02-12 2006-07-27 エス　オー　イ　テク　シリコン　オン　インシュレータ　テクノロジース 極度に粗れた基板上の半導体構造
JP2006295037A (ja) * 2005-04-14 2006-10-26 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4273540B2 (ja) 1998-07-21 2009-06-03 株式会社Ｓｕｍｃｏ 貼り合わせ半導体基板及びその製造方法
US7198671B2 (en) * 2001-07-11 2007-04-03 Matsushita Electric Industrial Co., Ltd. Layered substrates for epitaxial processing, and device
EP1408551B1 (en) * 2001-07-17 2014-07-02 Shin-Etsu Handotai Co., Ltd. Method for producing bonding wafer
CN1186457C (zh) 2001-08-29 2005-01-26 曹卫 均相基因矩阵
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
JP2003282845A (ja) 2002-03-20 2003-10-03 Mitsubishi Electric Corp 炭化ケイ素基板の製造方法およびその製造方法により製造された炭化ケイ素基板、ならびに、ショットキーバリアダイオードおよび炭化ケイ素薄膜の製造方法
JP4147577B2 (ja) 2002-07-18 2008-09-10 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US7129123B2 (en) * 2002-08-27 2006-10-31 Shin-Etsu Handotai Co., Ltd. SOI wafer and a method for producing an SOI wafer
FR2846788B1 (fr) 2002-10-30 2005-06-17 Procede de fabrication de substrats demontables
US20040126993A1 (en) * 2002-12-30 2004-07-01 Chan Kevin K. Low temperature fusion bonding with high surface energy using a wet chemical treatment
US6989314B2 (en) * 2003-02-12 2006-01-24 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure and method of making same
JP2005024918A (ja) 2003-07-02 2005-01-27 Mitsubishi Electric Corp 表示制御装置
JP2005085964A (ja) 2003-09-08 2005-03-31 Sumitomo Mitsubishi Silicon Corp 貼り合わせ基板の製造方法
US7544583B2 (en) 2003-09-08 2009-06-09 Sumco Corporation SOI wafer and its manufacturing method
FR2871172B1 (fr) * 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication
JP4730581B2 (ja) 2004-06-17 2011-07-20 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5364368B2 (ja) * 2005-04-21 2013-12-11 エイオーネックス・テクノロジーズ・インコーポレイテッド 基板の製造方法
FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
JP2007227415A (ja) 2006-02-21 2007-09-06 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法および貼り合わせ基板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1083962A (ja) 1996-09-06 1998-03-31 Asahi Chem Ind Co Ltd Ｓｏｓ基板の形成方法およびそれを用いた半導体装置
JP2002164520A (ja) * 2000-11-27 2002-06-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
JP2003066427A (ja) * 2001-08-30 2003-03-05 Seiko Epson Corp 電気光学装置用基板の製造方法、電気光学装置用基板、電気光学装置及び電子機器
JP2004087768A (ja) * 2002-08-27 2004-03-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
JP2004221198A (ja) * 2003-01-10 2004-08-05 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP2006517734A (ja) * 2003-02-12 2006-07-27 エス　オー　イ　テク　シリコン　オン　インシュレータ　テクノロジース 極度に粗れた基板上の半導体構造
JP2006043281A (ja) 2004-08-06 2006-02-16 Olympia:Kk 遊技システム
JP2006295037A (ja) * 2005-04-14 2006-10-26 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2128891A4

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010278338A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 界面近傍における欠陥密度が低いｓｏｓ基板
JP2010278337A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 表面欠陥密度が少ないｓｏｓ基板
EP2437282A4 (en) * 2009-05-29 2012-11-28 Shinetsu Chemical Co SOS SUBSTRATE WITH LOW SURFACE DEFECT DENSITY NEAR INTERFACE
EP2437281A4 (en) * 2009-05-29 2013-01-16 Shinetsu Chemical Co SOS SUBSTRATE WITH LOW SURFACE DEFECT DENSITY
US9214379B2 (en) 2009-05-29 2015-12-15 Shin-Etsu Chemical Co., Ltd. SOS substrate having low defect density in vicinity of interface
US9214380B2 (en) 2009-05-29 2015-12-15 Shin-Etsu Chemical Co., Ltd. SOS substrate having low surface defect density
WO2014020906A1 (ja) * 2012-07-30 2014-02-06 住友化学株式会社 複合基板の製造方法および半導体結晶層形成基板の製造方法
JPWO2014080874A1 (ja) * 2012-11-22 2017-01-05 信越化学工業株式会社 複合基板の製造方法及び複合基板
JP2014003319A (ja) * 2013-08-22 2014-01-09 Shin Etsu Chem Co Ltd 表面欠陥密度が少ないｓｏｓ基板
JP2014003320A (ja) * 2013-08-22 2014-01-09 Shin Etsu Chem Co Ltd 界面近傍における欠陥密度が低いｓｏｓ基板

Also Published As

Publication number Publication date
US20100084746A1 (en) 2010-04-08
KR101335713B1 (ko) 2013-12-04
EP2128891B1 (en) 2015-09-02
US8765576B2 (en) 2014-07-01
KR20100014873A (ko) 2010-02-11
EP2128891A4 (en) 2011-07-06
EP2128891A1 (en) 2009-12-02

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