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WO2008155850A1 - キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム - Google Patents

キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム Download PDF

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Publication number
WO2008155850A1
WO2008155850A1 PCT/JP2007/062464 JP2007062464W WO2008155850A1 WO 2008155850 A1 WO2008155850 A1 WO 2008155850A1 JP 2007062464 W JP2007062464 W JP 2007062464W WO 2008155850 A1 WO2008155850 A1 WO 2008155850A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
ram
cache
ecc
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/062464
Other languages
English (en)
French (fr)
Inventor
Takashi Miura
Iwao Yamazaki
Takahito Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2009520204A priority Critical patent/JP4764945B2/ja
Priority to PCT/JP2007/062464 priority patent/WO2008155850A1/ja
Priority to EP07767302A priority patent/EP2169555A4/en
Publication of WO2008155850A1 publication Critical patent/WO2008155850A1/ja
Priority to US12/654,442 priority patent/US8533565B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　キャッシュメモリ制御部は、演算器より送信された８バイトのストアデータを保持する複数のＳＴＢと、複数のＷＢと、ＤＡＴＡ－ＲＡＭと、ＦＣＤＲと、ＥＣＣ－ＲＡＭとを備える。このような構成において、キャッシュメモリ制御部は、ストア対象外となるデータをＤＡＴＡ－ＲＡＭから取得してＦＣＤＲに格納し、格納したデータを、演算器より出力されてＳＴＢまたはＷＢに格納されているストアデータのストア対象データとマージして新たなストアデータを生成する。そして、キャッシュメモリ制御部は、生成した新たなストアデータをＤＡＴＡ－ＲＡＭに書き込むとともに、新たなストアデータからＥＣＣを生成してＥＣＣ－ＲＡＭに書き込む。
PCT/JP2007/062464 2007-06-20 2007-06-20 キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム Ceased WO2008155850A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009520204A JP4764945B2 (ja) 2007-06-20 2007-06-20 キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム
PCT/JP2007/062464 WO2008155850A1 (ja) 2007-06-20 2007-06-20 キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム
EP07767302A EP2169555A4 (en) 2007-06-20 2007-06-20 CACHE CONTROL, CACHE CONTROL PROCEDURE AND CACHE CONTROL PROGRAM
US12/654,442 US8533565B2 (en) 2007-06-20 2009-12-18 Cache controller and cache controlling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062464 WO2008155850A1 (ja) 2007-06-20 2007-06-20 キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,442 Continuation US8533565B2 (en) 2007-06-20 2009-12-18 Cache controller and cache controlling method

Publications (1)

Publication Number Publication Date
WO2008155850A1 true WO2008155850A1 (ja) 2008-12-24

Family

ID=40156016

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062464 Ceased WO2008155850A1 (ja) 2007-06-20 2007-06-20 キャッシュ制御装置、キャッシュ制御方法およびキャッシュ制御プログラム

Country Status (4)

Country Link
US (1) US8533565B2 (ja)
EP (1) EP2169555A4 (ja)
JP (1) JP4764945B2 (ja)
WO (1) WO2008155850A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11416334B2 (en) * 2019-05-24 2022-08-16 Texas Instmments Incorporated Handling non-correctable errors

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01185753A (ja) 1988-01-21 1989-07-25 Nec Corp 記憶装置
JPH03108041A (ja) 1989-09-19 1991-05-08 Internatl Business Mach Corp <Ibm> パイプライン式エラー検査／訂正キヤツシユ・メモリ及びキヤツシユ・メモリ・アレイ
JPH08286977A (ja) * 1995-04-14 1996-11-01 Kofu Nippon Denki Kk ストアインキャッシュの障害処理システム
JPH10232789A (ja) 1997-02-19 1998-09-02 Hitachi Ltd Ｅｃｃパーシャルライト制御ユニット
JP2004038341A (ja) * 2002-06-28 2004-02-05 Fujitsu Ltd 記憶制御装置およびデータ格納方法
JP2004514184A (ja) 1999-08-17 2004-05-13 サン・マイクロシステムズ・インコーポレーテッド デジタル・データにおけるソフト・エラーを訂正するための方法および装置

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US3814921A (en) * 1972-11-15 1974-06-04 Honeywell Inf Systems Apparatus and method for a memory partial-write of error correcting encoded data
US5313475A (en) * 1991-10-31 1994-05-17 International Business Machines Corporation ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme
JPH06119238A (ja) * 1992-10-07 1994-04-28 Hitachi Ltd 主記憶制御方法および装置
JP3534917B2 (ja) * 1995-11-08 2004-06-07 株式会社日立製作所 メモリアクセス制御方法
US6366984B1 (en) * 1999-05-11 2002-04-02 Intel Corporation Write combining buffer that supports snoop request
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6804162B1 (en) * 2001-04-05 2004-10-12 T-Ram, Inc. Read-modify-write memory using read-or-write banks
US6848071B2 (en) * 2001-04-23 2005-01-25 Sun Microsystems, Inc. Method and apparatus for updating an error-correcting code during a partial line store
US6988172B2 (en) * 2002-04-29 2006-01-17 Ip-First, Llc Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
US20070044003A1 (en) * 2005-08-04 2007-02-22 Jack Doweck Method and apparatus of detecting and correcting soft error
CN101336418B (zh) * 2006-01-31 2011-02-09 富士通株式会社 纠错码生成方法以及存储器管理装置
JP4791525B2 (ja) * 2006-02-14 2011-10-12 富士通株式会社 読み出し処理装置および読み出し方法
US7617437B2 (en) * 2006-02-21 2009-11-10 Freescale Semiconductor, Inc. Error correction device and method thereof
US20080235461A1 (en) * 2007-03-22 2008-09-25 Sin Tan Technique and apparatus for combining partial write transactions
US7836262B2 (en) * 2007-06-05 2010-11-16 Apple Inc. Converting victim writeback to a fill
US8086936B2 (en) * 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01185753A (ja) 1988-01-21 1989-07-25 Nec Corp 記憶装置
JPH03108041A (ja) 1989-09-19 1991-05-08 Internatl Business Mach Corp <Ibm> パイプライン式エラー検査／訂正キヤツシユ・メモリ及びキヤツシユ・メモリ・アレイ
JPH08286977A (ja) * 1995-04-14 1996-11-01 Kofu Nippon Denki Kk ストアインキャッシュの障害処理システム
JPH10232789A (ja) 1997-02-19 1998-09-02 Hitachi Ltd Ｅｃｃパーシャルライト制御ユニット
JP2004514184A (ja) 1999-08-17 2004-05-13 サン・マイクロシステムズ・インコーポレーテッド デジタル・データにおけるソフト・エラーを訂正するための方法および装置
JP2004038341A (ja) * 2002-06-28 2004-02-05 Fujitsu Ltd 記憶制御装置およびデータ格納方法

Also Published As

Publication number Publication date
JPWO2008155850A1 (ja) 2010-08-26
US20100107038A1 (en) 2010-04-29
EP2169555A4 (en) 2011-01-05
EP2169555A1 (en) 2010-03-31
JP4764945B2 (ja) 2011-09-07
US8533565B2 (en) 2013-09-10

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