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WO2008155847A1 - 処理装置 - Google Patents

処理装置 Download PDF

Info

Publication number
WO2008155847A1
WO2008155847A1 PCT/JP2007/062454 JP2007062454W WO2008155847A1 WO 2008155847 A1 WO2008155847 A1 WO 2008155847A1 JP 2007062454 W JP2007062454 W JP 2007062454W WO 2008155847 A1 WO2008155847 A1 WO 2008155847A1
Authority
WO
WIPO (PCT)
Prior art keywords
command
command buffer
read out
sequence
start point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/062454
Other languages
English (en)
French (fr)
Inventor
Megumi Yokoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2009520201A priority Critical patent/JP5099133B2/ja
Priority to PCT/JP2007/062454 priority patent/WO2008155847A1/ja
Priority to EP20070767292 priority patent/EP2169540A4/en
Publication of WO2008155847A1 publication Critical patent/WO2008155847A1/ja
Priority to US12/654,298 priority patent/US20100106943A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

　ループの起点を固定せずにループとなる命令のフェッチを簡易な構成で実現する。命令バッファと、命令デコーダと、前記命令バッファに対応して設けられ、一の命令バッファに格納された命令列が読み出される場合に、次に読み出されるべき命令列が格納された他の命令バッファの識別情報により、一の命令バッファと他の命令バッファ間の接続関係を示すポインタと、命令列の処理がループ状の繰り返しになるような所定命令の命令フェッチを行う場合に繰り返しの起点となる命令列が格納された命令バッファの識別情報を記憶した起点記憶部とを有する処理装置の処理方法であって、一の命令バッファに格納された命令列を読み出し、該命令列から所定命令を検出した場合に、起点記憶部に記憶した識別情報を次に読み出す命令バッファの識別情報としてポインタに設定する。
PCT/JP2007/062454 2007-06-20 2007-06-20 処理装置 Ceased WO2008155847A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009520201A JP5099133B2 (ja) 2007-06-20 2007-06-20 処理装置
PCT/JP2007/062454 WO2008155847A1 (ja) 2007-06-20 2007-06-20 処理装置
EP20070767292 EP2169540A4 (en) 2007-06-20 2007-06-20 PROCESSING DEVICE
US12/654,298 US20100106943A1 (en) 2007-06-20 2009-12-16 Processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062454 WO2008155847A1 (ja) 2007-06-20 2007-06-20 処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,298 Continuation US20100106943A1 (en) 2007-06-20 2009-12-16 Processing device

Publications (1)

Publication Number Publication Date
WO2008155847A1 true WO2008155847A1 (ja) 2008-12-24

Family

ID=40156013

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062454 Ceased WO2008155847A1 (ja) 2007-06-20 2007-06-20 処理装置

Country Status (4)

Country Link
US (1) US20100106943A1 (ja)
EP (1) EP2169540A4 (ja)
JP (1) JP5099133B2 (ja)
WO (1) WO2008155847A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10318433B2 (en) * 2016-12-20 2019-06-11 Texas Instruments Incorporated Streaming engine with multi dimensional circular addressing selectable at each dimension

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3804941B2 (ja) * 2002-06-28 2006-08-02 富士通株式会社 命令フェッチ制御装置
WO2006112190A1 (ja) * 2005-04-08 2006-10-26 Matsushita Electric Industrial Co., Ltd. プロセッサ

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3203701B2 (ja) * 1990-11-01 2001-08-27 インターナショナル・ビジネス・マシーンズ・コーポレーション コードセグメントのリンク方法とそのシステム及びコードセグメントのダイナミックリンク方法
WO1993017385A1 (en) * 1992-02-27 1993-09-02 Intel Corporation Dynamic flow instruction cache memory
JP3683968B2 (ja) * 1996-02-09 2005-08-17 富士通株式会社 情報処理装置
KR100347865B1 (ko) * 1999-11-15 2002-08-09 삼성전자 주식회사 어드레스 트레이스를 이용한 분기 예측 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3804941B2 (ja) * 2002-06-28 2006-08-02 富士通株式会社 命令フェッチ制御装置
WO2006112190A1 (ja) * 2005-04-08 2006-10-26 Matsushita Electric Industrial Co., Ltd. プロセッサ

Also Published As

Publication number Publication date
JPWO2008155847A1 (ja) 2010-08-26
EP2169540A4 (en) 2010-09-15
EP2169540A1 (en) 2010-03-31
US20100106943A1 (en) 2010-04-29
JP5099133B2 (ja) 2012-12-12

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