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WO2008152911A1 - Semiconductor device, and its manufacturing method - Google Patents

Semiconductor device, and its manufacturing method Download PDF

Info

Publication number
WO2008152911A1
WO2008152911A1 PCT/JP2008/059790 JP2008059790W WO2008152911A1 WO 2008152911 A1 WO2008152911 A1 WO 2008152911A1 JP 2008059790 W JP2008059790 W JP 2008059790W WO 2008152911 A1 WO2008152911 A1 WO 2008152911A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor substrate
drift region
enabled
reduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/059790
Other languages
French (fr)
Japanese (ja)
Inventor
Kazuhiko Kusuda
Takuya Sunada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Panasonic Electric Works Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007220440A external-priority patent/JP2009016775A/en
Application filed by Panasonic Electric Works Co Ltd filed Critical Panasonic Electric Works Co Ltd
Publication of WO2008152911A1 publication Critical patent/WO2008152911A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies

Landscapes

  • Thin Film Transistor (AREA)

Abstract

Provided are a semiconductor device having a drift region on one surface of a semiconductor substrate, and its manufacturing method. A simple constitution is enabled to realize the reduction of a parasitic capacitance and to raise a high withstand voltage by removing the semiconductor substrate at least partially, and is enabled to realize the reduction of the cost by improving a sufficient mechanical strength and a production yield. The semiconductor device (1) includes a drift region (3) (a region defined by right and left broken lines) on one surface (21) of a semiconductor substrate (2). At least one portion of the semiconductor substrate (2) is removed from the side of the other surface (22) to form the drift region (3) or a removed portion (23) leading to the vicinity of the former, and the removed portion (23) is filled with an insulating member (4) of glass or resin. The semiconductor device (1) is enabled to realize the reduction of the parasitic capacitance and the high withstand voltage by forming the removed portion (23) in the lower portion of the drift region (3), and to realize the sufficient mechanical strength by filling the insulating member (4).
PCT/JP2008/059790 2007-06-08 2008-05-28 Semiconductor device, and its manufacturing method Ceased WO2008152911A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007152621 2007-06-08
JP2007-152621 2007-06-08
JP2007-220440 2007-08-27
JP2007220440A JP2009016775A (en) 2007-06-08 2007-08-27 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2008152911A1 true WO2008152911A1 (en) 2008-12-18

Family

ID=40129522

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/059790 Ceased WO2008152911A1 (en) 2007-06-08 2008-05-28 Semiconductor device, and its manufacturing method

Country Status (1)

Country Link
WO (1) WO2008152911A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002025700A2 (en) * 2000-09-21 2002-03-28 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
WO2004004013A1 (en) * 2002-06-26 2004-01-08 Cambridge Semiconductor Limited Lateral semiconductor device
WO2004053993A1 (en) * 2002-12-10 2004-06-24 Power Electronics Design Centre Power integrated circuits
JP2007059595A (en) * 2005-08-24 2007-03-08 Toshiba Corp Nitride semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002025700A2 (en) * 2000-09-21 2002-03-28 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
WO2004004013A1 (en) * 2002-06-26 2004-01-08 Cambridge Semiconductor Limited Lateral semiconductor device
WO2004053993A1 (en) * 2002-12-10 2004-06-24 Power Electronics Design Centre Power integrated circuits
JP2007059595A (en) * 2005-08-24 2007-03-08 Toshiba Corp Nitride semiconductor device

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