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WO2008150927A3 - System including a fine-grained memory and a less-fine-grained memory - Google Patents

System including a fine-grained memory and a less-fine-grained memory Download PDF

Info

Publication number
WO2008150927A3
WO2008150927A3 PCT/US2008/065167 US2008065167W WO2008150927A3 WO 2008150927 A3 WO2008150927 A3 WO 2008150927A3 US 2008065167 W US2008065167 W US 2008065167W WO 2008150927 A3 WO2008150927 A3 WO 2008150927A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
fine
page
grained
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/065167
Other languages
French (fr)
Other versions
WO2008150927A2 (en
Inventor
Tom Mcwilliams
Earl T Cohen
James M Bodwin
Ulrich Bruening
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Schooner Information Technology Inc
Original Assignee
Schooner Information Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schooner Information Technology Inc filed Critical Schooner Information Technology Inc
Priority to US12/130,661 priority Critical patent/US7975109B2/en
Priority to US12/197,899 priority patent/US8732386B2/en
Priority to US12/276,540 priority patent/US8229945B2/en
Publication of WO2008150927A2 publication Critical patent/WO2008150927A2/en
Publication of WO2008150927A3 publication Critical patent/WO2008150927A3/en
Anticipated expiration legal-status Critical
Priority to US13/149,851 priority patent/US8244969B2/en
Priority to US13/528,064 priority patent/US8667001B2/en
Priority to US13/584,755 priority patent/US8667212B2/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
PCT/US2008/065167 2007-05-30 2008-05-29 System including a fine-grained memory and a less-fine-grained memory Ceased WO2008150927A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US12/130,661 US7975109B2 (en) 2007-05-30 2008-05-30 System including a fine-grained memory and a less-fine-grained memory
US12/197,899 US8732386B2 (en) 2008-03-20 2008-08-25 Sharing data fabric for coherent-distributed caching of multi-node shared-distributed flash memory
US12/276,540 US8229945B2 (en) 2008-03-20 2008-11-24 Scalable database management software on a cluster of nodes using a shared-distributed flash memory
US13/149,851 US8244969B2 (en) 2007-05-30 2011-05-31 System including a fine-grained memory and a less-fine-grained memory
US13/528,064 US8667001B2 (en) 2008-03-20 2012-06-20 Scalable database management software on a cluster of nodes using a shared-distributed flash memory
US13/584,755 US8667212B2 (en) 2007-05-30 2012-08-13 System including a fine-grained memory and a less-fine-grained memory

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US94093407P 2007-05-30 2007-05-30
US60/940,934 2007-05-30
US3536208P 2008-03-10 2008-03-10
US61/035,362 2008-03-10
US3902708P 2008-03-24 2008-03-24
US3902008P 2008-03-24 2008-03-24
US61/039,027 2008-03-24
US61/039,020 2008-03-24
US4270008P 2008-04-04 2008-04-04
US61/042,700 2008-04-04

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/197,899 Continuation-In-Part US8732386B2 (en) 2008-03-20 2008-08-25 Sharing data fabric for coherent-distributed caching of multi-node shared-distributed flash memory

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/130,661 Continuation-In-Part US7975109B2 (en) 2007-05-30 2008-05-30 System including a fine-grained memory and a less-fine-grained memory
US12/130,661 Continuation US7975109B2 (en) 2007-05-30 2008-05-30 System including a fine-grained memory and a less-fine-grained memory

Publications (2)

Publication Number Publication Date
WO2008150927A2 WO2008150927A2 (en) 2008-12-11
WO2008150927A3 true WO2008150927A3 (en) 2009-03-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/065167 Ceased WO2008150927A2 (en) 2007-05-30 2008-05-29 System including a fine-grained memory and a less-fine-grained memory

Country Status (2)

Country Link
TW (1) TW200912643A (en)
WO (1) WO2008150927A2 (en)

Cited By (1)

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US8315081B2 (en) 2010-03-22 2012-11-20 Qualcomm Incorporated Memory cell that includes multiple non-volatile memories

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US8386747B2 (en) * 2009-06-11 2013-02-26 Freescale Semiconductor, Inc. Processor and method for dynamic and selective alteration of address translation
EP2317443A1 (en) 2009-10-29 2011-05-04 Incard SA Method for executing data updates in an IC Card
TWI497293B (en) 2009-12-17 2015-08-21 Ibm Data management in solid state storage devices
US8325543B2 (en) 2010-02-26 2012-12-04 International Business Machines Corporation Global bit select circuit interface with false write through blocking
US8325549B2 (en) 2010-02-26 2012-12-04 International Business Machines Corporation Global bit select circuit interface with simplified write bit line precharging
US9342453B2 (en) 2011-09-30 2016-05-17 Intel Corporation Memory channel that supports near memory and far memory access
CN103946812B (en) 2011-09-30 2017-06-09 英特尔公司 Apparatus and method for realizing multi-level memory hierarchy
EP2761480A4 (en) 2011-09-30 2015-06-24 Intel Corp Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
CN103946811B (en) 2011-09-30 2017-08-11 英特尔公司 Apparatus and method for implementing a multi-level memory hierarchy with different modes of operation
US8638595B2 (en) 2012-04-16 2014-01-28 International Business Machines Corporation Global bit select circuit with write around capability
WO2014120215A1 (en) 2013-01-31 2014-08-07 Hewlett-Packard Development Company, L.P. Adaptive granularity row-buffer cache
TWI566253B (en) * 2015-09-02 2017-01-11 慧榮科技股份有限公司 Method for managing a memory apparatus, and associated memory apparatus thereof and associated controller thereof
US10095622B2 (en) * 2015-12-29 2018-10-09 Intel Corporation System, method, and apparatuses for remote monitoring
TW201818248A (en) * 2016-11-15 2018-05-16 慧榮科技股份有限公司 Memory managing method for data storage device
US12130754B2 (en) * 2020-08-17 2024-10-29 Intel Corporation Adaptive routing for pooled and tiered data architectures
TWI774245B (en) * 2021-02-20 2022-08-11 瑞昱半導體股份有限公司 Linked list searching method and linked list searching device
US11947568B1 (en) * 2021-09-30 2024-04-02 Amazon Technologies, Inc. Working set ratio estimations of data items in a sliding time window for dynamically allocating computing resources for the data items
US12499054B2 (en) 2022-08-22 2025-12-16 Samsung Electronics Co., Ltd. Systems, methods, and apparatus for accessing data in versions of memory pages

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US5963983A (en) * 1996-04-15 1999-10-05 International Business Machines Corporation Method and apparatus for dynamically creating conversion tables to access a semiconductor memory device
EP1548600A1 (en) * 2003-12-26 2005-06-29 Samsung Electronics Co., Ltd. Data management device and method for flash memory
US20060174063A1 (en) * 2005-02-03 2006-08-03 Craig Soules Method of cooperative caching for distributed storage system
EP1746510A1 (en) * 2004-04-28 2007-01-24 Matsushita Electric Industrial Co., Ltd. Nonvolatile storage device and data write method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963983A (en) * 1996-04-15 1999-10-05 International Business Machines Corporation Method and apparatus for dynamically creating conversion tables to access a semiconductor memory device
EP1548600A1 (en) * 2003-12-26 2005-06-29 Samsung Electronics Co., Ltd. Data management device and method for flash memory
EP1746510A1 (en) * 2004-04-28 2007-01-24 Matsushita Electric Industrial Co., Ltd. Nonvolatile storage device and data write method
US20060174063A1 (en) * 2005-02-03 2006-08-03 Craig Soules Method of cooperative caching for distributed storage system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GOPAL S ET AL: "Speculative versioning cache", IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 12, no. 12, 1 December 2001 (2001-12-01), pages 1305 - 1317, XP011093967, ISSN: 1045-9219 *
MCDONALD A; JAEWOONG CHUNG; CARLSTROM B D; CHI CAO MINH; CHAFI H; KOZYRAKIS C; OLUKOTUN K: "Architectural semantics for practical transactional memory", ACM SIGARCH COMPUTER ARCHITECTURE NEWS, vol. 34, no. 2, June 2006 (2006-06-01), USA, pages 53 - 64, XP002497810, ISSN: 0163-5964 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8315081B2 (en) 2010-03-22 2012-11-20 Qualcomm Incorporated Memory cell that includes multiple non-volatile memories

Also Published As

Publication number Publication date
TW200912643A (en) 2009-03-16
WO2008150927A2 (en) 2008-12-11

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