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WO2008149987A1 - パターニング方法 - Google Patents

パターニング方法 Download PDF

Info

Publication number
WO2008149987A1
WO2008149987A1 PCT/JP2008/060480 JP2008060480W WO2008149987A1 WO 2008149987 A1 WO2008149987 A1 WO 2008149987A1 JP 2008060480 W JP2008060480 W JP 2008060480W WO 2008149987 A1 WO2008149987 A1 WO 2008149987A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
sacrifice
thin film
patterned
patterning method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/060480
Other languages
English (en)
French (fr)
Inventor
Pao-Hwa Chou
Kazuhide Hasebe
Shigeru Nakajima
Yasushi Akasaka
Mitsuaki Iwashita
Reiji Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to US12/441,741 priority Critical patent/US7754622B2/en
Priority to KR1020097005558A priority patent/KR101291766B1/ko
Publication of WO2008149987A1 publication Critical patent/WO2008149987A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
    • H10P50/695—
    • H10P50/696—
    • H10P50/71—
    • H10P76/4085—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

　開示されるパターニング方法においては、薄膜上に、この薄膜とは異なる膜からなり、かつ、ＳｉＢＮからなる犠牲膜を形成し、犠牲膜を、フォトリソグラフィ技術を用いて、所定の間隔を持つパターンに加工し、加工された犠牲膜の側壁上に、犠牲膜及び薄膜とは異なる膜からなる側壁スペーサを形成し、加工された犠牲膜を除去し、側壁スペーサをマスクに用いて、薄膜を加工する。
PCT/JP2008/060480 2007-06-07 2008-06-06 パターニング方法 Ceased WO2008149987A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/441,741 US7754622B2 (en) 2007-06-07 2008-06-06 Patterning method utilizing SiBN and photolithography
KR1020097005558A KR101291766B1 (ko) 2007-06-07 2008-06-06 패터닝 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-151065 2007-06-07
JP2007151065 2007-06-07

Publications (1)

Publication Number Publication Date
WO2008149987A1 true WO2008149987A1 (ja) 2008-12-11

Family

ID=40093791

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060480 Ceased WO2008149987A1 (ja) 2007-06-07 2008-06-06 パターニング方法

Country Status (5)

Country Link
US (1) US7754622B2 (ja)
JP (1) JP4589983B2 (ja)
KR (1) KR101291766B1 (ja)
TW (1) TWI376745B (ja)
WO (1) WO2008149987A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010219106A (ja) * 2009-03-13 2010-09-30 Tokyo Electron Ltd 基板処理方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040561A (ja) * 2009-08-11 2011-02-24 Tokyo Electron Ltd 半導体装置の製造方法。
US8343881B2 (en) 2010-06-04 2013-01-01 Applied Materials, Inc. Silicon dioxide layer deposited with BDEAS
CN102064096B (zh) * 2010-12-03 2012-07-25 北京大学 一种细线条的制备方法
US8633077B2 (en) 2012-02-15 2014-01-21 International Business Machines Corporation Transistors with uniaxial stress channels
CN103632928A (zh) * 2012-08-29 2014-03-12 中芯国际集成电路制造(上海)有限公司 自对准双重图形的形成方法
CN104078417A (zh) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 自对准双构图方法及nand闪存的金属互连结构
US9263282B2 (en) * 2013-06-13 2016-02-16 United Microelectronics Corporation Method of fabricating semiconductor patterns
JP6607827B2 (ja) * 2016-06-14 2019-11-20 東京エレクトロン株式会社 基板処理方法及び硼素添加珪素の除去方法
WO2019066898A1 (en) * 2017-09-29 2019-04-04 Intel Corporation SELF-ALIGNED INTEGRATED PHASE CHANGE MEMORY CELL

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126637A (ja) * 1985-11-18 1987-06-08 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション 開孔の形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950013789B1 (ko) * 1992-12-02 1995-11-16 현대전자산업주식회사 반도체 소자의 미세 게이트 전극 형성 방법
JP2000173979A (ja) 1998-12-07 2000-06-23 Sanyo Electric Co Ltd エッチングマスク及び微細パターンの形成方法
US20080145536A1 (en) * 2006-12-13 2008-06-19 Applied Materials, Inc. METHOD AND APPARATUS FOR LOW TEMPERATURE AND LOW K SiBN DEPOSITION
KR100843236B1 (ko) * 2007-02-06 2008-07-03 삼성전자주식회사 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126637A (ja) * 1985-11-18 1987-06-08 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション 開孔の形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010219106A (ja) * 2009-03-13 2010-09-30 Tokyo Electron Ltd 基板処理方法

Also Published As

Publication number Publication date
JP4589983B2 (ja) 2010-12-01
KR20090057023A (ko) 2009-06-03
TWI376745B (en) 2012-11-11
JP2009016813A (ja) 2009-01-22
US7754622B2 (en) 2010-07-13
US20100112796A1 (en) 2010-05-06
KR101291766B1 (ko) 2013-08-01
TW200915418A (en) 2009-04-01

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