WO2008149487A1 - Soiウェーハのシリコン酸化膜形成方法 - Google Patents
Soiウェーハのシリコン酸化膜形成方法 Download PDFInfo
- Publication number
- WO2008149487A1 WO2008149487A1 PCT/JP2008/001101 JP2008001101W WO2008149487A1 WO 2008149487 A1 WO2008149487 A1 WO 2008149487A1 JP 2008001101 W JP2008001101 W JP 2008001101W WO 2008149487 A1 WO2008149487 A1 WO 2008149487A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- oxide film
- soi wafer
- silicon oxide
- thermal oxidation
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200880014803A CN101730925A (zh) | 2007-05-29 | 2008-04-25 | Soi晶片的硅氧化膜形成方法 |
| US12/450,955 US8053334B2 (en) | 2007-05-29 | 2008-04-25 | Method for forming silicon oxide film of SOI wafer |
| KR1020097024708A KR101488667B1 (ko) | 2007-05-29 | 2008-04-25 | Soi 웨이퍼의 실리콘 산화막 형성 방법 |
| EP08751626.6A EP2151851B1 (en) | 2007-05-29 | 2008-04-25 | Method for forming silicon oxide film of soi wafer |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007142338A JP5183969B2 (ja) | 2007-05-29 | 2007-05-29 | Soiウェーハのシリコン酸化膜形成方法 |
| JP2007-142338 | 2007-05-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008149487A1 true WO2008149487A1 (ja) | 2008-12-11 |
Family
ID=40093321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2008/001101 Ceased WO2008149487A1 (ja) | 2007-05-29 | 2008-04-25 | Soiウェーハのシリコン酸化膜形成方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8053334B2 (ja) |
| EP (1) | EP2151851B1 (ja) |
| JP (1) | JP5183969B2 (ja) |
| KR (1) | KR101488667B1 (ja) |
| CN (1) | CN101730925A (ja) |
| TW (1) | TWI474397B (ja) |
| WO (1) | WO2008149487A1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014114029A1 (zh) * | 2013-01-23 | 2014-07-31 | 中国科学院上海微系统与信息技术研究所 | 基于增强吸附来制备绝缘体上材料的方法 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103329247B (zh) * | 2011-01-25 | 2018-07-31 | Ev 集团 E·索尔纳有限责任公司 | 用于永久接合晶片的方法 |
| JP2014516470A (ja) | 2011-04-08 | 2014-07-10 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ウェハを恒久的にボンディングするための方法 |
| JP5927894B2 (ja) * | 2011-12-15 | 2016-06-01 | 信越半導体株式会社 | Soiウェーハの製造方法 |
| US8927334B2 (en) | 2012-09-25 | 2015-01-06 | International Business Machines Corporation | Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package |
| JP5780234B2 (ja) | 2012-12-14 | 2015-09-16 | 信越半導体株式会社 | Soiウェーハの製造方法 |
| US9064971B2 (en) * | 2012-12-20 | 2015-06-23 | Intel Corporation | Methods of forming ultra thin package structures including low temperature solder and structures formed therby |
| FR3003684B1 (fr) * | 2013-03-25 | 2015-03-27 | Soitec Silicon On Insulator | Procede de dissolution d'une couche de dioxyde de silicium. |
| JP2016201454A (ja) * | 2015-04-09 | 2016-12-01 | 信越半導体株式会社 | Soiウェーハの製造方法 |
| JP6515757B2 (ja) * | 2015-09-15 | 2019-05-22 | 信越化学工業株式会社 | SiC複合基板の製造方法 |
| JP6531743B2 (ja) * | 2016-09-27 | 2019-06-19 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
| WO2020149046A1 (ja) * | 2019-01-16 | 2020-07-23 | 株式会社村田製作所 | キャビティを有するシリコン基板及び該シリコン基板を用いたキャビティsoi基板 |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS634624A (ja) * | 1986-06-25 | 1988-01-09 | Sony Corp | 半導体装置の製造方法 |
| JPS6433935A (en) * | 1987-07-29 | 1989-02-03 | Seiko Instr & Electronics | Formation of silicon oxide film |
| JPH02248045A (ja) * | 1989-03-22 | 1990-10-03 | Nec Corp | SiO↓2膜の形成方法 |
| JPH05226620A (ja) * | 1992-02-18 | 1993-09-03 | Fujitsu Ltd | 半導体基板及びその製造方法 |
| JPH0680624B2 (ja) | 1990-02-28 | 1994-10-12 | 信越半導体株式会社 | 接合ウエーハの製造方法 |
| JPH07153835A (ja) * | 1993-11-26 | 1995-06-16 | Nippondenso Co Ltd | 接合式soi半導体装置及びその製造方法 |
| JPH08222715A (ja) * | 1995-02-16 | 1996-08-30 | Komatsu Electron Metals Co Ltd | 貼り合わせsoi基板の製造方法 |
| JPH1074922A (ja) * | 1996-07-05 | 1998-03-17 | Nippon Telegr & Teleph Corp <Ntt> | Soi基板の製造方法 |
| JPH11345954A (ja) | 1998-05-29 | 1999-12-14 | Shin Etsu Handotai Co Ltd | 半導体基板及びその製造方法 |
| JP2007073768A (ja) | 2005-09-07 | 2007-03-22 | Shin Etsu Handotai Co Ltd | 貼り合わせsoiウェーハの製造方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69126153T2 (de) | 1990-02-28 | 1998-01-08 | Shinetsu Handotai Kk | Verfahren zur Herstellung von verbundenen Halbleiterplättchen |
| US5989981A (en) | 1996-07-05 | 1999-11-23 | Nippon Telegraph And Telephone Corporation | Method of manufacturing SOI substrate |
| JP4285244B2 (ja) | 2004-01-08 | 2009-06-24 | 株式会社Sumco | Soiウェーハの作製方法 |
| JP2006216826A (ja) * | 2005-02-04 | 2006-08-17 | Sumco Corp | Soiウェーハの製造方法 |
| JP4427489B2 (ja) * | 2005-06-13 | 2010-03-10 | 株式会社東芝 | 半導体装置の製造方法 |
-
2007
- 2007-05-29 JP JP2007142338A patent/JP5183969B2/ja active Active
-
2008
- 2008-04-25 US US12/450,955 patent/US8053334B2/en active Active
- 2008-04-25 KR KR1020097024708A patent/KR101488667B1/ko active Active
- 2008-04-25 WO PCT/JP2008/001101 patent/WO2008149487A1/ja not_active Ceased
- 2008-04-25 CN CN200880014803A patent/CN101730925A/zh active Pending
- 2008-04-25 EP EP08751626.6A patent/EP2151851B1/en active Active
- 2008-04-29 TW TW97115752A patent/TWI474397B/zh active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS634624A (ja) * | 1986-06-25 | 1988-01-09 | Sony Corp | 半導体装置の製造方法 |
| JPS6433935A (en) * | 1987-07-29 | 1989-02-03 | Seiko Instr & Electronics | Formation of silicon oxide film |
| JPH02248045A (ja) * | 1989-03-22 | 1990-10-03 | Nec Corp | SiO↓2膜の形成方法 |
| JPH0680624B2 (ja) | 1990-02-28 | 1994-10-12 | 信越半導体株式会社 | 接合ウエーハの製造方法 |
| JPH05226620A (ja) * | 1992-02-18 | 1993-09-03 | Fujitsu Ltd | 半導体基板及びその製造方法 |
| JPH07153835A (ja) * | 1993-11-26 | 1995-06-16 | Nippondenso Co Ltd | 接合式soi半導体装置及びその製造方法 |
| JPH08222715A (ja) * | 1995-02-16 | 1996-08-30 | Komatsu Electron Metals Co Ltd | 貼り合わせsoi基板の製造方法 |
| JPH1074922A (ja) * | 1996-07-05 | 1998-03-17 | Nippon Telegr & Teleph Corp <Ntt> | Soi基板の製造方法 |
| JPH11345954A (ja) | 1998-05-29 | 1999-12-14 | Shin Etsu Handotai Co Ltd | 半導体基板及びその製造方法 |
| JP2007073768A (ja) | 2005-09-07 | 2007-03-22 | Shin Etsu Handotai Co Ltd | 貼り合わせsoiウェーハの製造方法 |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP2151851A4 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014114029A1 (zh) * | 2013-01-23 | 2014-07-31 | 中国科学院上海微系统与信息技术研究所 | 基于增强吸附来制备绝缘体上材料的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5183969B2 (ja) | 2013-04-17 |
| US20100112824A1 (en) | 2010-05-06 |
| CN101730925A (zh) | 2010-06-09 |
| TW200903640A (en) | 2009-01-16 |
| KR101488667B1 (ko) | 2015-02-02 |
| EP2151851A1 (en) | 2010-02-10 |
| US8053334B2 (en) | 2011-11-08 |
| JP2008300435A (ja) | 2008-12-11 |
| EP2151851A4 (en) | 2010-06-30 |
| EP2151851B1 (en) | 2016-11-23 |
| KR20100017407A (ko) | 2010-02-16 |
| TWI474397B (zh) | 2015-02-21 |
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