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WO2008144408A1 - Consommation de puissance réduite dans un convertisseur analogique-numérique - Google Patents

Consommation de puissance réduite dans un convertisseur analogique-numérique Download PDF

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Publication number
WO2008144408A1
WO2008144408A1 PCT/US2008/063729 US2008063729W WO2008144408A1 WO 2008144408 A1 WO2008144408 A1 WO 2008144408A1 US 2008063729 W US2008063729 W US 2008063729W WO 2008144408 A1 WO2008144408 A1 WO 2008144408A1
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WIPO (PCT)
Prior art keywords
clock
sample
stage
adc
hold
Prior art date
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Ceased
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PCT/US2008/063729
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English (en)
Inventor
Jomy G. Joy
Ankit Seedher
Ayaskant Shrivastava
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Texas Instruments Inc
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Texas Instruments Inc
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution

Definitions

  • the invention relates generally to the design of analog-to-digital converters (ADC), and more specifically to a technique for reducing power consumption in the early stages of a pipelined sub-ADC in a time-interleaved ADC.
  • ADC analog-to-digital converters
  • An analog-to-digital converter is generally used to sample an analog signal at various time instances, and generate a digital code representing the strength (of voltage or current) of the sampled analog signal at the corresponding time instance.
  • Time interleaved ADC is a type of ADC in which multiple individual ADCs (conveniently hereafter referred to as sub-ADCs) are operated in parallel, with each sub- ADC sampling a corresponding successive sample of the analog input signal in a time- interleaved fashion. The samples generated by the sub-ADCs are then multiplexed into a single stream to represent the output codes generated by the interleaved ADC. Due to such an operation, each sub-ADC may be designed for lower sampling rates, while the time interleaved ADC provides high overall sampling rates.
  • sub-ADCs multiple individual ADCs
  • each sub-ADC sampling a corresponding successive sample of the analog input signal in a time- interleaved fashion.
  • the samples generated by the sub-ADCs are then multiplexed into a single stream to represent the output codes generated by the interleaved ADC. Due to such an operation, each sub-ADC may be designed for lower sampling rates, while the time interleave
  • Pipelined ADCs are often used to implement sub-ADCs in a time-interleaved ADC.
  • a pipelined ADC is a type of ADC which contains a sequence of (pipelined) stages, with each stage resolving a number of bits forming a sub-code.
  • the sub-codes generated by various stages are used to generate a digital code corresponding to the analog input sampled by the corresponding sub- ADC.
  • Each stage (except the last stage) of a pipelined ADC generates a residue signal representing that portion of the input signal that needs to be resolved by subsequent stages.
  • the residue signal represents a difference of the voltage of the input signal to the stage and the voltage level corresponding to the sub-code provided by the stage.
  • the residue signal (in an amplified form, typically) of one stage is provided as an input signal to the next stage in the sequence.
  • the first stage represents an early stage (since the sample is processed first by the first stage) in the sequence.
  • FIG. 1 is a block diagram of a time-interleaved ADC in an embodiment.
  • FIG. 2 is a block diagram illustrating the details of a pipelined sub-ADC used in a time-interleaved ADC in an embodiment.
  • FIG. 3 is a block diagram illustrating the internal details of a stage of a pipelined sub- ADC in an embodiment.
  • FIG. 4 is a circuit diagram of a portion of a pipelined sub-ADC implemented according to a charge redistribution technique in an embodiment.
  • FIG. 5 is a prior timing diagram illustrating the time relationship between the operations of an input sample and hold amplifier and sample and hold phases of pipelined sub- ADCs used in a time interleaved ADC.
  • FIG. 6 is a flowchart illustrating the manner in which power consumption may be reduced in an amplifier used in an early stage of a pipelined sub-ADC used in a time- interleaved ADC according to several aspects of the invention.
  • FIG. 7 is a timing diagram illustrating the time relationship between the operations of an input sample and hold amplifier and the sample and hold phases of pipelined sub-ADC in an embodiment of the invention.
  • FIG. 8 is a block diagram of an example system in which various aspects of the invention may be implemented.
  • a stage of a pipelined ADC used as a sub- ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals.
  • the first set of clock signals and the second set of clock signals are designed to cause hold phases of the stage to commence earlier than sampling phases of the next stage.
  • the stage corresponds to an earliest stage in the pipelined sub- ADC.
  • FIG. 1 is a block diagram of a time interleaved ADC in an embodiment.
  • Time interleaved ADC 100 is shown containing input sample and hold amplifier (input SHA) 120, sub-ADCs 110-1 through HO-N, switches 150-1 through 150-N, and clock generator 180. Each component is described below.
  • Clock generator 180 generates various clock signals used for determining (controlling) sample and hold phases (operations) of the components/units in time interleaved ADC 100.
  • Clock generator 180 generates clock 140 to input SHA 120, and multiple clocks on path 181 to control sample and hold operations for internal stages/units in sub-ADCs 110-1 through HO-N as well as for controlling opening/closing of switches 150-1 through 150-N (though connections are not shown in the FIG.).
  • Input SHA 120 receives an analog input on path 130, and in response to clock 140
  • Input SHA 120 provides the captured samples on path 125.
  • Input SHA 120 represents an example of a sample and hold unit. Other techniques, potentially without amplification, may be used in place of input SHA 120.
  • Each of switches 150-1 through 150-N operates to provide a corresponding sample
  • Switches 150-1 through 150-N may be controlled by clock signals generated by clock generator 180 and contained in path 181.
  • Each of sub-ADCs 110-1 through 110-N receives a corresponding sample of the analog input (130) in a corresponding time interval, and operates to provide a digital code corresponding to the strength (voltage/current) of the sample.
  • the samples generated by the sub-ADCs may then be multiplexed into a single stream (not shown) to represent the digital codes generated by time interleaved ADC 100.
  • Various clocks used to specify sample/hold intervals or operations for internal stages/units in each of the sub-ADCs are provided on path 181 by clock generator 180.
  • Each of sub-ADCs 110-1 through 110-N may be implemented as a pipelined ADC, the internal details of which are described next. 3. Pipelined Sub-ADC
  • FIG. 2 is a block diagram illustrating the details of sub- ADC 110-1 implemented as a pipelined ADC in an embodiment.
  • Sub- ADC 110-1 is shown containing sample and hold amplifier (SHA) 210, and stages 220-1 through 220-S and digital error correction block 230. Each block is described below in further detail.
  • SHA sample and hold amplifier
  • SHA 210 samples the input signal received on path 151-1, and holds the voltage level of the sample for further processing.
  • Each stage 220-1 through 220-S generates a sub-code corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage.
  • stage 220-1 converts a voltage level on path 211 to generate a sub-code on path 223-1, and the amplified residue signal generated on path 212 is provided as an input to stage 220-2.
  • Digital error correction block 230 receives sub-codes from various stages, and generates a digital code corresponding to the sample received on path 151-1. Essentially, it performs a weighted addition of the sub-codes to generate the overall code, as is well known in the relevant arts. The generated digital code is provided on path 246.
  • FIG. 3 further illustrates the components contained in each stage (described with reference to stage 220- 1 only, for conciseness) in an embodiment.
  • Stage 220- 1 is shown containing flash ADC350, digital to analog converter (DAC) 360, subtractor 370 and gain amplifier 380.
  • Flash ADC 350 converts a sample of an analog signal received on path 211 into a corresponding P-bit sub-code provided on path 356 (contained in path 223-1 of FIG. 2, and P is less than N, wherein N is the number of bits of the overall digital output code provided on path 246 by sub- ADC 110-1).
  • DAC 360 converts the sub-code received on path 356 into corresponding analog signal (Vdac) on path 367.
  • Subtractor 370 generates a residue signal as the difference of sample 211 (Vin) and the analog signal received on path 367 (Vdac).
  • Gain amplifier 380 amplifies the residue signal (Vin-Vdac) and is provided on path 212 as an amplified residue signal.
  • the signal on path 212 is used to resolve the remaining bits in the N-bit digital code by the subsequent stages.
  • Subtractor 370, DAC 360, and gain amplifier 380 may be implemented using a capacitor network and an operational amplifier according to one of several techniques such as charge redistribution stage, flip-around charge redistribution stage etc. An embodiment implemented as a charge redistribution stage is described next. 4. Switched-Capacitor Network and Amplifier Used in a Stage
  • FIG. 4 is a circuit diagram illustrating the manner in which subtractor 370, DAC 360, and gain amplifier 380 of stage 220-1 are implemented in an embodiment that uses a
  • subtractor 370 DAC 360, and gain amplifier 380 can also be implemented according to other techniques such as a flip-around charge redistribution technique.
  • Subtractor 370, DAC 360, and gain amplifier 380 are shown implemented using operational amplifier 450, sampling capacitors 431-434, feedback capacitors 461 and 462, sampling switches 421D, 422D, 423D and 424D, DAC switches 421 A-C, 422A-C, 423A-C and 424A-C, common mode switches 451 and 452 , reset switches 481 and 482 , and feedback switches 471 and 472.
  • Sampling switches 421D, 422D, 423D and 424D, reset switches 481 and 482, and common mode switches 451 and 452 make contact (closed) during sample phase (interval). The remaining switches are in break state (open) during the sample phase.
  • sampling capacitors 431-434 are connected to input signal Vin (i.e., signal on path 211 of FIGS. 2 and 3), and amplifier inputs 455 and 456 are connected to common mode input Vicm.
  • One end of capacitors 461 and 462 is connected to common mode input Vicm while the other end is connected to another common mode input Vocm.
  • Vicm and Vocm are set to ensure proper operation of the operational amplifier 450.
  • input signal is sampled across the sampling capacitors 431-434, while the charge stored on capacitors 461 and 462 (due to previous phase) is reset.
  • feedback switches 471 and 472 operate to connect feedback capacitors 461 and 462 to inputs of operational amplifier 455 and 456 respectively.
  • Switches 421 A-C operate to connect capacitor 431 to one of Vrefp, Vrefm and Vcm terminal depending on sub code generated by flash ADC 350.
  • the component values can be adjusted to get a voltage gain required in gain amplifier 380, as well as any subtractive/additive operations to implement DAC 360 and subtractor 370. This, as well as detailed operation of the circuit of FIG. 4, will not be described in detail, as being well known to one skilled in the relevant arts.
  • FIG. 5 is a prior timing diagram illustrating the time relationship between the operations of an input SHA and the sample and hold phases of (pipelined) sub- ADCs used in a time interleaved ADC.
  • the timing diagram is described/shown with respect to the embodiment of FIG. 1.
  • the timing diagram is shown assuming only two pipelined sub-ADCs (for example, sub-ADC 110-1 and sub-ADC 110-2) are used in time interleaved ADC 100. Further, only a few representative cycles of the various waveforms are shown in the interest of conciseness. The description below is provided with combined reference to FIGS. 2, 3, 4 and 5.
  • each of waveforms 510, 520, 530, 540, 550 and 560 is generated by clock generator 180 and provided on path 181 to respective component.
  • Waveform 140 represents clock 140 provided to input SHA 120.
  • Time intervals T2, T4, T6, T8 and TlO represent sample phases (marked S2, S3, S4, S5 and S6 in FIG. 5) in input SHA 120, i.e., time intervals during which the input analog signal 130 is sampled onto sampling capacitors(not shown, but contained internally) in input SHA 120.
  • Time intervals Tl, T3, T5, T7, T9 and Tl l represent hold phases (marked Hl, H2, H3, H4, H5 and H6) in input SHA 120, i.e. time intervals during which the sampled input (analog signal 130) is transferred from the internal sample capacitors (not shown) to hold capacitors (not shown) in input SHA 120.
  • a hold interval represents an interval of time during which the 'sampled' signal is transferred to the 'hold' capacitors.
  • Waveform 510 represents a clock provided to enable sampling in the first stage ( 220- 1 of FIG. 2) of pipelined sub-ADC 110-1. As noted with respect to FIG. 4, sampling switches 421D, 422D, 423D and 424D, reset switches 481 and 482, and common mode switches 451 and 452 are closed during a sample phase.
  • Logic high of waveform 510 during time intervals Tl, T5 and T9 represent sample intervals (marked SI l, S12, and S13 in FIG. 5), and causes the switches noted above to be closed for the corresponding interval.
  • Waveform 520 represents a clock provided to enable hold phases in the first stage (220-1) as well as (simultaneously) sample phases in stage 220-2 of sub-ADC 110-1.
  • logic high of waveform 520 enables a hold phase in stage 220-1 and a sample phase in stage 220-2 (marked Hl 1/S21 in FIG. 5).
  • the combined time interval T7+T8 represents a next hold (sample) phases in stage 220-1 (220-2), and is marked H12/S22 in FIG. 5.
  • Waveform 530 represents a clock signal enabling hold phases in stage 220-2 and sample phases in stage 220-3 in sub- ADC 110-1.
  • Waveform 540 represents a clock provided to enable sampling in the first stage (not shown in the FIGS., but contained internally) of pipelined sub-ADC 110-2. It may be seen that the first stages of sub- ADC 110-1 and sub- ADC 110-2 sample the analog input during alternate hold phases of input SHA 120 in a time-interleaved manner.
  • Waveform 550 represents a clock provided to enable hold phases in the first stage as well as (simultaneously) sample phases in the second stage of sub-ADC 110-2.
  • Waveform 560 represents a clock signal enabling hold phases in stage 2 and sample phases in stage 3 of sub-ADC 110-2.
  • stage 220-2 begins sampling phase S21 at start of time interval T3 and ends sampling at end of time interval T4.
  • the output 212 of the previous stage (220-1) should reach its final value at least by end of T4.
  • stage 220-1 also occurs in the same time interval T3/T4.
  • operational amplifier 450 (which may have to drive both a self-capacitance and routing parasitic as well as the load presented by stage 220-2) must ensure that the output reaches its final value (settle to within an acceptable accuracy) by end of time interval T4.
  • a hold phase of a stage operate sufficiently fast to make available a correct output for a next stage.
  • amplifiers used in the first stage are often implemented as high-speed amplifiers.
  • ADC 110-1 may be implemented as a high-speed (high bandwidth) amplifier to provide the fast output settling time noted above. This may lead to high power dissipation in operational amplifier 450, and, in general, higher power consumption in time interleaved ADC 100.
  • An aspect of the invention reduces such power dissipation as described below.
  • FIG. 6 is a flowchart illustrating the manner in which power consumption may be reduced in an amplifier used in an early stage of a pipelined sub-ADC used in a time- interleaved ADC according to several aspects of the invention.
  • the flowchart is described with respect to FIGS. 1-4 (as well as in comparison to FIG. 5), and in particular with respect to reducing power consumption in operational amplifier 450 of stage 220-1 of sub- ADC 110- 1.
  • At least some of the techniques described below also apply to amplifiers in other stages such as 220-2 through 220-S, as well as one or more stages of sub-ADCs 110-2 through 110-N.
  • the steps are described in a specific sequence merely for illustration.
  • step 601 The flowchart starts in step 601, in which control passes immediately to step 610.
  • step 610 clock generator 180 determines a phase instance tl of operation of an input sample and hold stage (input SHA 120) of time interleaved ADC 100 coinciding with an end of a corresponding sample phase of a stage of a sub- ADC in a time interleaved ADC.
  • clock generator 180 determines the end of time interval Tl corresponding to end of sampling phase Sl 1 of stage 220-1. Control then passes to step 630.
  • clock generator 180 determines a phase instance t2 of operation of input SHA 120 coinciding with the beginning of a corresponding sample phase (i.e., in which the same sample received from input SHA 120 is processed) of a next stage of the sub-ADC.
  • clock generator 180 determines the end of time interval T2 corresponding to the beginning of sampling phase S 12 of stage 220-1.
  • step 640 clock generator 180 begins a hold phase of the stage coinciding with time instance t3 occurring at or later than time instance tl and earlier than time instance t2.
  • clock generator begins a hold phase of stage 220-1 at a time instance earlier than t2 but at or later than tl.
  • step 699 A timing diagram illustrating the steps described above in an example scenario is shown in FIG. 7, and is briefly described next.
  • FIG. 7 is a timing diagram illustrating the time relationship between the operations of input SHA 120 and the sample and hold phases of pipelined sub-ADCs 110-1 and 110-2 in an embodiment of the invention. Again, for ease of description, it is assumed that time- interleaved ADC 100 contains only sub-ADCs 110-1 and 110-2. It is also assumed that positive going (active) edges of the respective signals specify the start of a corresponding operation (sample or hold phase), and negative going (inactive) edges specify end of the corresponding operation.
  • Waveform 710 represents a sample clock used to control sample operations (sample phases) of stage 220-1 of sub-ADC 110-1.
  • Waveform 720 represents a hold clock used to control hold operations (hold phases) of stage 220-1 of sub- ADC 110-1.
  • Waveform 730 represents a sample clock used to control sample operations (sample phases) of stage 220-2 of sub-ADC 110-1.
  • Waveform 740 represents a hold clock used to control hold operations (hold phases) of stage 220-2 of sub-ADC 110-1. Waveform 740 may also be used to control sample operations in stage 220-3 of sub ADC-110-1.
  • Waveform 750 represents a sample clock used to control sample operations (sample phases) of the first stage (not shown) of sub-ADC 110-2.
  • Waveform 760 represents a hold clock used to control hold operations (hold phases) of the first stage of sub- ADC 110-2.
  • Waveform 770 represents a sample clock used to control sample operations (sample phases) of the second stage (not shown) of sub-ADC 110-2.
  • Waveform 780 represents a hold clock used to control hold operations (hold phases) of the second stage of sub-ADC 110-2.
  • Waveform 780 may also be used to control sample operations of the third stage (not shown) of sub ADC-110-2.
  • Waveforms 710, 720, 730, 740, 750, 760, 770 and 780 may be generated by clock generator 180 in a known way.
  • active edges of hold clock 720 occur earlier than active edges of sample clock 730.
  • active edges of hold clock 720 are shown coinciding with inactive edges of sample clock 710.
  • a similar relationship also holds with respect to waveforms 750 and 760.
  • more time is provided for output 212 of operation amplifier 450 of stage 220-1 of sub-ADC 110-1 to settle to its final value.
  • the sample interval of stage 220-2 sampling is not concurrent (does not overlap) with the hold phase of stage 220-1 for the time interval T2 (also equal to T4, T6 etc.). Instead, hold phases (e.g.
  • stage 220-1 HI l, H12 etc.
  • sample phases S21, S22 etc.
  • large signal slewing to drive self-capacitance of operation amplifier 450 and routing parasitic (which in combination may be a significant fraction of the total load presented to operational amplifier 450) can happen in the interval T2 (when 220-2 is not yet sampling), and only small signal linear settling (due to load presented by stage 220-2) needs to occur once stage 220-2 starts sampling.
  • operational amplifier 450 (as well as the first stage amplifier of sub- ADC 110-2) may be implemented as a (comparatively) lower speed (lower bandwidth) amplifiers consuming lesser power.
  • amplifiers in earlier stages of pipelined sub-ADCs in time-interleaved ADC 100 may be implemented as low-speed devices to reduce overall power consumption.
  • Time-interleaved ADC 110 implemented according to one or more aspects of the invention may be incorporated in a system as described next.
  • System FIG. 8 is a block diagram of receiver system 800 illustrating an example system in which various aspects of the invention may be implemented. For illustration, it is assumed that receiver system 800 is implemented within a Wireless Receiver. However, receiver system 800 can be implemented in other devices (wireless as well as wire-based communications) as well. Receiver system 800 is shown containing low noise amplifiers (LNA) 810, mixer
  • processor 820 filter circuit 860, analog-to-digital converter (ADC) 870, and processor 880. Each block/stage is described below in further detail.
  • ADC analog-to-digital converter
  • LNA 810 receives signals on path 801 and amplifies the received signals to generate a corresponding amplified signal on path 812. For example, in wireless systems the signals that are transmitted from satellites, etc. may be received by an antenna (not shown) and the received signals are provided on path 801. The received signals may be weak in strength and thus amplified by LNA 810 for further processing. LNA 810 may be implemented in a known way.
  • Mixer 820 may be used to down-convert the received amplified signal on path 812 into an intermediate signal with the frequency band of interest centered at a lower frequency than the carrier frequency of the received signal.
  • a signal with the frequency band of interest centered at 2.4 GHz (carrier frequency) is converted to a signal with the frequency band of interest centered at zero frequency.
  • Mixer 820 may receive the amplified signal on path 812 and a signal of fixed frequency on path 822 as inputs, and provides the intermediate signal on path 826.
  • the signal of fixed frequency on path 822 may be generated by a phase locked loop (not shown) in a known way.
  • Filter circuit 860 may correspond to a low pass filter, which allows the desired low frequencies and rejects all other unwanted high frequencies present in the signal received on line 826.
  • the filtered signal which contains the frequency band of interest, is provided on path 867.
  • ADC 870 converts (samples) the filtered signal received on path 867 to a corresponding digital value, which represents the signal of interest in received signal 801.
  • Processor 880 processes the received digital values to provide various user applications and may be implemented as multiple processing units, each potentially operating independently.
  • ADC 870 may correspond to ADC 100 (FIG. 1) described in sections above (and implemented according to various aspects of the invention).

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un étage d'un CAN à chevauchement (100) utilisé comme sous-CAN dans un CAN à entrelacement temporel qui est actionné en utilisant un premier ensemble de signaux d'horloge, un étage suivant étant actionné en utilisant un second ensemble de signaux d'horloge. Le premier ensemble et le second ensemble de signaux d'horloge sont conçus pour provoquer le démarrage de phase de blocage de l'étage plus tôt que les phases d'échantillonnage de l'étage suivant. Dans un mode de réalisation, le démarrage des phases de blocage coïncide avec la fin d'une phase d'échantillonnage immédiatement précédente de l'étage. Ainsi, davantage de temps est fourni pour la sortie d'un amplificateur utilisé dans l'étage pour régler une valeur finale, permettant l'utilisation d'un amplificateur à faible vitesse et une réduction de la consommation de puissance dans le CAN entrelacé. Dans un mode de réalisation, l'étage correspond à un étage antérieur dans le sous-CAN à chevauchement.
PCT/US2008/063729 2007-05-15 2008-05-15 Consommation de puissance réduite dans un convertisseur analogique-numérique Ceased WO2008144408A1 (fr)

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US11/748,495 US7551114B2 (en) 2007-05-15 2007-05-15 Reducing power consumption in the early stages of a pipeline sub-ADC used in a time-interleaved ADC

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