[go: up one dir, main page]

WO2008036484A3 - Nonvolatile memory with reduced coupling between floating gates - Google Patents

Nonvolatile memory with reduced coupling between floating gates Download PDF

Info

Publication number
WO2008036484A3
WO2008036484A3 PCT/US2007/076163 US2007076163W WO2008036484A3 WO 2008036484 A3 WO2008036484 A3 WO 2008036484A3 US 2007076163 W US2007076163 W US 2007076163W WO 2008036484 A3 WO2008036484 A3 WO 2008036484A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gates
nonvolatile memory
reduced coupling
inverted
floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/076163
Other languages
French (fr)
Other versions
WO2008036484A2 (en
Inventor
Henry Chien
George Matamis
Tuan Pham
Masaaki Higashitani
Hidetaka Horiuchi
Jeffrey W Lutze
Nima Mokhlesi
Yupin Kawing Fong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/534,139 external-priority patent/US20080074920A1/en
Priority claimed from US11/534,135 external-priority patent/US7615445B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of WO2008036484A2 publication Critical patent/WO2008036484A2/en
Publication of WO2008036484A3 publication Critical patent/WO2008036484A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
PCT/US2007/076163 2006-09-21 2007-08-17 Nonvolatile memory with reduced coupling between floating gates Ceased WO2008036484A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/534,135 2006-09-21
US11/534,139 US20080074920A1 (en) 2006-09-21 2006-09-21 Nonvolatile Memory with Reduced Coupling Between Floating Gates
US11/534,135 US7615445B2 (en) 2006-09-21 2006-09-21 Methods of reducing coupling between floating gates in nonvolatile memory
US11/534,139 2006-09-21

Publications (2)

Publication Number Publication Date
WO2008036484A2 WO2008036484A2 (en) 2008-03-27
WO2008036484A3 true WO2008036484A3 (en) 2008-08-07

Family

ID=39166676

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/076163 Ceased WO2008036484A2 (en) 2006-09-21 2007-08-17 Nonvolatile memory with reduced coupling between floating gates

Country Status (2)

Country Link
TW (1) TWI359499B (en)
WO (1) WO2008036484A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8429574B2 (en) * 2011-04-14 2013-04-23 Cadence Design Systems, Inc. Dual-pattern coloring technique for mask design

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617632A1 (en) * 1995-12-26 1997-07-03 Lg Semicon Co Ltd Non-volatile memory cell device, e.g. ROM cell
WO2005001922A1 (en) * 2003-06-20 2005-01-06 Sandisk Corporation Floating gate structures with vertical projections
US20050087795A1 (en) * 2003-09-22 2005-04-28 Makoto Sakuma Nonvolatile semiconductor memory device
US20050199939A1 (en) * 2004-03-12 2005-09-15 Lutze Jeffrey W. Self aligned non-volatile memory cells and processes for fabrication
US20050212034A1 (en) * 2004-03-24 2005-09-29 Renesas Technology Corp. Nonvolatile semiconductor memory device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617632A1 (en) * 1995-12-26 1997-07-03 Lg Semicon Co Ltd Non-volatile memory cell device, e.g. ROM cell
WO2005001922A1 (en) * 2003-06-20 2005-01-06 Sandisk Corporation Floating gate structures with vertical projections
US20050087795A1 (en) * 2003-09-22 2005-04-28 Makoto Sakuma Nonvolatile semiconductor memory device
US20050199939A1 (en) * 2004-03-12 2005-09-15 Lutze Jeffrey W. Self aligned non-volatile memory cells and processes for fabrication
US20050212034A1 (en) * 2004-03-24 2005-09-29 Renesas Technology Corp. Nonvolatile semiconductor memory device and manufacturing method thereof

Also Published As

Publication number Publication date
TWI359499B (en) 2012-03-01
TW200820428A (en) 2008-05-01
WO2008036484A2 (en) 2008-03-27

Similar Documents

Publication Publication Date Title
TWI257148B (en) A self aligned non-volatile memory cell and process for fabrication
TW200616236A (en) Self aligned non-volatile memory cells and processes for fabrication
WO2012050779A3 (en) Memory arrays having different substantially vertical distances between adjacent memory cells
ATE546829T1 (en) METHOD FOR PRODUCING A NON-VOLATILE FLOATING GATE MEMORY CELL
TW200713520A (en) Non-volatile memory and fabricating method thereof
TW200802735A (en) Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element
WO2012096841A3 (en) Memory devices incorporating strings of memory cells having string select gates, and methods of forming the same
WO2012009076A3 (en) Memory arrays having substantially vertical, adjacent semiconductor structures and their formation
TW200605334A (en) Single poly non-volatile memory
WO2004034468A3 (en) Flash memory array with increased coupling between floating and control gates
WO2010111072A3 (en) Methods, devices, and systems relating to a memory cell having a floating body
WO2008057686A3 (en) Template for three-dimensional thin-film solar cell manufacturing and methods of use
TW200643952A (en) Bidirectional split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
FR2918794B1 (en) NON-VOLATILE SRAM MEMORY CELL HAVING MOBILE GRID TRANSISTORS AND PIEZOELECTRIC ACTUATION.
TW200635042A (en) Split gate flash memory and manufacturing method thereof
WO2008036552A3 (en) Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
TWI263342B (en) Non-volatile memory and manufacturing method and operating method thereof
WO2008036484A3 (en) Nonvolatile memory with reduced coupling between floating gates
TW200625608A (en) Non-volatile memory device and manufacturing method and operating method thereof
TW200419783A (en) Flash memory with selective gate within a substrate and method of fabricating the same
TW200701440A (en) Non-volatile memory and manufacturing method and operating method thereof
ATE529892T1 (en) WRITE-PROTECTED MEMORY WITH EEPROM STRUCTURE
TW200802818A (en) Nonvolatile memory device and method of fabricating the same
TW200631166A (en) Non-volatile memory and manufacturing method thereof
TW200620635A (en) Non-volatile memory cell in a trench having a first portion deeper than a second portion, an array of such memory cells, and method of manufacturing

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07814194

Country of ref document: EP

Kind code of ref document: A2