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WO2008027114A2 - Réseau de ressources de calcul - Google Patents

Réseau de ressources de calcul Download PDF

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Publication number
WO2008027114A2
WO2008027114A2 PCT/US2007/015869 US2007015869W WO2008027114A2 WO 2008027114 A2 WO2008027114 A2 WO 2008027114A2 US 2007015869 W US2007015869 W US 2007015869W WO 2008027114 A2 WO2008027114 A2 WO 2008027114A2
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WO
WIPO (PCT)
Prior art keywords
computational
neighbor
upstream
computational resources
downstream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/015869
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English (en)
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WO2008027114A3 (fr
Inventor
Robert C. Botchek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tableau LLC
Original Assignee
Tableau LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/510,922 external-priority patent/US20080052525A1/en
Priority claimed from US11/510,894 external-priority patent/US20080052490A1/en
Priority claimed from US11/510,950 external-priority patent/US20080126472A1/en
Priority claimed from US11/511,190 external-priority patent/US20080052429A1/en
Application filed by Tableau LLC filed Critical Tableau LLC
Publication of WO2008027114A2 publication Critical patent/WO2008027114A2/fr
Publication of WO2008027114A3 publication Critical patent/WO2008027114A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2131—Lost password, e.g. recovery of lost or forgotten passwords

Definitions

  • the present invention relates generally to data processing systems and, more particularly, to hardware-based systems capable of performing large scale data processing and evaluation.
  • a sea of computational resources includes a number of -computational resources, each of which is a member of one or more nearest neighbor pairings.
  • Each nearest neighbor pairing has an upstream neighbor and a downstream neighbor, and each nearest neighbor pairing transfers data between the upstream neighbor and the downstream neighbor using a nearest neighbor protocol.
  • atomic units of work are selectively passed from the highest upstream computational resource, which can be accessed by a gateway device or the like, to one or more downstream computational resources, one of which eventually performs the work (for example, data processing, etc.) and then passes the computational result from that work upstream.
  • the atomic units of work can be configured and/or formatted as request packets that can utilize a signature word as a work unit identifier.
  • the computational results can likewise be configured and/or formatted as response packets that also utilize the signature word as a work product identifier.
  • Each pair of computational resources thus includes a first computational resource and a second computational resource coupled to the first computational resource.
  • the first • computational resource is configured to operate as an upstream neighbor of the second computational resource and similarly the second computational resource is configured to operate as a downstream neighbor of the first computational resource.
  • Each computational resource communicates with its neighbor using a nearest neighbor protocol, which can be a three phase protocol involving offering a request packet, committing to transfer the request packet and, finally, either transferring the request packet or keeping the request packet for consumption by the upstream neighbor.
  • a nearest neighbor protocol can be a three phase protocol involving offering a request packet, committing to transfer the request packet and, finally, either transferring the request packet or keeping the request packet for consumption by the upstream neighbor.
  • the upstream neighbor can be designated to arbitrate the priority of simultaneous downstream and upstream communication requests and to propagate a clock signal used by the computational resources.
  • each upstream neighbor can have multiple downstream neighbors and, likewise, each downstream neighbor can have multiple upstream neighbors.
  • the computational resources can be programmable devices such as FPGAs or the like. Consumption of a single request packet (that is, atomic unit of work) generates a single response packet (that is, computational result) that is passed upstream to a desired location, such as a host computer utilizing the nearest neighbor array.
  • the configuration of the nearest neighbor pairings can be a 2-dimensional matrix, a octagonal connection array, a star array, or any other configuration that allows appropriate utilization of the computational resources by a host computer or other user of the sea of computational resources. Further details and advantages of the invention are provided in the following Detailed Description and the associated Figures.
  • Figure 1 is a flow diagram according to one or more embodiments of the present invention.
  • Figure 2 is a schematic diagram illustrating a host computer system coupled to a hardware accelerator, according to one or more embodiments of the present invention.
  • Figure 3 is a schematic diagram illustrating a logic resource such as an FPGA 5 according to one or more embodiments of the present invention.
  • Figure 4 is a schematic and flow diagram illustrating data flow between two logic resources in a sea of computational resources (for example, a processing matrix) according to one or more embodiments of the present invention.
  • Figure 5 is a state diagram showing request packet flow in a nearest neighbor pairing according to one or more embodiments of the present invention.
  • Figure 6 is a block diagram of a typical computer system or integrated circuit system suitable for implementing embodiments of the present invention, including a hardware accelerator that can be implemented and/or coupled to the computer system according to one or more embodiments of the present invention.
  • Embodiments of the present invention relate to techniques, apparatus, methods, etc. that can be used in interconnecting a plurality of computational resources in a computational unit or the like.
  • the invention is explained in part using a processing matrix in a password recovery system as an exemplary use of the present invention, but the invention is not limited to such an application, as will be appreciated by those skilled in the art.
  • a host computer is coupled to and utilizes a processing matrix (or other type of sea of computational resources) as part of a computational unit, wherein the processing matrix comprises a number of computational resources that are interconnected using a nearest neighbor protocol.
  • the interconnection of computational resources and the techniques available for sharing computational work among the computational resources use one or more embodiments of the present invention.
  • a specific family of password recovery techniques may be termed "brute force” attacks wherein specialized and/or specially adapted software/equipment is used to try some or all possible passwords.
  • the most effective such brute force attacks frequently rely on an understanding of human factors. For example, most people select passwords that are derived from words or names in their environment and which are therefore easier to remember (for example, names of relatives, pets, local or favorite places, etc.).
  • This understanding of the human factors behind the selection of passwords allows the designers of the "brute force” attacks to focus the attacks on words derived from a "dictionary" which itself is based on and constructed from an understanding of the environment in which the password was selected.
  • Embodiments of the present invention include systems, apparatus, methods, etc. used to implement a sea of computational resources (in the form of multiple nearest neighbor pairings) for use by a host computer or the like.
  • a computational unit using one or more embodiments of the present invention can generally be characterized as possessing three functional levels and/or blocks: 1) an input such as a front-end interface designed to communicate with the host computer (for example, a host computer on which password recovery or other encryption breaking software and intermediate software are executing), 2) a gateway coupled to the input, where the gateway can include a master device (for example, an FPGA) and a memory and an associated controller (which can be part of the master device), wherein the memory stores both unprocessed data (for example, blocks of passwords or other encrypted data to be processed) and blocks of computational results to be sent to the host computer or elsewhere via the host computer, and 3) coupled to the gateway, a sea of computational resources (referred to herein in some cases as a processing matrix of symmetric logic resources) according to one or more embodiments of the present
  • Some embodiments of the present invention are designed to work in conjunction with existing applications, such as password recovery applications.
  • password recovery applications can function as primary software in embodiments of the present invention and are already capable of generating lists of password candidates to be tested, to compute cipher keys based on each password candidate, and to test the validity of each cipher key.
  • Earlier password recovery applications have been limited in their performance by the computational capability of the computer processors on which they were executed.
  • the responsibility of calculating cipher keys is outsourced from the password recovery applications to an invoked intermediate software API (Application Programming Interface) to send passwords to one or more hardware accelerators according to embodiments of the present invention.
  • Each hardware accelerator performs the computationally expensive cipher calculations and then returns its results to the intermediate software API, which in turn sends the results to the password recovery applications.
  • FIG. 1 One example of a password recovery system that can utilize the present invention is shown in Figure 1, where method 100 begins at 110 with data (for example, blocks) being generated for testing. In some cases, this block generation can be performed by software running on a host computer to create password candidates for testing. At 120 the data to be tested can be formatted for test processing. In the example involving password discovery, an intermediate software layer, such as the above-referenced invoked API, can format and package the password candidates for processing by the computational resources in the computational unit coupled to the host computer. The blocks can then be processed at 130, for example by processing the password candidates to try and find a target password.
  • data for example, blocks
  • this block generation can be performed by software running on a host computer to create password candidates for testing.
  • the data to be tested can be formatted for test processing.
  • an intermediate software layer such as the above-referenced invoked API, can format and package the password candidates for processing by the computational resources in the computational unit coupled to the host computer.
  • the blocks can then be processed at 130, for example by
  • a processing matrix in computational unit can look for particular signatures in the matrix calculation results to validate the probability that a given password candidate is the target password.
  • a processing matrix can return processing results to an external entity or module, such as the primary or intermediate software, for further validation of the calculations and/or determinations regarding the target password.
  • the results of processing done at 130 are received for further evaluation or the like, for example receipt by the intermediate software layer for unpacking of the processing results and forwarding the unpacked results to the primary software.
  • Validation and/or verification can be performed at 150.
  • the primary software can verify whether one or more password candidates are indeed the target password sought by the primary software.
  • the intermediate software formats data exchanged between the primary software and the hardware accelerator, whether computational results or password candidates, and the hardware accelerator performs the computationally expensive processing of the candidate data. Other general schemes that would benefit from the available computational unit will be apparent to those skilled in the art.
  • Embodiments of the present invention include a computational unit (for example, a hardware accelerator) that can be coupled to another device (for example, a host computer) via an input and/or interface.
  • the computational unit includes computational resources (such as FPGAs or the like) and can communicate with the host computer using a storage interface protocol.
  • computational resources such as FPGAs or the like
  • FIG. 2 One such computational unit 200 is shown in Figure 2. In the exemplary system 200 of Figure 2, two input types are available - a USB input 202 and a FireWire input 204.
  • At least one such input is coupled to the host computer 230.
  • phrases such as “coupled to” and “connected to” and the like are used herein to describe a connection between two devices, elements and/or components and are intended to mean coupled either directly together, or indirectly, for example via one or more intervening elements or via a wireless connection, where appropriate.
  • a bridge 206 connects these inputs 202, 204 to a gateway 208 and transfers data between a host computer interface and a storage interface.
  • bridge 206 can be an Oxford Semiconductor OXUF922 device
  • the host computer interface can be a 1394 interface 204 or a USB interface 202
  • the storage interface can be an IDE BUS 207.
  • Devices such as the Oxford Semiconductor are inexpensive, readily available, and are well optimized for moving data between the host computer interface and the storage interface.
  • IDE BUS 207 may require additional bus interface logic in gateway 208, this additional complexity is more than offset by the cost, availability, and performance advantages afforded by the selection of an appropriate bridge 206.
  • Gateway 208 can be a device, a software module, a hardware module or combination of one or more of these, as will be appreciated by those skilled in the art.
  • gateway 208 can be a device such as an application specific integrated circuit (ASIC), microprocessor, master FPGA or the like, as will be appreciated by those skilled in the art.
  • ASIC application specific integrated circuit
  • microprocessor microprocessor
  • master FPGA master FPGA
  • a memory 210 is coupled to the gateway 208 and is used for storing (for example, in a
  • DDR SDRAM memory incoming data to be processed (for example, blocks of password candidates) and for storing computational results from a sea of computational resources 250 (also referred to as a processing matrix or an array herein).
  • the bridge 206 and the gateway 208 are coupled to another memory 212 via a processor bus 209 (for example, an ARM bus or the like).
  • Memory 212 can include flash memory containing code and/or FPGA configuration data, as well as other information needed for operation of the system 200.
  • Logic for controlling and configuring the gateway 208 and configuration data in unit 212 can be housed in a module 214.
  • additional controls, features, etc. for example, temperature sensing, fan control, etc.
  • Gateway 208 controls data flow into and out of array 250.
  • computational resources sea 250 has a plurality of logic resources 255 (for example, programmable devices such as FPGAs) coupled to one another as pairings (even where a given computational resource has multiple connections to other computational resources, these are merely multiple pairings) using a "nearest neighbor" configuration and/or protocol, which is explained in more detail below.
  • Each logic resource 255 is provided with one or more clock signals 262 and data/control signals 264. FPGA coupling and use of these signals are described in more detail below.
  • the northwestern-most device 255 is the device farthest upstream in the array. Thus request packets from the gateway 208 flow downstream to all other devices from this northwestern-most position and all response packets in this embodiment flow back to this northwestern-most position in the array 250.
  • Some embodiments of the present invention provide significant advantages by emulating block-oriented storage devices (for example, a hard disk) when communicating with a host computer. Such emulation radically simplifies a number of software development problems and greatly enhances portability of the processing system of the present invention across different host and operating system environments.
  • Software on the host computer 230 can read from a well-known address (for example, sector 0 is an example of one such well-known address, though there are many alternative addresses that can be used, as will be appreciated by those skilled in the art) to determine the current status and capabilities of the hardware accelerator 200.
  • the computational unit 200 generally disallows block write operations to the well-known address to prevent standard block-oriented drivers and utilities in the host computer's operating system (O/S) from attempting to format the contents of the perceived block-oriented storage device (that is, the computational unit 200), thus dissuading standard drivers from attempting other input/output (I/O) operations to the computational unit 200 that is emulating a block-oriented storage device.
  • O/S operating system
  • I/O input/output
  • Atomic units of work can be formatted into “request packets” (for example, by intermediate software on the host computer 230) and then concatenated into arrays of request packets (which can be padded to multiples of 512 bytes in length, inasmuch as 512 bytes is a typical block size when transferring data to/from a block- oriented storage device).
  • the padded arrays of request packets are then transmitted to the hardware accelerator 200 using a block write request appropriate for the interface bus through which the hardware accelerator is connected. (The necessary sector address for the block write request can be made known to host software through information returned in response to reading the well-known address.)
  • the hardware accelerator 200 buffers this block-oriented data transmission in on-board memory 210.
  • the computational unit memory 210 is conceptually organized in the system of Figure 2 as a FIFO.
  • a computational unit memory controller which may be part of the gateway 208, extracts successive request packets from the computational unit memory and re-transmits the request packets, typically one at a time, to the logic resources 255 of FPGA matrix 250, which generate computational results from the request packets and send these results to the host computer 230 (for example, to the intermediate software for formatting and/or other processing before substantive review/evaluation by the primary software), hi this case, the logic resources format "responses” into “response packets” and transmit these response packets to the computational unit memory controller which in turn stores the response packets in memory 210.
  • the memory dedicated to response packets is conceptually organized as a FIFO.
  • packet mode of operation discussed herein is only one of a wide variety of communication schemes that can be used in connection with embodiments of the present invention, wherein a computational matrix performs one or more tasks.
  • the request packet and response packet type of operational mode is provided herein as an example only.
  • software on the host computer 230 can perform block read requests to the computational unit 200 at periodic intervals. (As with earlier block write requests, the necessary sector address for the block read request can be made known to host software through information returned in response to reading the well-known address.)
  • the computational unit 200 interprets these block read requests as requests to read from the response packet FIFO in memory buffer 210.
  • the memory controller concatenates response packets into arrays of response packets and then pad the end of the data transfer to a multiple of 512 bytes in length. Further, the memory controller ensures that only whole response packets are returned to the host computer. That is, a single response packet will not be split across two read requests from the host computer.
  • the computational unit can be designed to run as a hardware accelerator across a number of different host computer and O/S environments. Normally, to make custom hardware such as the hardware accelerator compatible with diverse environments, earlier systems and the like would require the development of customer device drivers for each of the environments. The development of such device drivers is generally complex, time-consuming, and expensive. To eliminate this need, the present invention can use one or more standard block-oriented storage protocols (for example, hard disk protocols) to communicate with the host computer.
  • Current O/S environments have built-in support for devices which support standard block- oriented storage protocols. This built-in support means that application level code on the host computer typically can communicate with a block-oriented storage device without needing custom drivers or other "kernel" level code. For example, in most current O/S environments, an application can query the identity of all attached block-oriented storage devices, "open" one of the devices, then perform arbitrary block read and write operations to that device.
  • the computational unit is coupled to the host computer via an IEEE- 1394 (that is, Fire Wire) or USB (Universal Serial Bus) interface and can expose itself to the host computer as a storage device.
  • IEEE- 1394 that is, Fire Wire
  • USB Universal Serial Bus
  • the computational unit exposes itself as an SBP-2 (Serial Bus Protocol-2) device, which is the standard way block-oriented storage devices are exposed over 1394.
  • SBP-2 Serial Bus Protocol-2
  • USB Universal Serial Bus Protocol-2
  • the computational unit exposes itself as a device conforming to the USB Mass Storage Class Specification, which is the standard way block-oriented storage devices are exposed over USB.
  • Request and response packets can share a common, generalized header structure.
  • the contents of a given request/response packet payload may vary depending on the nature of the computation being performed by the hardware accelerator.
  • Table 1 provides an exemplary packet structure (all multi-byte integer values such as packet length, signature word, etc. are stored in little-endian byte order, where the least significant byte of each multi-byte integer value is stored at the lowest offset within the packet):
  • the Packet Length field defines a total packet length of n bytes, where (in this embodiment) n is always an even value greater than or equal to 6. Placing the Packet Length field at the beginning of the packet simplifies hardware design, allowing hardware to detect/determine total packet length by inspecting only the packet's first 16-bit word.
  • the Signature Word can be a 32-bit project or task "identifier" value and is unique for all packets at any given point in time. Signature words provide an efficient mechanism for associating request and response packets. This feature allows request packets to be processed by an arbitrary logic resource and to be processed in non-deterministic order. Signature Word values can be assigned by software in the host computer when the host software formats the request packets using any algorithm to assign and re-use Signature Word values so long as no two active (that is, outstanding) request packets sent to the same hardware accelerator have the same Signature Word value at the same time.
  • software on the host computer may determine that a maximum of M request packets can be outstanding at a time for a given hardware accelerator. Then, software may allocate an array S of M 32-bit storage elements. Software would initialize array S such that:
  • software on the host computer can allocate a second array R of M storage elements. Each element in this second array will provide storage for one request packet. Assuming that array S is initialized as shown above, then Signature Word values in array S can be used as indexes into the second array of structures R. As each Signature Word value is unique, the host software is guaranteed that the element thus selected in array R is not currently in use and may be used as storage for a newly formatted request packet.
  • the Signature Word value in the response packet is used to associate the response packet with the element in array R which stores the original request packet, hi this way, host software can efficiently associate requests and responses even though responses arrive in a non- deterministic order.
  • Tahles 2 and 3 show examples of request and response packets as they may appear in an implementation of the hardware accelerator specifically designed to do password attack computations:
  • Firmware Stepping, Firmware Build Date, and Firmware Build Time allow host software to determine automatically the generation of firmware running in the hardware accelerator.
  • Matrix Technology Code, Matrix Row Count, and Matrix Column Count allow host software to determine the FPGA technology and FPGA matrix dimensions. Buffer
  • Memory Size indicates the total amount of buffer memory installed in the hardware accelerator.
  • Request FIFO Data Available Count indicates the maximum number of bytes that may be written to the Request Packet FIFO at the present time and Request FIFO Address indicates the sector address to be used when writing to the Request Packet FIFO.
  • Response FIFO Data Available Count indicates the maximum number of bytes which may be read from the Response Packet FIFO at the present time and Response FIFO Address indicates the sector address to be used when reading from the Response Packet FIFO.
  • Configuration Sector Address identifies the sector address of the Configuration Sector. The Configuration Sector is written by host software to set the current operating parameters of the hardware accelerator.
  • Bit-Stream Size indicates the maximum length of FPGA configuration bit stream which can be written by the host.
  • Bit-Stream Sector Address identifies the sector address to be used when writing an FPGA configuration bit stream to the hardware accelerator.
  • SRAM-based FPGAs in the hardware accelerator are not configured.
  • host software Before the hardware accelerator can process request packets, host software must write an appropriate FPGA configuration bit stream to the hardware accelerator.
  • Each FPGA may be configured with the same or different configuration bit streams as necessary to implement the logic resources as required for a given hardware accelerator and/or computational unit application.
  • Configuration bit streams are developed using FPGA development tools appropriate for the FPGAs as used in the matrix of the hardware accelerator.
  • the FPGAs in the processing matrix can be Xilinx XC3S1600E-FG320 components.
  • Host software can perform block reads and block writes of the Configuration Sector to configure matrix FPGAs in the hardware accelerator according to the format of Table 5:
  • the Control Word contains a number of bits which direct firmware in the hardware accelerator to perform FPGA configuration actions.
  • a Control Word may be configured as follows:
  • DEV_EN should always be set to "1" either before or when attempted to configure the FPGA. Setting the CFGJtST bit to a "1" resets the hardware accelerator configuration logic and restores the FPGA Configuration Bit- Stream address pointer to the beginning of the FPGA
  • MTRXJtST bit Setting the MTRXJtST bit to a "1" resets all logic in the FPGA matrix. This operation is global to all FPGAs in the matrix. MTRXJR.ST should be used, for example, at the end of a hardware acceleration job. The MTRX_RST bit resets to "0" automatically.
  • the Status Word contains a number of bits which indicate the status of the current
  • a Status Word may be configured as follows:
  • BUSY is read as "1" when the hardware accelerator is busy processing a configuration request.
  • INIT and DONE indicate that the FPGA is driving its configuration INIT and DONE signals, respectively.
  • DEVJEN is read as "1" when the FPGA is powered ON.
  • the Status Word bits always reflect the configuration state of the FPGA identified by the row and column in FPGA Row Address and FPGA Column Address, respectively.
  • FPGA Row Address and FPGA Column Address are written by the host to indicate the coordinates of an FPGA within the matrix to be configured.
  • FPGA Bit-Stream Length indicates the length of the configuration bit-stream that has been written from the host to the FPGA Configuration Bit-Stream Buffer. This indicates the number of FPGA configuration bits that should be copied from the FPGA Configuration Bit- Stream Buffer to the selected FPGA during configuration.
  • the FPGA Configuration Bit-Stream Buffer is the memory that is written when host software performs block write operations to the FPGA Configuration Bit-Stream Sector address. Before writing a new bit stream, host software should always write a " 1" to the CFG_RST in the Control Word.
  • Tasks thus can be split between a host computer and a computational unit according to one or more embodiments of the present invention.
  • the computational unit while specialized in its ability to receive and process large quantities of data, is nonetheless general and adaptable in its ability to be configured to work on a large number of different tasks (for example, in the case of attacking passwords, encryption algorithms).
  • This flexibility is derived, in part, from the use of FPGAs and/or other programmable devices in one or more implementations of a computational matrix in the computational unit.
  • "SRAM-based" FPGAs which do not retain their configuration (that is, their programming) across power-down, reflect the practice of building such devices on an underlying matrix of static RAM based memory cells. This FPGA variety is usable in embodiments of the present invention.
  • Computational units can generally be thought of as possessing three major functional blocks: 1) a front-end interface/input designed to communicate with a host computer or other device (for example, on which application software is executing, 2) a memory unit having a controller coupled to a memory buffer that stores data to be processed by the computational matrix and computational results from the computational matrix to be forwarded to a destination outside the computational unit, and 3) a computational or processing matrix of symmetric logic resources (for example, an FPGA matrix) capable of being configured to perform the specific computations required of each encryption scheme.
  • a front-end interface/input designed to communicate with a host computer or other device (for example, on which application software is executing
  • a memory unit having a controller coupled to a memory buffer that stores data to be processed by the computational matrix and computational results from the computational matrix to be forwarded to a destination outside the computational unit
  • 3) a computational or processing matrix of symmetric logic resources for example, an FPGA matrix
  • the front-end interface allows the computational unit to be coupled to the host computer via one or more interfaces that allow easy connection to a wide variety of host computers.
  • interfaces that allow easy connection to a wide variety of host computers.
  • Fire Wire and/or USB interfaces are commonly in use and can be used in connection with embodiments of the present invention.
  • the memory unit (comprising, for example, a memory and its associated controller, which can be part of the gateway) is responsible for buffering blocks of passwords to be processed.
  • the memory controller and memory are also responsible for buffering the computational results generated for each password so that those results can be transmitted back to the host computer.
  • Other memory configurations can be used, as will be appreciated by those skilled in the art, and those presented in the Figures and herein are provided as examples only.
  • the processing matrix of symmetric logic resources is built using SRAM-based FPGAs in some embodiments of the present invention.
  • SRAM-based FPGAs accomplishes two objectives: 1) the logic resources can be reconfigured readily to perform different functions (for example, attacks on different encryption schemes), and 2) SRAM-based FPGAs tend to cost less per unit logic than other FPGA technologies, allowing more logic resources to be deployed at a given cost, and thus increasing the number of password attacks that can be performed in parallel at a given hardware cost.
  • the use of such logic resources also means that the computational matrix of the computational unit can be configured to perform more than one task/function, for example where some FPGAs are programmed to perform a first processing task and other FPGAs in the matrix are configured to perform a second, following task.
  • each password candidate or other candidate data packet can be formatted into a "request packet" buffered in the memory unit of the hardware accelerator, while the computational results generated for each password candidate or other candidate data are formatted into a "response packet" that also are temporarily buffered in the memory unit prior to transmission to the host computer.
  • a single logic resource 300 such as an FPGA 5 usable in a computational unit according to one or more embodiments of the present invention is shown in more detail in Figure 3.
  • Device 300 could be any of the devices 255 of Figure 2, though one or more neighboring device interfaces might be inactive, depending on the position of device 300 in the processing matrix 250. Every logic resource 300 in the example of Figure 3 must have at least one clock signal, coming from a west neighbor, a north neighbor, or both.
  • two clock signals 262n and 262w are shown as inputs to device 300.
  • a clock signal multiplexer 302 selects which signal to use.
  • a clock multiplexer control signal can be provided by a detection coordination unit 304 or the like, as will be appreciated by those skilled in the art.
  • Each device 300 can have a west nearest neighbor interface 310, a north nearest neighbor interface 312, an east nearest neighbor interface 314 and a south nearest neighbor interface 316.
  • a request packet available at the west interface 310 or the north interface 312 is available to be sent to a downstream multiplexer 320, which feeds incoming downstream request packets to a downstream FIFO buffer 322. From FIFO buffer 322, downstream request packets are sent to a request packet router 324.
  • router 324 can either send a downstream request packet to the computational block(s) 350 of device 300 for processing in device 300 or make the request packet available to the east interface 314 and/or south interface 316 for possible processing further downstream (at a neighboring device).
  • Device 300 can contain one or more computational blocks 350, depending on the space and resources available on a given type of device 300 (for example, an FPGA), the complexity and/or other computational costs of processing to be performed on request packets, etc.
  • device 300 might contain multiple instantiations of such computational blocks 350 so that multiple request packets can be processed simultaneously in parallel on a single device 300. For purposes of this discussion, it is assumed that device 300 can have such multiple instantiations of a required computational block 350.
  • the east interface 314 and south interface 316 can be coupled to an upstream multiplexer 330.
  • Multiplexer 330 also receives completed computational results as response packets from the computational blocks 350 of device 300.
  • Multiplexer 330 provides the response packets it receives to an upstream FIFO buffer 332 and thence to an upstream response packet router 334.
  • Upstream response packet router 334 can send the response packets it receives to either the north interface 312 or the west interface 310 for further upstream migration toward the gateway.
  • Detection coordinator 304 also can control other elements of device 300, such as the downstream multiplexer 320 and upstream response packet router 334.
  • An upstream FPGA 410 can provide a synchronous clock signal 420, downstream control signals 422 and data on a bi-directional signal line 424 (for example, carrying 16 bits) to a downstream FPGA 430.
  • downstream FPGA 430 can provide upstream control signals 432 and data on bidirectional signal line 424 to upstream FPGA 410.
  • Downstream control/status can include:
  • the upstream FPGA 410 is always the arbiter, so that when both the upstream FPGA 410 and the downstream FPGA 430 request a transmit at the same time, the upstream FPGA 410 determines which command will take priority.
  • the downstream FPGA 430 is responsible for propagating the synchronous clock signal to any FPGA(s) further downstream.
  • an upstream device can request a transmit 504 to a downstream device, after which a transmit request is pending at state 506.
  • the upstream device can cancel the transmit at 508 by going back to BDLE 502 or can commit to the transmit at 510 by going to the transmit ready state 512 (which can include "transmit ready” and/or "transmit ready EOP" states, where the upstream device drives the data bus).
  • the upstream device can pause by going at 516 to a transmit wait state 518 (after which the upstream device returns at 520 to the transmit ready state 512) or can complete the transmission at 514, after which the upstream device returns to IDLE 502.
  • the upstream device can sit in IDLE 502 until a receipt request is received.
  • the upstream device can acknowledge the request at 522 and enter the receive acknowledged state 524.
  • the device can hold this state at 526, cancel the reception at 528 by returning to IDLE 502, or move at 530 to a receive ready state 532 when the downstream device commits to sending the data to the upstream device.
  • the device can wait by moving at 536 to a receive wait state 538, after which it returns at 540 to the receive ready state 532.
  • the device can move at 534 back to the IDLE state 502.
  • control/status bits can change on the negative edge of a synchronous clock signal while data can be clocked on the positive edge of the synchronizing clock only when both upstream and downstream devices are signaling "ready.”
  • Clock synchronization is a major problem in complex digital logic designs such as those found in embodiments of the present invention.
  • a "nearest neighbor" scheme can be used in some embodiments of the present invention.
  • each FPGA in the processing matrix only communicates with one or more of its nearest neighbors in the matrix.
  • the terms North, South, East, and West are used herein to designate the 4 nearest neighbors to a given programmable device, using the cardinal points of the compass in their usual two dimensional sense.
  • each computational resource has a maximum of 4 nearest neighbors.
  • the nearest neighbor pairings will function analogously and thus provide the multiple pairings described in detail herein.
  • One "nearest neighbor” architecture that can be employed in embodiments of the present invention is shown in the sea of computational resources 250 of Figure 2, where each "interior” device 255i is coupled to its 4 neighboring devices, each "edge” device 255e is coupled to 3 of its neighboring devices, and each “corner” devices 255c is coupled to 2 of its neighboring devices.
  • This nearest neighbor architecture of Figure 2 facilitates the design of a symmetric array of FPGA-based logic resources with the following attributes, among others:
  • Nearest-neighbors can communicate bi-directionally at high-speed.
  • Each computational resource (for example, FPGA-based logic resource) is clock synchronized to its nearest neighbor to the "North” or to the "West” in the matrix.
  • Each computational resource (for example, FPGA-based logic resource) communicates with resources no farther than its nearest neighbors vertically (North and/or South) and/or horizontally (East and/or West).
  • ⁇ Request packets flow from the gateway 208 and upper left (northwest-most) device 255 to the lower right (that is, in a generally southeast migration).
  • the matrix dimensions (that is, the dimensions of any nearest neighbor array and/or configuration) can scale more or less arbitrarily, allowing matrices of greater or fewer resources (through the number of resources and/or through the coupling scheme between resources) to be deployed as best fits the cost and performance requirements of the design.
  • the nearest neighbor architecture is the available bidirectional transfer protocol. This protocol can govern transfers between each pair of coupled adjacent neighbors in the configuration. Pairings are either vertical (that is, north-south) or horizontal (that is, east-west). In vertical pairings in the embodiment shown in Figure 2, the neighbor to the North is the master and in horizontal pairings the neighbor to the West is the Master. Likewise, the neighbor to the South or East is the Slave. In this discussion, the Master is also sometimes termed the "upstream” neighbor and transfers towards the master are termed “upstream” transfers. Similarly, the Slave is sometimes termed the "downstream” neighbor and transfers towards the Slave are termed "downstream” transfers.
  • Each master is responsible for propagating/driving the synchronizing clock to the slave.
  • the master also is responsible for determining the direction of each data transfer on the bi- directional interface. If the master and the slave make simultaneous requests to transfer data, the master arbitrates the conflicting requests and determines the prevailing transfer direction.
  • Each FPGA has one or more computational blocks capable of processing request packets (for example, each programmable device 255 can be programmed to implement 1, 2, 3, 8, 12 or any other number of computational blocks within the programmable device, as will be appreciated by those skilled in the art).
  • Each computational block within an FPGA is always in one of two states: 1) idle - not currently processing a request packet, or 2) busy - actively processing a request packet (also referred to herein as "consuming" a request packet, which generates a response packet containing a computational result).
  • Each FPGA has an input FIFO that can buffer one or more request packets (it is advantageous in most embodiments to have the FIFO large enough to make sure that the computational blocks are idle for as short a time as possible - that is, it generally is good for there to be one or more request packets waiting at all times in each device of the computational resource array).
  • a computational resource device If a computational resource device has an idle computational block, it prefers to consume a request packet rather than passing it to a downstream neighbor.
  • the FPGA will offer the request packet to one or more of its downstream neighbors (that is, the neighbor to the South or the neighbor to the East in Figure 2).
  • a "three-phase" nearest-neighbor protocol can be used (which can be considered in light of the state machine 500 of Figure 5 in some embodiments of the present invention).
  • an upstream neighbor "offers" a request packet to one or more downstream neighbors.
  • the upstream neighbor either commits to the transfer or cancels the transfer.
  • the upstream neighbor can only commit to the transfer if its downstream neighbor is currently indicating that it can accept the transfer.
  • a downstream neighbor signals that it is able to accept a transfer by entering the "request acknowledge" state.
  • a downstream neighbor Once having entered the "request acknowledge" state, a downstream neighbor cannot leave this state unless and until the upstream neighbor commits to the transfer or cancels the transfer request.
  • the upstream neighbor may cancel a transfer request whether or not the downstream neighbor has entered the request acknowledge state.
  • the upstream neighbor begins and ultimately completes the transfer of a request packet to a downstream neighbor.
  • the flow of response packets from downstream neighbors towards their upstream neighbors can be symmetric to that described for the flow of request packets.
  • the downstream (or slave) device is responsible for offering a response packet and then committing to the transfer.
  • the upstream (or master) device is responsible for accepting response packets.
  • a particularly advantageous characteristic of this architecture is the ability of a device in a sea of computational resources to offer a packet for transfer without specifically committing to the transfer of that packet.
  • This capability allows each device in the processing matrix: 1) to offer packets to more than one nearest neighbor without knowing in advance which neighbor will ultimately accept the packet, and 2) to offer packets to neighbors while still retaining the option to process a packet internally.
  • This three-phase protocol permits nearly optimal utilization of logic and communication resources within the array.
  • Each device/FPGA then communicates "upstream" with the device/FPGA from which it receives its synchronizing clock using the bi-directional data interface discussed above.
  • This data interface operates synchronously to the clock. Request packets are passed from the "upstream” neighbor to the "downstream” neighbor, and response packets are passed in the reverse direction. In this manner, the problems of clock synchronization across the hardware accelerator are greatly mitigated. In this scheme, it is necessary only for "nearest neighbors" (that is, upstream/downstream computational resource pairings) to be synchronized with each other.
  • appropriate request packets are fed into the sea of computational resources by the memory controller. If logic resources in a given device/FPGA are available to process the request packet immediately, the request packet is said to be "consumed” by the given device/FPGA (that is, the atomic unit of work is processed to generate a computational result). If no logic resources are presently available to process the request packet, then the device/FPGA will attempt to pass the request packet to one of its downstream neighbors (to the "East” or to the "South” in Figure 2). This process continues until all logic resources are busy and a given request packet can be passed no further downstream (East or South). As logic resources complete the processing associated with each candidate data block (for example, a password candidate), those logic resources once again become available to process new requests.
  • Figure 6 illustrates a typical computer system that can be used as a host computer and/or other component in a system in accordance with one or more embodiments of the present invention.
  • the computer system 600 of Figure 6 can execute primary and/or intermediate software, as discuss in connection with embodiments of the present invention above.
  • the computer system 600 includes any number of processors 602 (also referred to as central processing units, or CPUs) that are coupled to storage devices including primary storage 606 (typically a random access memory, or RAM), primary storage 604 (typically a read only memory, or ROM).
  • primary storage 604 acts to transfer data and instructions uni-directionally to the CPU and primary storage 606 is used typically to transfer data and instructions in a bi-directional manner.
  • a mass storage device 608 also is coupled bi-directionally to CPU 602 and provides additional data storage capacity and may include any of the computer-readable media described above.
  • the mass storage device 608 may be used to store programs, data and the like and is typically a secondary storage medium such as a hard disk that is slower than primary storage. It will be appreciated that the information retained within the mass storage device 608, may, in appropriate cases, be incorporated in standard fashion as part of primary storage 606 as virtual memory.
  • a specific mass storage device such as a CD-ROM 614 may also pass data uni-directionally to the CPU.
  • CPU 602 also is coupled to an interface 610 that includes one or more input/output devices such as such as video monitors, track balls, mice, keyboards, microphones, touch- sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers.
  • CPU 602 optionally may be coupled to a computer or telecommunications network using a network connection as shown generally at 612. With such a network connection, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing described method steps.
  • CPU 602 when it is part of a host computer or the like, optionally may be coupled to a computational unit 200 as one embodiment of the present invention that is used to assist with computationally expensive processing and/or other tasks.
  • Apparatus 200 can be the specific embodiment of Figure 2 or a related embodiment of the present invention.
  • the above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.
  • the hardware elements described above may define multiple software modules for performing the operations of this invention. For example, instructions for running a data encryption cracking program, password breaking program, etc. may be stored on mass storage device 608 or 614 and executed on CPU 602 in conjunction with primary memory 606.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Advance Control (AREA)
  • Storage Device Security (AREA)

Abstract

Un ensemble de ressources de calcul comprend une pluralité de ressources de calcul appartenant, chacune d'elles, à un ou plusieurs appariements de voisins les plus proches. Chacun des ces appariements de voisins les plus proches comprend un voisin amont et un amont aval et chaque appariement de voisins les plus proches transfère des données entre le voisin amont et le voisin aval à l'aide d'un protocole de voisin le plus proche. Globalement, des unités de travail atomiques sont sélectivement transférées de la ressource de calcul amont la plus haut, à laquelle on peut accéder par une passerelle ou analogue, à une ou plusieurs ressources de calcul aval dont au moins une va finalement réaliser le travail (le traitement de données, etc. par exemple), puis transfère le résultat de calcul pour ce travail en amont. Les unité de travail atomiques peuvent être configurées et/ou formatées sous forme de paquets de requête pouvant utiliser un mot de signature comme identifiant de produit de travail. Diverses règles peuvent être mises en place pour simplifier et optimiser le fonctionnement des ressources de calcul. La configuration des appariements de voisins les plus proches peut former une matrice en 2D, un réseau de connexion octogonal, un réseau en étoile ou n'importe quelle autre configuration permettant une bonne utilisation des ressources de calcul par un calculateur hôte ou tout autre utilisateur de l'ensemble de ressources de calcul.
PCT/US2007/015869 2006-08-28 2007-07-12 Réseau de ressources de calcul Ceased WO2008027114A2 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US11/510,922 US20080052525A1 (en) 2006-08-28 2006-08-28 Password recovery
US11/511,190 2006-08-28
US11/510,950 2006-08-28
US11/510,894 2006-08-28
US11/510,922 2006-08-28
US11/510,894 US20080052490A1 (en) 2006-08-28 2006-08-28 Computational resource array
US11/510,950 US20080126472A1 (en) 2006-08-28 2006-08-28 Computer communication
US11/511,190 US20080052429A1 (en) 2006-08-28 2006-08-28 Off-board computational resources

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WO2008027114A3 WO2008027114A3 (fr) 2008-04-24

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PCT/US2007/011809 Ceased WO2008027091A1 (fr) 2006-08-28 2007-05-17 Procédé et système de récupération de mot de passe au moyen d'un accélérateur matériel
PCT/US2007/012257 Ceased WO2008027092A1 (fr) 2006-08-28 2007-05-23 Communication informatique
PCT/US2007/015870 Ceased WO2008027115A2 (fr) 2006-08-28 2007-07-12 Ressources de calcul hors cote
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PCT/US2007/012257 Ceased WO2008027092A1 (fr) 2006-08-28 2007-05-23 Communication informatique
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CN105799620B (zh) * 2014-12-29 2019-01-22 上海通用汽车有限公司 车辆电子控制模块的安全代码计算
WO2018201249A1 (fr) 2017-05-03 2018-11-08 Eidetic Communications Inc. Appareil et procédé de commande d'accélération de données
CN108616535B (zh) * 2018-04-28 2021-02-09 浪潮集团有限公司 一种基于fpga多协议安全认证网络交换加速系统及方法

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US5577262A (en) * 1990-05-22 1996-11-19 International Business Machines Corporation Parallel array processor interconnections
WO1992006436A2 (fr) * 1990-10-03 1992-04-16 Thinking Machines Corporation Systeme d'ordinateur parallele
JP3136088B2 (ja) * 1996-02-22 2001-02-19 シャープ株式会社 データ処理装置及びデータ処理方法
US6085316A (en) * 1998-07-28 2000-07-04 Sun Microsystems, Inc. Layered counterflow pipeline processor with anticipatory control
GB2348974B (en) * 1999-04-09 2004-05-12 Pixelfusion Ltd Parallel data processing systems
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WO2008027115A2 (fr) 2008-03-06
WO2008027091B1 (fr) 2008-05-08
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WO2008027114A3 (fr) 2008-04-24
WO2008027092A1 (fr) 2008-03-06

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