WO2008023312A1

WO2008023312A1 - Substrate for the application of thin layers, and method for the production thereof

Info

Publication number: WO2008023312A1
Application number: PCT/IB2007/053286
Authority: WO
Inventors: Rogier A. H. Niessen; Petrus H. L. Notten; Johannes H. G. Op Het Veld; Remco H. W. Pijnenburg; Youri V. Ponomarev
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2006-08-21
Filing date: 2007-08-17
Publication date: 2008-02-28
Anticipated expiration: 2009-02-21

Abstract

The invention relates to a substrate for the application of thin layers. The invention further relates to a thin layer battery stack based on such a substrate. The invention also relates to a method for the manufacture of such a substrate. Moreover, the invention relates to a method for the application of at least one layer to such a substrate. The substrate may comprise multiple vias having a width of between 2 and 10 microns. The substrate may be made of silicon and the vias are produced by making holes in the substrate using an etching technique.

Description

Substrate for the application of thin layers, and method for the production thereof

FIELD OF THE INVENTION

The invention relates to a substrate for the application of thin layers. The invention further relates to a thin layer battery stack based on such a substrate. The invention also relates to a method for the manufacture of such a substrate. Moreover, the invention relates to a method for the application of at least one layer to such a substrate.

BACKGROUND OF THE INVENTION

Three-dimensional substrates for the application of thin layers are for instance used in the manufacture of thin layer battery stacks. An example hereof is disclosed in the international patent application WO2005/027245, where a solid-state thin-film battery, in particular a lithium ion battery, is fabricated directly onto a structured silicon substrate provided with multiple slits or trenches in which an electron-conductive barrier layer, and a stack of a silicon anode, a solid-state electrolyte, and a cathode are deposited successively. The slits or trenches are provided in the substrate to increase the contact surface area between the different components of the stack to improve the rate capability of the battery. The layers of the battery stack are deposited for instance by chemical and/or physical vapour deposition methods onto the substrate. However, there are limits to the aspect ratio of the trenches or holes to which thin layers can satisfactorily be applied. The aspect ratio is defined as the mean depth of the trench divided by the mean width of the trench. Further, problems due to strain may occur at the highly curved bottom of the trenches, where the volumes of the anode and cathode commonly change upon intercalation of active species during use of the battery stack. This may result in reduced stability and durability of the thin layer battery as a whole.

It is the object of the invention to improve the application of thin layers to three-dimensional substrates.

SUMMARY OF THE INVENTION

The invention provides a substrate for the application of thin layers, comprising at least one via forming a channel from a side of the substrate to another side of the substrate. The application of a thin layer in a via of a three-dimensional substrate according to the invention is much easier and faster to achieve than the application of a thin layer in (blind) trenches or (blind) holes that are only accessible from one side of the substrate. Moreover, since high-curvature regions are no longer present within the substrate according to the invention, problems related to strain are greatly reduced. Products such as thin film battery stacks benefit from this, resulting in an improved performance and durability of these battery stacks. A via is considered as a channel with access entrances on one side of the substrate as well as another side, in particular an opposite side, of the substrate in contrast to trenches and holes that only have an access entrance on one side of the substrate. The vias are preferably substantially linearly to facilitate deposition of thin layers onto the substrate. The via may be oriented either substantially vertically (perpendicularly to the substrate), substantially diagonally (enclosing an angle with the substrate), or otherwise. As another advantage, vias enable the application of thin films to three-dimensional substrates with a larger aspect ratio than achievable with comparable holes and trenches. Improved aspect ratios can be used in low pressure vapour deposition techniques, in particular LPCVD and ALD. Also techniques depositing from a liquid (sol-gel deposition techniques) benefit from the use of vias in the substrate rather than trenches and holes.

Preferably the substrate comprises multiple vias. Thus the advantages of a three-dimensional substrate are optimized, providing a large deposition area which is advantageous in specific thin layer applications such as battery stacks. In a preferred embodiment, the via has an aspect ratio of at least 10. Thus a relatively large inner surface area is provided by the via. Preferably, the via has an aspect ratio larger than 20, more preferably the aspect ratio is larger than 50 In a particular preferred embodiment the via has an aspect ratio larger than 100, more preferably larger than 150 to further increase the contact surface area between different thin layers of a battery stack to be deposited onto the substrate according to the invention to further improve the rate capability of the battery. In this context it is noted that the aspect ratio to be applied is commonly dependent on the technique used to realize the via(s). In case dry etching techniques, such as Reactive Ion Etching (RIE), is used, merely aspect ratios up to about 30 can be realized. In case wet etching techniques are used typically increased aspect ratio up to about 200 can be realized.

In another preferred embodiment, the width of the via is from 50 nm to 1 mm. By means of a dry etching technique, in particular reactive ion etching, a via can be realized having a width falling within the aforementioned range. The channel width of the via to be realized is however commonly dependent on the lithography used. In case a wet etching technique is used commonly vias can be realized having a width from 1 μm to 10 μm. In a particular preferred embodiment the width of the via is from 2 to 10 μm. Such substrates are particularly useful for the application of thin layer battery stacks.

Preferably, the depth of the via is at least 25 μm. Such depths are advantageous in applications such as battery stacks. More preferable, the depth of the via is larger than 100 μm. Compared to conventional 3D substrates with only one entrance to cavities or holes, it is much easier and faster to apply a thin layer to the three-dimensional substrates according to the invention. If the via is a straight channel essentially perpendicular to the first side of the substrate, the depth of the via corresponds to the thickness of the substrate.

It is advantageous if the substrate is mainly made out of silicon, more preferably amorphous silicon. Silicon results in convenient three dimensional substrates according to the invention. . However, it may be clear that also other suitable materials, in particular semiconductor materials, may be applied as substrate, such as for example germanium. It is however expected in practice that the substrate according to the invention will be made substantially of silicon.

In a preferred embodiment, at least one thin layer is applied to the inner surface of the via in the substrate. Such a thin layer is less susceptible to material stress due to a volume change of said thin layer, and hence has an improved layer stability when comparing to the comparable layer applied to a comparable hole or cavity in a conventional 3D substrate comprising one or more blind trenches and/or blind holes.

Preferably, a stack of thin layers is applied to the substrate. With a stack of layers, the improved stability and strain reduction compared to the same stack in a blind hole or blind cavity in a conventional 3D substrate becomes even more pronounced. More preferably, a stack of active thin layers is applied to the substrate. In a particular preferred embodiment a stack of at least an anode, a cathode, and a solid-state electrolyte separating said anode and said cathode is deposited onto the substrate as to form a battery stack.

The invention also provides a thin layer battery stack based on a substrate according to the invention, wherein at least part of the battery stack is applied to the inner surface of the at least via of the substrate. The deposition of different active thin layers of the battery stack into the at least one via of the substrate can be realized relatively easily, as the via will be accessible multilaterally. This facilitates a low-pressure homogeneous deposition of the different thin layers of the battery stack. Moreover, since the vias are commonly substantially linearly, wherein highly curved regions are omitted, an excessive built-up of material stress within the battery stack during use can be prevented, as a result of which deterioration due to cracking of the battery stack can be counteracted, both in short term and in long term. The improved stability is most effective in rechargeable batteries, more in particular lithium- ion batteries, as this kind of battery is commonly subjected to considerable volume changes during charge and discharge cycles. Also, larger aspect ratios are achievable by the vias instead of trenches and holes, thus improving the effective surface area of the battery stack and its performance.

As already mentioned, the application of vias commonly increases the inner surface area of the substrate (compared to the inner surface area being defined by blind cavities according to the prior art), as a result of which the contact surface area between different thin layers of the battery stack deposited onto the substrate will also be increased. This increased contact surface area between different active thin layers of the battery stack commonly improves the rate capability of the battery. In this context it is noted that the effective aspect ratio of the via will be different for each layer of the battery stack. Each time a thin layer is deposited in the via onto the substrate the effective aspect ratio will be increased for the subsequent thin layer to be deposited in the via onto the substrate, or in fact onto the layer deposited lastly.

In a preferred embodiment, the via comprises a free space enclosed by the battery stack. The free space accommodates volume expansion of the battery stack, thus resulting in an improved stability of the battery stack. Volume expansion may occur in particular due to the intercalation of lithium ions in the anode and/or the cathode during charging of a battery.

The invention also relates to a battery pack, comprising multiple battery stacks according to the invention, wherein the battery stacks are mutually connected in series and/or in parallel.

The invention further relates to an electronic device provided with at least one thin layer battery stack according to the invention. An example of such an electric device is a shaver, wherein the electrochemical energy source may function for example as backup (or primary) power source. Other applications which can be enhanced by providing a backup power supply comprising an energy system according to the invention are for example portable RF modules (like e.g. cell phones, radio modules, et cetera), sensors and actuators in (autonomous) micro systems, energy and light management systems, but also digital signal processors and autonomous devices for ambient intelligence. It may be clear this enumeration may certainly not being considered as being limitative. Another example of an electric device wherein a thin layer battery stack according to the invention may be incorporated (or vice versa) is a so-called ' system- in-package' (SiP). In a system-in-package one or multiple electronic components and/or devices, such as integrated circuits (ICs), chips, displays, et cetera, are embeddded at least partially in the substrate, in particuarly a monocrystalline silicon conductive substrate, onto which the thin layer battery stack according to the invention is deposited.

Moreover, the invention provides a method for the manufacture of a substrate according to any of the preceding claims, comprising the steps: the application of a patterned mask to the first side of a substrate, defining the positions of at least one via, and etching of at least part of the via at the positions defined by the mask from the first side of the substrate. The etching may be performed by known etching techniques. The preferred method is dry etching, more preferably reaction ion etching (RIE). After the etching the mask may be removed from the substrate. Preferably, the via is a substantially straight channel. A straight channel is the easiest form to etch. Preferably, the via is essentially perpendicular to the first side of the substrate. However, as already mentioned the vias may also be oriented otherwise, such as for example substantially diagonally (enclosing an angle with the substrate). In case RIE is used as etching technique, the vias will commonly be oriented substantially vertically (substantially perpendicularly to an upper surface of the substrate).

In a preferred embodiment, the via is etched from the first side of the substrate to the opposite side of the substrate. Thus, the via is easily obtained in a straightforward manner. However, it is also conceivable for a person skilled in the art to etch vias which are oriented diagonally with respect to the substrate, provided that the material structure of the substrate allows diagonally oriented etched vias. In this latter case, it is possible that one or more vias extend from one side of the substrate to another side of the substrate, for example an adjacent side, not being the opposite side of the substrate.

In another preferred embodiment at least one via is generated by etching a cavity in the first side of the substrate until the etched cavity reaches a predetermined distance from the opposite side of the substrate, followed by the removal of a material layer from the opposite side of the substrate having a thickness of at least the predetermined distance to generate at least one via. Removal of the backing layer from the opposite side of the substrate can be achieved by means of Chemical Mechanical Polishing (CMP). Commonly, this embodiment of the method according to the invention is advantageous in case relatively deep vias need to be generated. In case relatively shallow vias need to be generated it is commonly preferred to use other techniques, such as dry chemical etching, in particular RIE, or wet chemical etching.

The invention also provides a method for the application of at least one layer to a substrate according the invention, wherein the layer is deposited from a precursor medium that is lead into the via. Thus, a substrate comprising a functional layer or stack of layers, such as a battery stack, is easily achieved. The precursor medium may be of gaseous or liquid form.

In a preferred embodiment, the precursor medium is lead through the via by supplying the precursor medium to the first side of the substrate while applying a relatively high pressure to the first side of the substrate and applying a relatively low pressure to the opposite side of the medium. Thus, the deposition of a layer in the via from the precursor medium is achieved more rapidly. The pressure difference between the two sides of the substrate may be achieved by applying an overpressure (with respect to atmospheric pressure) on the first side and/or applying a underpressure (with respect to atmospheric pressure) on the opposite side of the substrate. Thus, the precursor medium is forced through the vias of the substrate according to the invention. Preferably, the used equipment is provided with means for the medium-tight separation of the first side and the opposite side in order to ensure efficient passing of the precursor medium through the vias. In this context it is noted that the transport of the precursor medium into the via(s) is forced by the pressure difference over said via(s). During curing/annealing of the precursor medium a pressure difference over the via is commonly no longer needed, and may even be undesired. In case ALD or LPCVD is used to generate thin layer(s) in the via(s), it is expected that a pressure difference over the via will commonly affect the deposition process, and hence the thin layer to be generated. Preferably, the layer is applied by a low pressure technique, in particular low pressure chemical vapour deposition or atomic layer deposition. Common equipment for low pressure chemical vapour deposition (LPCVD) or atomic layer deposition (ALD) may be employed.

In a preferred embodiment, a battery stack is deposited onto the substrate. The invention provides a relatively rapid method to manufacture battery stacks on a three- dimensional substrate. The resulting battery stacks circumvent strain-related instability, and may benefit from the use of relatively high aspect ratios of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be elucidated by the following non-restricting examples.

Fig. Ia and Ib show a substrate known in the art and a substrate according to the invention. Fig. 2a-d show a method for the manufacture of substrates according to the invention.

Fig. 3a-3d show another method for the preparation of substrates according to the invention.

Fig. 4a-c show a method for the application of thin layers on a substrate according to the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Figure Ia shows a three dimensional substrate 1 according to the state of the art. The substrate 1 has a blind trench or hole 2 etched into the substrate material 3 that is merely accessible from the top side of the substrate material 3, wherein a rechargeable battery stack is deposited. In this example, the battery stack is a lithium ion battery comprising a lithium diffusion barrier layer 4 which is also the anode current collector, an amorphous silicon anode 5, a solid electrolyte layer 6, a cathode layer 7 and a cathode current collector 8. Due to lithium ion transition between various layers, the volume of the layers change during use and recharging (discharging and charging) of the battery. This causes strain within the trench 2, especially near the curvature 9 on the bottom of the trench or hole 2. Such strain may lead to reduction of the battery performance after repeated use and discharge and charge cycles.

Figure Ib shows a three dimensional substrate 10 according to the invention, comprising a via 11 that spans the substrate material 12 from one side 13 to the opposite side 14. A Battery stack is deposited in the via 11, comparable to figure Ia. The lithium- ion battery stack comprises a lithium diffusion barrier layer 15 which is also the anode current collector, an amorphous silicon anode 16, a solid electrolyte layer 17, a cathode layer 18 and a cathode current collector 19. The form of the via 11 is typically an essentially cylindrical hole, but other forms are also usable. The strain due to lithium ion transition between various layers during use and recharging (discharging and charging) of the battery is greatly diminished when compared to the construction in figure Ia. This results in an improved battery performance in comparison with the battery stack from figure Ia, even after repeated use and discharge and charge cycles. Also, the aspect ratio of the via 11 that can be realized by the use of a substrate 10 according to the invention is (considerably) higher than the maximum aspect ratio achievable for the construction of figure Ia.

Figure 2a shows a silicon substrate 30 upon which a silicon oxide layer 31 was deposited. On top of the silicon oxide layer 31, a patterned mask 32 was deposited using printing or photolithography. In figure 2b, the silicon oxide layer 31 is partially removed according to the pattern mask 32 by wet fluoric acid (HF) etching. Subsequently, in figure 2c the cavities 33 in the silicon substrate 30 are gradually formed by dry etching with Reactive Ion Etching (RIE), until the opposite side of the substrate 30 is reached and a via 34 is obtained that spans the substrate from one side to the opposite side. Finally, the mask 32 and silicon oxide layer 31 are removed, for instance by wet chemical etching, resulting in the three-dimensional substrate 35 shown in figure 2d, comprising vias through the silicon substrate material 30. This method offers a simple way to manufacture a 3D substrate 35 according to the invention.

Figure 3a-3d shows another method for the preparation of substrates according to the invention. Figure 3 a shows a silicon substrate 40 provided with a patterned mask 41 deposited on a silicon oxide layer (not explicitly shown) on the top side, wherein trenches or holes 42 are etched according to the pattern determined by the mask 41. The depth of the trenches 43 is slightly shorter than the thickness 44 of the substrate 40. Subsequently, a layer of substrate 40 is removed from the bottom side 45 by for instance chemical mechanical polishing (CMP) or etching with for instance potassium hydroxide (KOH). The removed thickness is enough to remove the bottom (or backing layer) from the trenches or holes 42, resulting in a substrate with decreased thickness that is provided with vias, as shown in figure 3b.

Figures 3c show an alternative version of the method of figures 3a and 3b. Here, vias 50 in the amorphous silicon substrate 51 are etched by dry etching, restricted by a mask 52 and a support 53 covered with a silicon oxide layer 54. Subsequently, the support 53 and mask are removed, yielding a three-dimensional substrate 55 according to the invention.

Figure 4a shows a substrate 60 comprising a via 61. A precursor medium 63 enters the via 61, depositing a material layer 64 on the inside area 65 of the via 61. Growth of the layer 63 propagates from both sides of the substrate 60 and is continued until a layer of the desired thickness is achieved. The deposition of a complete layer 65 is much faster than the deposition of a comparable layer in a blind cavity such as shown in figure Ia, wherein the precursor medium 63 only has access to the cavity from one side. The precursor medium may be a gas or a liquid. Typically, the precursor in the medium is an organometallic compound, suitable for deposition of a metal or metal oxide layer on the substrate 60.

An alternative method is shown in figure 4b, wherein a substrate 70 comprising a via 71 is subjected to a flow of precursor fluid 72 that is directed through the via 71 by applying a pressure difference between the first side 73 and the opposite side 74. The pressure on the first side 73 should be higher than the pressure on the opposite side 74, which may be achieved by applying an increased pressure on the first side 73, or a reduced pressure (vacuum) on the opposite side 74. The deposition of the layer 75 propagates in the direction of the flow of the precursor fluid 72. Using the methods according to figure 4a or 4b, a battery stack according to figure Ib may be manufactured by using an appropriate precursor medium for each subsequent layer. Typically, the precursor medium is a gas, when using volatile precursors in low pressure chemical vapour deposition (LPCVD) or atomic layer deposition (ALD). Alternatively, liquid precursor mediums including dissolved or dispersed precursors may be used. In a preferred embodiment, the substrate 80 has a battery stack 81 applied to it, but leaves a void channel 82 open in the middle. Such a void channel 82 facilitates volume expansion of the battery stack 81 during use and/or recharging of the battery, resulting in a battery with increased performance and durability.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. Substrate for the application of thin layers, comprising at least one via forming a channel from a side of the substrate to another side of the substrate.

2. Substrate according to claim 1, characterized in that the substrate comprises multiple vias.

3. Substrate according to any of the preceding claims, characterized in that the via has an aspect ratio of at least 10.

4. Substrate according to any of the preceding claims, characterized in that the width of the via is from 2 to 10 μm.

5. Substrate according to any of the preceding claims, characterized in that the depth of the via is at least 25 μm.

6. Substrate according to any of the preceding claims, characterized in that the substrate mainly is mainly made out of silicon.

7. Substrate according to any of the preceding claims, characterized in that at least one thin layer is applied to the inner surface of the via in the substrate.

8. Substrate according to claim 7, characterized in that a stack of thin layers is applied to the substrate.

9. Substrate according to any of the preceding claims, characterized in that the substrate comprises at least one via forming a channel from a side of the substrate to an opposite side of the substrate.

10. Thin layer battery stack based on a substrate according to any of the preceding claims, wherein at least part of the battery stack is applied to the inner surface of the via in the substrate.

11. Thin layer battery stack according to claim 10, characterized in that the via comprises a free space enclosed by the battery stack.

12. Battery pack, comprising multiple battery stacks according claim 10 or 11, wherein the battery stacks are mutually connected.

13. Electronic device provided with at least one thin layer battery stack according to claim 10 or 11.

14. Electronic device according to claim 13, characterized in that the at least one electronic component, in particular an integrated circuit (IC), is at least partially embedded in the substrate.

15. Electronic device according to claim 13 or 14, characterized in that the electronic device and the thin layer battery stack form a System in Package (SiP).

16. Method for the manufacture of a substrate according to any of the preceding claims 1-9, comprising the steps the application of a patterned mask to the first side of a substrate, defining the positions of at least one via, and - the etching of at least part of the via at the positions defined by the mask from the first side of the substrate

17. Method according to claim 16, characterized in that the via is etched from the first side of the substrate to the opposite side of the substrate.

18. Method according to claim 16, characterized in that the via is generated by etching a channel in the first side of the substrate until the etched channel reaches a predetermined distance from the opposite side of the substrate, followed by the removal of a layer of an opposite side of the substrate having a thickness of at least the predetermined distance.

19. Method for the application of at least one layer to a substrate according to any of the claims 1-9, characterized in that the layer is deposited from a precursor medium that is lead into the via.

20. Method according to claim 19, characterized in that the precursor medium is lead through the via by supplying the precursor medium to the first side of the substrate while applying a relatively high pressure to the first side of the substrate and applying a relatively low pressure to the opposite side of the medium.

21. Method according to any of the preceding claims 19 or 20, characterized in that the layer is applied by a low pressure technique, in particular low pressure chemical vapour deposition or atomic layer deposition.

22. Method according any of the preceding claims 19-21, characterized in that a battery stack is applied to the substrate.