WO2008013340A1

WO2008013340A1 - Low power deterministic bist using split lfsr

Info

Publication number: WO2008013340A1
Application number: PCT/KR2006/004847
Authority: WO
Inventors: Sungho Kang; Myung-Hoon Yang; Youbean Kim
Original assignee: Industry Academic Cooperation Foundation of Yonsei University
Current assignee: Industry Academic Cooperation Foundation of Yonsei University
Priority date: 2006-07-27
Filing date: 2006-11-17
Publication date: 2008-01-31
Anticipated expiration: 2009-01-27
Also published as: KR100768549B1

Abstract

A technique of dividing a linear feedback shift register (LFSR) into LFSRs in orde r to reduce power consumption by reducing the number of transitions in a deterministic built-in self test (BIST) for testing a semiconductor device is provided. The determinis tic BIST technique of testing the semiconductor device by applying test patterns to a sc an chain of the semiconductor device includes: dividing a test cube generated by autom atic test pattern generation (ATPG) into a zero-set cube and a one-set cube; generatin g test patterns by combining test patterns generated by the zero-set cube and the one-s et cube; and comparing two generated test pattern values, and if the two test pattern va lues are the same, providing the generated test pattern value to an input of the scan ch ain, and otherwise, I.e. if the two test pattern values are different, providing the previous scan chain input value to an input of the scan chain.

Description

LOW POWER DETERMINISTIC BIST USING SPLIT LFSR

TECHNICAL FIELD

The present invention relates to a technique of splitting a linear feedback shift re gister (LFSR) so as to reduce power consumption by reducing number of transitions in a deterministic built-in self test (BIST) for testing a semiconductor device.

BACKGROUND ART

A built-in self test (BIST) is a logic test for determining whether a circuit is defecti ve. The BIST is a typical technique used in a design for testability (DFT) substituting f or expensive automated test equipment (ATE) and allows at-speed testing. However, since correlation of test patterns that are applied in a test mode is very low as compare d with those in a normal functional mode, a large amount of heat is generated due to an excessive number of transitions. Since heat damages circuits, power concerns are o ne of the most important considerations in the test mode. In case of the BIST in which deterministic test patterns are applied in order to detect defects, which are hardly foun d by using random patterns, unnecessary switching operations are performed since X values (disregarding bits) of the test pattern are filled with random patterns, and therefo re power concerns become further serious.

In the past, a method using double LFSR reseeding has been suggested as a m ethod of reducing power consumption when a deterministic pattern is applied to detect defects. According to the method of using double LFSR reseeding, a main-LFSR gen erates test patterns by using an existing LFSR reseeding, and an additional sub-LFSR generates a mask pattern. Final patterns are generated by performing an OR operatio n or an AND operation with the two LFSR patterns. Accordingly, the number of transiti ons of the patterns that are finally applied to a scan operation can be reduced. Howev er, in this method, an additional LFSR and an additional seed value for generating the mask pattern has to be stored, and the number of transitions of the patterns is reduced by only about 25 %.

A method of using a hold cube has also been suggested and according to this m ethod, each test cube is divided into several blocks, and a hold flag is allocated to each of the blocks. When the hold flag of a block is 1 , a scan input in the corresponding bio ck maintains the last value generated in the previous block. However, in this method, an additional storage space for storing the hold cube is needed and additional hardware for a hold flag shift register is necessary. A low power test method using a scan slice overlapping has been suggested ho wever, a test pattern is divided into several overlapping slice sets, and accordingly trans itions do not occur in an overlapping block. However, in this case, since a change of t he number of overlapping blocks is high, deviations of a reduction of the number of swit ching operations increases.

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL PROBLEM

The present invention provides a new linear feedback shift register (LFSR) resee ding method using split LFSRs capable of reducing the number of transitions in a scan chain by researching a structure capable of generating low power patterns even when d eterministic patterns are applied, in relation with a scan operation in which power is larg ely consumed.

The present invention also provides a low power and deterministic built-in self te st (BIST) method of testing a semiconductor device capable of reducing power consum ption by reducing the number of transitions in a scan chain by dividing the LFSR into tw o LFSRs and using the two LFSRs and a device therefor.

TECHNICAL SOLUTION

According to an aspect of the present invention, there is provided a deterministic built-in self test (BIST) method of testing a semiconductor device by applying a test patt ern in a scan chain of the semiconductor device, the method comprising: dividing a test cube generated by automatic test pattern generation (ATPG) into a zero-set cube and a one-set cube; generating test patterns by combining test patterns generated by the zer o-set cube and the one-set cube; and comparing two generated test pattern values, and if the two test pattern values are the same, providing the generated test pattern value t o an input of the scan chain, and otherwise, I.e. if the two test pattern values are differe nt, providing the previous scan chain input value to an input of the scan chain.

The method may further comprise initially removing defects by applying pseudo-r andom patterns to the scan chain before dividing the test cube.

When the test pattern values generated in the generating of the test patterns are different from each other, the previous scan chain input value is inverted and applied t o the scan chain. The above-described method can be implemented as a computer readable progr am, and thus a computer readable recording medium having embodied thereon the co mputer program is also within the scope of the present invention.

According to another aspect of the present invention, there is provided a low pow er and deterministic built-in self test (BIST) device for testing a semiconductor device by applying a test pattern in a scan chain of the semiconductor device, the device compri sing: a first unit dividing a test cube generated by automatic test pattern generation (AT

PG) into a zero-set cube and a one-set cube; a second unit generating test patterns by combining test patterns generated by t he zero-set cube and the one-set cube; and a third unit comparing two generated test p attern values and, if the two test pattern values are the same, providing the generated t est pattern value to an input of the scan chain, and otherwise, I.e. if the two test pattern values are different, providing the previous scan chain input value to an input of the sea n chain.

The first unit may include a linear feedback shift register (LFSR) for the zero-set cube and an LFSR for the one-set cube.

The third unit may include a selecting unit inputting the generated test pattern val ue as an input of the scan chain when the test pattern values are the same, and inputtin g the previous scan chain input value as an input of the scan chain when the test patter n values are different from each other. In the BIST method according to an embodiment of the present invention and th e device therefor, two split LFSRs are used to generate test patterns. Each LFSR gen erates a zero-set cube which is constructed by bits of 0 in the original test cube and a o ne-set cube which is constructed by 1 bits in the original test cube, respectively. Accor dingly, the 1 bits generated in the LFSR for the zero-set cube and the bits of 0 generate d in the LFSR for the one-set cube have X values (don't care bits). The X values allow the final input values to be maintained, thereby reducing the number of transitions in th e scan chain. As the experiment result of applying the present invention to the ISCAS circuits, the BIST according to an embodiment of the present invention can reduce the switching operations in the scan chain by 50 %.

ADVANTAGEOUS EFFECTS According to an embodiment of the present invention, when a circuit is tested by applying a deterministic pattern using the BIST technique, power consumption due to th e applied patterns is low, and therefore, a safe and low power test can be performed on the circuit. In addition, since it is possible to supply one module, which is combined w ith software for automatically generating the structure according to an embodiment of th e present invention, in CAD related fields, an economic effect due to single item can be achieved. It is possible to create profits due to the technology transfer such as insertio n of the corresponding algorithm into the existing BIST generation tool.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view illustrating a built-in self test (BIST) device;

FIG. 2 illustrates an algorithm source for generating low power patterns and modi fied patterns; and

FIG. 3 illustrates a flowchart of an encoding method according to an embodiment of the present invention.

BEST MODE

A built-in self test (BIST) structure using split linear feedback shift register s (LFSRs) Hereinafter, the BIST structure for applying the aforementioned low power and d eterministic patterns will be described. In FIG. 1 , a hardware architecture according to an embodiment of the present invention is illustrated. By comparing the hardware arc hitecture with an existing reseeding hardware structure, two XOR logic gates 30 and 30' , a multiplexer (MUX) 40, and a modified pattern decoder 50 are additionally used for th e hardware architecture. In addition, in the present invention, an LFSR is divided into an LFSR 10 for a zero-set cube and an LFSR 20 for a one-set cube. The split test cub e has a less number of specific bits than an original test cube. Accordingly, the length of each LFSR is less than that of an existing LFSR. Accordingly, even when two LFSR s are used, the total size of the LFSR is the same as that of the existing LFSR. When a deterministic pattern is applied, it is determined by using the XOR gate 30 whether th e two LFSR outputs are the same. When the two LFSR outputs are the same, the LF SR output is selected by using the MUX 40. When the two LFSR outputs are different from each other, a previous scan input value is selected by the MUX 40. When the pr evious scan input value is selected, since if a modified pattern value is 1 , the previous s can input value has to be inverted, the XOR 30 operation is performed with respect to t he previous scan input value and the modified pattern value. The output of the XOR o peration is applied to a scan chain through MUX 40.

Mechanism of reducing the number of transitions of the pattern applied to a scan operation

In the existing LFSR reseeding method, a seed value is obtained by solving a Nn ear equation obtained from a characteristic polynomial of the LFSR with respect to a giv en test cube. The LFSR generates all the specific bits except of X values of the test c ube by using the seed value. The X values are filled with pseudo random patterns gen erated by the LFSR. The X values that are filled with pseudo random patterns generat ed by the LFSR cause unnecessary transitions in a scan chain. Accordingly, in order t o minimize the number of transitions in a test pattern, X values have to be filled with suit able values.

Given a signal S, P-ι(S) represents a probability that the signal S is 1. P₀(S) repr esents a probability that the signal S is 0. When it is assumed that the signal S is a ra ndom pattern generated by the LFSR, P₀(S) + Pi(S) = 1 , and P₀(S) = P₁(S) = 0.5. In th is case, a transition probability P_tr(S) of the signal S represents a probability that a curre nt value of the signal S is different from its previous value. The transition probability P_tr (S) of the signal S can be computed as P_tr(S) = P₀(S) x P-i(S) + P₀(S) x Pi(S) = 0.5 x 0. 5 + 0.5 x 0.5 = 0.5.

In order to reduce the number of transitions in the test pattern, the transition prob ability P_tr(S) of the signal S has to be reduced. When the values that are previously in put into the scan chain can replace all the X values of the test pattern, the transition pro bability P_tr(S) of the test pattern can be reduced to a minimum. For example, in the tes t cube, when it is assumed that the probability that the values of the test pattern are not the X values is 5 %, the probability that the values of the test pattern are 0 is 50 %, and the probability that the values of the test pattern are 1 is 50 %, the transition probability P_tr(S) of the test pattern is 2.5 %. However, if the previous input values can replace th e X values as much as possible, the transition probability Ptr(S) of the test pattern can b e considerably reduced, thereby reducing the number of switching operations. When it is assumed that C=(C₀ c_m--ι)<≡{0,1 ,X}^m is a deterministic test cube C, S

(C)={i|Cj≠X} is a specific bit set of the deterministic test cube C, S(C) can be divided into a zero-set cube and a one-set cube. In this case, when So(C)={i|Ci=O} is the zero-set cube, and Si(C)={i|Ci=1} is the one-set cube, an initial seed for generating the determini stic test cube C can be obtained by solving a known linear equation. An initial seed for generating the zero-set cube and the one-set cube can also be obtained through the s ame procedures. All 1 bits in the pattern generated through the zero-set cube and all 0 bits in the pattern generated through the one-set cube are X values with respect to ea ch cube.

Table 1 is a table for comparing patterns generated from the zero-set cube and t he one-set cube. Table 1 represents the values generated through the LFSR for the z ero-set cube and the one-set cube and values of an original test cube corresponding to the generated values. O_x and 1_X at first and second columns represent a 0 or 1 bit in w hich X values of the zero-set and one-set cubes are filled with the values generated in e ach LFSR. Similarly, 0_s and 1_S represent a 0 or 1 bit in which specific bit values of the zero-set and one-set cubes are filled with the values generated in each LFSR. Accordi ng to the definition of the zero-set and one-set cubes, two LFSRs cannot generate 0_s a nd 1_S at the same time. [Table 1 ]

Referring to Table 1 , when the values of the zero-set cube pattern and the one-s et cube pattern are all 0, the value of the original test cube is 0 or X. Accordingly, in thi s case, when value of 0 is used as the scan input value, the original test cube value can be compatible with the original test cube. Similarly, when the values of the zero-set c ube pattern and the one-set cube pattern are 1 , the value of the original test cube is 1 o r X. Accordingly, the value of 1 can be used as the scan input value. When the value of 1 is generated in the zero-set cube, the value of 0 is generated in the one-set cube and the value of the original test cube is X. Accordingly, in this case, when the previou s input value is used as the scan input value, the transition does not occur in the scan c hain. Finally, when the zero-set cube generates 0 and the one-set cube generates 1 , t he value of the original test cube may be 0, 1 , or X. Accordingly, like the aforemention ed case, when the previous scan input value is used, the previous scan input value may incompatible with the value of the original test cube. In this case, additional informati on is necessary so that the previous scan input value may be compatible with the value of the original test cube. That is, when the previous scan input value is inverted and u sed at the incompatible location, the value of the original test cube can be accurately ap plied. In general, since the ratio of the X values in the test cube is very high, the frequ ency of the aforementioned modifications is not high. Practically, a ratio of large circuit s among ISCAS circuits which need the aforementioned modification are equal to or les s than 2 %. Accordingly, when the aforementioned cases are neglected, the transition s occur only when the values of the patterns generated in the two LFSRs are the same.

Even in this case, since the transitions occur only when the generated values are diff erent from the previous scan input values, the transition probability is 25 %. As such, t he transition probability is reduced by 50 % as compared with the case using one LFSR

Encoding algorithm

In the present embodiment, an encoding method suggested in the present invent ion in order to reduce the number of transitions in the test pattern will be described. A n algorithm source, which generates low power patterns and modified patterns by using the structure of the BIST device of FIG. 1 , is illustrated in FIG. 2. In FIG. 2, C is a test cube generated by automatic test pattern generation (ATPG). C[i] represents the i-th value of C. C is divided into a zero-set cube C₀ and a one-set cube Ci. Patterns Po a nd Pi are generated by the LFSR for generating a zero-set cube and a one-set cube. P₀[I] and P₁[J] represent i-th values of the patterns P₀ and P₁.

FIG. 3 illustrates a flowchart of the encoding method of FIG. 2. First, in order to easily remove detectable defects, pseudo-random patterns are applied (operation 102). Then, in order to detect the rest of the defects, which are not detected by the pseudo-random patterns, ATPG is performed to generate deterministic patterns in the form of test cubes (operation 104). Each test cube generated by the A TPG is divided into zero-set and one-set cubes C₀ and Ci (operation 106). Initial seed values with respect to the divided test cubes are calculated by the existing LFSR resee ding method (operations 108 and 110). The low power test pattern Pι_[i] generated by t he split LFSR in the present invention is obtained by combining the test patterns genera ted by the two divided test cubes (operations 112 and 114).

Next, the values of the zero-set and one-set cubes generated in each LFSR are compared with each other (operation 116). When the generated values are the same, a value is used as an input value of a scan chain (operation 120). When the generate d values are different from each other, previous scan chain input values are used as the input value of the scan chain (operation 122). As described above, when the two LF

SR outputs are different, the previous scan input value may be incompatible with a valu e of an original test cube. Therefore, when the previous scan input value is incompatib

Ie with the value of the original test cube, the previous scan input value has to be invert ed and used. Then, the value of the modified pattern P_c[i] is 1. That is, when the val ue of the modified pattern Pc[i] is 0, the previous scan input value is applied to the scan chain without change. When the value of the modified pattern Pc[i] is 1 , the previous scan input value is inverted and applied to the scan chain.

A computer program can perform the aforementioned method. The invention c an also be embodied as a computer program on a computer readable recording mediu m. The computer readable recording medium is any data storage device that can stor e data that can be thereafter read by a computer system. Examples of the computer r eadable recording medium include read-only memory (ROM), random-access memory ( RAM), CD-ROMs, magnetic tapes, floppy disks, optical data storage devices, and carrie r waves (such as data transmission through the Internet). Performance of the BIST according to an embodiment of the present invent ion

An experiment for examining efficiency of the BIST method according to an emb odiment of the present invention is performed with respect to the largest circuits from a mong ISCAS '89 benchmark circuits. First, 10,000 pseudo-random patterns are applie d, and easily detectable defects are removed. Then, ATPG is performed on the rest of the defects to generate deterministic test patterns in order to achieve a 100 % defect d etection rate.

Table 2 represents the number of transitions of the patterns generated by using t he existing LFSR reseeding method and the number of transitions of the low power patt erns generated by the method according to an embodiment of the present invention, as an experiment result of the split LFSR structure using ISCAS '89 benchmark circuits. As known from Table 2, the number of transitions is reduced by about 50 % with respec t to all the circuits.

[Table 2]

Claims

1. A deterministic built-in self test (BIST) method of testing a semiconductor device by applying a test pattern in a scan chain of the semiconductor device, the method com prising: dividing a test cube generated by automatic test pattern generation (ATPG) into a zero-set cube and a one-set cube; generating test patterns by combining test patterns generated by the zero-set cu be and the one-set cube; and comparing two generated test pattern values, and if the two test pattern values ar e the same, providing the generated test pattern value to an input of the scan chain, an d otherwise, I.e. if the two test pattern values are different, providing the previous scan chain input value to an input of the scan chain

2

The method of claim 1 , further comprising initially removing defects by applying p seudo-random patterns to the scan chain before dividing the test cube.

3.

The method of claim 1 , wherein when the generated test pattern values generate d in the generating of the test patterns are different from each other, the previous scan i nput value is inverted and applied to the scan chain.

4.

A computer recording medium having embodied thereon a computer program for executing the method of any one of claims 1 to 3.

5.

A low power and deterministic built-in self test (BIST) device for testing a semico nductor device by applying a test pattern in a scan chain of the semiconductor device, t he device comprising: a first unit dividing a test cube generated by automatic test pattern generation (A TPG) into a zero-set cube and a one-set cube; a second unit generating test patterns by combining test patterns generated by t he zero-set cube and the one-set cube; and a third unit comparing two generated test pattern values, and if the two test patte rn values are the same, providing the generated test pattern value to an input of the sea n chain, and otherwise, I.e. if the two test pattern values are different, providing the prev ious scan chain input value to an input of the scan chain.

6.

The device of claim 5, wherein the first unit includes a linear feedback shift regist er (LFSR) for the zero-set cube and an LFSR for the one-set cube.

7. The device of claim 5, wherein the third unit includes a selecting unit inputting th e generated test pattern value as an input of the scan chain when the test pattern value s are the same and inputting the previous scan chain input value as an input of the sea n chain when the test pattern values are different from each other.