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WO2008011441A3 - Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory - Google Patents

Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory Download PDF

Info

Publication number
WO2008011441A3
WO2008011441A3 PCT/US2007/073741 US2007073741W WO2008011441A3 WO 2008011441 A3 WO2008011441 A3 WO 2008011441A3 US 2007073741 W US2007073741 W US 2007073741W WO 2008011441 A3 WO2008011441 A3 WO 2008011441A3
Authority
WO
WIPO (PCT)
Prior art keywords
adjacent
coupling
memory cell
nonvolatile memory
storage elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/073741
Other languages
French (fr)
Other versions
WO2008011441A2 (en
Inventor
Yan Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/458,995 external-priority patent/US7495953B2/en
Priority claimed from US11/458,996 external-priority patent/US7506113B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of WO2008011441A2 publication Critical patent/WO2008011441A2/en
Publication of WO2008011441A3 publication Critical patent/WO2008011441A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
PCT/US2007/073741 2006-07-20 2007-07-18 Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory Ceased WO2008011441A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/458,995 2006-07-20
US11/458,995 US7495953B2 (en) 2006-07-20 2006-07-20 System for configuring compensation
US11/458,996 US7506113B2 (en) 2006-07-20 2006-07-20 Method for configuring compensation
US11/458,996 2006-07-20

Publications (2)

Publication Number Publication Date
WO2008011441A2 WO2008011441A2 (en) 2008-01-24
WO2008011441A3 true WO2008011441A3 (en) 2008-07-17

Family

ID=38957572

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/073741 Ceased WO2008011441A2 (en) 2006-07-20 2007-07-18 Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory

Country Status (2)

Country Link
TW (1) TWI355663B (en)
WO (1) WO2008011441A2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721703A (en) * 1996-04-29 1998-02-24 Micron Technology, Inc. Reprogrammable option select circuit
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6044004A (en) * 1998-12-22 2000-03-28 Stmicroelectronics, Inc. Memory integrated circuit for storing digital and analog data and method
US6522580B2 (en) * 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US20040057285A1 (en) * 2002-09-24 2004-03-25 Sandisk Corporation Non-volatile memory and method with reduced neighboring field errors
US20050057965A1 (en) * 2003-09-17 2005-03-17 Raul-Adrian Cernea Non-volatile memory and method with bit line coupled compensation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721703A (en) * 1996-04-29 1998-02-24 Micron Technology, Inc. Reprogrammable option select circuit
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6044004A (en) * 1998-12-22 2000-03-28 Stmicroelectronics, Inc. Memory integrated circuit for storing digital and analog data and method
US6522580B2 (en) * 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US20040057285A1 (en) * 2002-09-24 2004-03-25 Sandisk Corporation Non-volatile memory and method with reduced neighboring field errors
US20050057965A1 (en) * 2003-09-17 2005-03-17 Raul-Adrian Cernea Non-volatile memory and method with bit line coupled compensation

Also Published As

Publication number Publication date
WO2008011441A2 (en) 2008-01-24
TWI355663B (en) 2012-01-01
TW200823904A (en) 2008-06-01

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