WO2008010148A1

WO2008010148A1 - Trench field effect transistors

Info

Publication number: WO2008010148A1
Application number: PCT/IB2007/052729
Authority: WO
Inventors: Ed Huang
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2006-07-14
Filing date: 2007-07-10
Publication date: 2008-01-24
Anticipated expiration: 2009-01-14

Abstract

A trench FET structure includes insulated gate trenches (22) defining mesas (18) between the insulated gate trenches (22). The mesas include source diffusions (8) at the surface adjacent to the trenches (22), leaving regions between the source diffusions at the centre of the mesas (18) where the body diffusion (6) is present at the surface. Trench protrusions (24) extend into the mesas (18), so that the trench protrusions (24) alternate with the regions of the mesas (18) where the body diffusions (6) are present at the surface along the mesas.

Description

DESCRIPTION

TRENCH FIELD EFFECT TRANSISTORS

The invention relates to Trench gated Field Effect Transistors (Trench

FETs) and to methods of making them.

Trench FETs have a number of applications for both high and low voltages. Trench FETs are commonly used, for example in voltage regulator modules (VRMs) in power supplies for electronic equipment such as personal computers.

An approach to trench FET design according to related art is shown in Figures 1 and 2.

Referring to Figure 2, a substrate is heavily doped n+ to provide a highly doped drain region 2, and a low doped drain region 4 doped n-type is provided on top. A p-type body region 6 is provided on the drain region, and a n+ doped source region 8 is provided on top of the body region.

Insulated trenches 10 define mesas 18 between the trenches. The trenches are filled with a gate 16 insulated from the body region 6 and low doped drain region 4 by gate insulator 12,14.

Both the n-type source region 8 adjacent to the trenches 10 and the p- type body region 6 are exposed at the surface, in order that a source electrode can connect to the body region 6 as well as the source region 8, as illustrated in Figure 1. Note that in Figure 1 the gate insulator and gate electrode are omitted for clarity.

In operation, voltage applied to the gate creates a channel adjacent to the trench between source and drain through the body region.

In the specific arrangement shown disclosed, the trenches 10 are each filled with a plug 12 at the base of the trench and a gate 16 above the plug. The gate 16 is insulated from the body region 6 with gate insulator 14 on the sidewalls of the trenches. The body region 6 and source region 8 are both exposed on first major surface 20 of the semiconductor device. One important parameter for MOSFETs is the specific on-resistance, Rdson, i.e. the resistance of the transistor for a given unit active area in the on- state. It is desirable to reduce this value.

Another useful parameter is the gate-drain charge density Qg_d, which contributes to switching losses, and needs to be kept low for this and other reasons.

There is a trade-off between these two parameters. To a first approximation, the product Rdson-Qgd is fixed for a given technology (cell pitch, trench width, pattern of layers etc.), but the product differs for different technologies. Thus, the product can be used as a figure of merit of the technology.

A further important parameter is the current carrying capacity per unit area; it is desirable to increase this.

To reduce the specific on-resistance in MOSFET structures it is usual to use thin trench widths to achieve a small cell pitch, for example 1 μm, to increase the number of channels per unit width and hence to decrease the resistance in the on state. Even smaller cell pitches are possible, for example using deep ultra-violet processing techniques.

However, a problem of using this approach is that it provides an undesirable rise in the gate resistance. Long lengths of very narrow gate require a number of connections using additional gate busbars to avoid the gate resistance being too high.

A still further problem is that the connection to both source 8 and body 6 is very difficult when the mesa width is narrow. A known approach is described in US 2005/0006700. This targets a low on-resistance using a transistor structure in which the trenches follow a "serpentine" path, i.e. the trenches are not straight. This allows the trenches to be closer in some regions than others.

According to the invention there is provided an insulated gate semiconductor device having a first major surface, comprising: a plurality of gate trenches across the first major surface; gate insulator on the sidewalls of the trenches; a conductive gate in the trenches; source regions of first conductivity type adjacent to the trenches at the first major surface; and body regions of second conductivity type opposite to the first conductivity type exposed at the first major surface between the source regions; wherein the trenches are shaped to have a plurality of first trench regions extending across the first major surface and a plurality of second trench regions extending as protrusions from the first trench regions laterally from the first trench regions across the first major surface between the first trench regions.

By providing protruding second trench regions extending from the first trench regions a much greater increase in channel width is achieved than using the "serpentine" path of US 2005/0006700. Accordingly, the device according to the invention can deliver improved current carrying capacity.

In preferred embodiments, adjacent first trench regions extend longitudinally across the first major surface defining mesa regions between adjacent first trench regions, longitudinally aligned pairs of aligned protrusions extend laterally into the mesa regions from the adjacent first trench regions, and the body regions alternate longitudinally with the pairs of aligned protrusions longitudinally along the mesa regions.

The body regions of adjacent mesa regions may be longitudinally aligned. Alternatively, the body regions of adjacent mesa regions may be longitudinally offset. This can distribute the body regions more evenly over the first major surface, which can deliver benefits in terms of improved avalanche breakdown ruggedness.

The invention also relates to a method of making a semiconductor device having a first major surface, comprising: defining body regions at the first major surface; defining source regions of a first conductivity type opposite to the second conductivity type of the body regions at the first major surface leaving part of the body regions exposed at the first major surface; and etching a plurality of gate trenches across the first major surface either before or after defining the body regions and source regions; forming gate insulator on the sidewalls of the trenches; forming a conductive gate in the trenches; wherein the source regions are patterned to run alongside the trenches; and the trenches are patterned to have a plurality of first trench regions extending across the first major surface and a plurality of second trench regions extending as protrusions from the first trench regions laterally from the first trench regions across the first major surface between the first trench regions.

For a better understanding of the invention, embodiments will now be described, purely by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows a top view of a prior art trench structure in side view; Figure 2 shows a side view of a semiconductor device according to the prior art and also represents a side view across section A-A shown in Figure 3 of a first embodiment of the invention;

Figure 3 shows a top view of the trench structure of a semiconductor device according to the first embodiment of the invention; Figure 4 shows a side view of the semiconductor device of Figure 3 across section B-B; and

Figure 5 shows a top view of a trench structure of a semiconductor device according to a second embodiment of the invention.

The first embodiment of the invention is illustrated in top view in Figure

3. The section across line A-A of the first embodiment is the same as the cross section of the related art shown in Figure 2. The invention differs in the pattern of trenches and regions, and accordingly the section across line B-B differs from the prior art and is illustrated in Figure 4.

Referring to the top view of Figure 3, the trenches 10 of the first embodiment of the invention have first longitudinal trench regions 22 which extend longitudinally across the first major surface, and a number of second trench regions in the form of protrusions 24 which extend laterally from the first trench regions 22.

The first longitudinal trench regions 22 define mesa regions 18 which extend longitudinally between the trench regions 22 and which include source regions 8 and body regions 6.

The protrusions 24 extending into the mesa regions on both sides of the mesa are aligned to form pairs 26. The body regions 6 are absent on the surface adjacent to the protrusions 24. Thus, moving longitudinally along the surface of the mesa regions 18, the pairs 26 of protrusions 24 alternate with the body regions 6. The source region 8 is present at the surface along the full length of the mesa regions 18.

In this embodiment, the pairs 26 of protrusions 24 are also aligned in adjacent mesa regions 18.

The term "channel width" will be used for the extent of the channel, since this is conventional in the art, even though the channel and hence the "width" extends along the edge of the gate trench which extends longitudinally in Figure 1.

In the Figure 1 arrangement, assuming that the trenches have a width W and length L, the total channel width of a trench is 2L since there is a channel on each side of the trench. The trench area is LW, so the ratio of channel width to trench area is 2L/LW = 2/W.

Turning now to Figure 3, assume that each first trench region 22 has a width W and length L as in Figure 1. Assuming that each protrusion 24 has a lateral length S and the same width W as the first trench region 22 then the total channel width is increased by 2S for each protrusion in the arrangement of Figure 3 compared with the arrangement of Figure 1. The arrangement thus achieves a significantly increased channel width. The increase in area for each protrusion is SW. Thus, the ratio of increase in channel width to increase in trench area is 2S/SW=2/W.

The value of the specific on-resistance is inversely proportional to the channel width and the gate-drain charge is proportional to the area of the trench, to a first approximation. Accordingly, the figure of merit of the product of the specific on-resistance and the gate-drain charge is proportional to the ratio of channel width to trench area. Since this ratio is 2/W both for the original structure and for the increase in the arrangement of Figure 3, the figure of merit is the same to a first order approximation in Figures 1 and 3. Thus, the arrangement of Figure 3 achieves an improvement in channel width, and hence greater current carrying capacity per unit area, without impairing the figure of merit at all.

The process can be carried out on a variety of existing processes which will determine the available sizes of trench width. Assume an existing process with a minimum trench width of 0.5 μm, a minimum cell pitch of 2.5 μm and a contact window size of 1.0 μm. In this case, assuming that the minimum gap between opposed source protrusions 24 is also 0.5 μm a very substantial increase in channel width per unit area of 60% is possible using the arrangement of Figure 3 over that of Figure 1. Even greater improvements are possible with smaller and smaller cell pitches. Thus, the arrangement of Figure 3 gives very considerable benefits.

Figure 5 illustrates an alternative arrangement in which even though the protrusions 24 extending into each mesa region 18 are aligned, the protrusions extending into adjacent mesa regions from each of the first longitudinal trench regions 22 are not aligned, and extend alternately from the first longitudinal trench regions 22 on either side of the first longitudinal trench regions.

In this arrangement, the body regions 6 are arranged more evenly over the surface. This can improve the uniformity of the MOSFET and help increase avalanche ruggedness over the arrangement of Figure 3. In this context, the term "ruggedness" is used to denote the capability of the MOSFET to withstand (not fail in the face of, hence "rugged") reverse avalanche energy. Note that generally the trenches will be the same width in the first trench regions 22 and protrusions 24. However, this is not an essential feature and it is possible for the trench widths to vary, as indeed is illustrated in Figure 5.

Although the embodiments include the protrusions on linear trenches extending longitudinally across the first major surface 20, the invention also envisages providing protrusions on other shaped trenches, for example hexagonal trench structures or other trench structures.

Further, the invention can apply to other types of semiconductor device with trenches, including in particular vertical DMOS as well as a Trench MOS structure. Any suitable transistor structure can be used - for example the low doped drain region 4 is optional and can be omitted if not required.

The invention is equally applicable to p-type and n-type structures.

Claims

1. An insulated gate semiconductor device having a first major surface, comprising: a plurality of trenches (10) across the first major surface (20); gate insulator (14) on the sidewalls of the trenches (10); a conductive gate (16) in the trenches (10); source regions (8) of first conductivity type adjacent to the trenches (10) at the first major surface (20); and body regions (6) of second conductivity type opposite to the first conductivity type exposed at the first major surface (20) between the source regions (8); wherein the trenches (10) are shaped to have a plurality of first trench regions (22) extending across the first major surface (20) and a plurality of second trench regions extending as protrusions (24) from the first trench regions laterally from the first trench regions (22) across the first major surface between the first trench regions (22).

2. A semiconductor device according to claim 1 , wherein adjacent first trench regions (22) extend longitudinally across the first major surface defining mesa regions (18) between adjacent first trench regions (22), longitudinally aligned pairs (26) of aligned protrusions (24) extend laterally into the mesa regions (18) from the adjacent first trench regions, and the body regions (6) alternate longitudinally with the pairs (26) of aligned protrusions (24) longitudinally along the mesa regions (18).

3. A semiconductor device according to claim 2, wherein the body regions (6) of adjacent mesa regions (18) are longitudinally aligned.

4. A semiconductor device according to claim 2, wherein the body regions (6) of adjacent mesa regions (18) are longitudinally offset.

5. A method of making an insulated gate semiconductor device, comprising: defining body regions (6) at a first major surface (20); defining source regions (8) of a first conductivity type opposite to the second conductivity type of the body regions (6) at the first major surface (20) leaving part of the body regions (6) exposed at the first major surface (20); etching a plurality of trenches (10) across the first major surface (20) either before or after defining the body regions and source regions; forming gate insulator (14) on the sidewalls of the trenches; forming a conductive gate (16) in the trenches; wherein the source regions (8) are patterned to run alongside the trenches (10); and the trenches (10) are patterned to have a plurality of first trench regions

(22) extending across the first major surface (20) and a plurality of second trench regions extending as protrusions (24) from the first trench regions (22) laterally from the first trench regions across the first major surface (20) between the first trench regions (22).

6. A method according to claim 5 including patterning the trenches to have adjacent first trench regions (22) extending longitudinally across the first major surface (20) defining mesa regions (18) between adjacent first trench regions (22), longitudinally aligned pairs (26) of aligned protrusions (24) extending laterally into the mesa regions (18) from the adjacent first trench regions, and the body regions (6) alternate longitudinally with the pairs of aligned protrusions (24) longitudinally along the mesa regions (18).