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WO2008000193A1 - An exchange system and method for increasing exchange bandwidth - Google Patents

An exchange system and method for increasing exchange bandwidth Download PDF

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Publication number
WO2008000193A1
WO2008000193A1 PCT/CN2007/070169 CN2007070169W WO2008000193A1 WO 2008000193 A1 WO2008000193 A1 WO 2008000193A1 CN 2007070169 W CN2007070169 W CN 2007070169W WO 2008000193 A1 WO2008000193 A1 WO 2008000193A1
Authority
WO
WIPO (PCT)
Prior art keywords
boards
node
board
switching
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2007/070169
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English (en)
French (fr)
Inventor
Feng Hong
Cheng Chen
Rong Fan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to JP2009515690A priority Critical patent/JP4843087B2/ja
Priority to ES07764119T priority patent/ES2392880T3/es
Priority to EP20070764119 priority patent/EP1981206B1/en
Priority to CNB2007800001784A priority patent/CN100561925C/zh
Publication of WO2008000193A1 publication Critical patent/WO2008000193A1/zh
Priority to US12/181,617 priority patent/US20080279094A1/en
Anticipated expiration legal-status Critical
Priority to US13/965,187 priority patent/US20130343177A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/45—Arrangements for providing or supporting expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections

Definitions

  • the present invention relates to the field of communications, and more particularly to a switching system and method that is compatible with the ATCA/ATCA300 architecture to increase switching bandwidth.
  • ATCA Advanced Telecommunications Computing Architecture
  • PICMG PCI Industrial Computer Manufacturers Group
  • ATCA is an open industry standard architecture developed and developed by PICMG (PCI Industrial Computer Manufacturers Group). It is positioned as a common hardware platform technology for communication devices and computing servers. This includes specifications for chassis structure, power supply, cooling, board structure, backplane interconnect topology, system management, and switching network recommendations.
  • ATCA is suitable for 600mm deep machine rejection.
  • PICMG has also developed the ATCA300 platform architecture standard, and ATCA and ATCA300 are compatible with the backplane.
  • the ATCA is an intermediate backplane and a front and rear plug-in board structure.
  • the Hub Board and the Node Board are both front boards.
  • the node boards are connected by Full Mesh or interconnected through a switch board.
  • ATCA supports up to 16 slots (21-inch machine rejection) and 14 slots in 19-inch machine rejection.
  • Each slot of the ATCA is divided into three areas: Zone 1 (Zone 1), Zone 2 (Zone 2), and Zone 3 (Zone 3).
  • Zone 1 is the power supply and management interconnection area
  • Zone 3 is the front board and the corresponding board.
  • Zone 2 is the interconnection area between the node boards (Full Mesh topology) or between the node board and the switch board (double star switching network interconnection).
  • ATCA supports up to 16 node boards; if you use a dual-star structure switching network interconnection, ATCA supports up to 14 node boards and 2 switching boards, each of which needs to be combined with another 15 The boards (14 node boards and 1 switch board) are interconnected; if dual-double-chain structure switching network interconnection is used, ATCA supports up to 12 node boards and 4 switching boards, each of which needs to be connected with another 15 The boards (12 node boards and 3 switch boards) are interconnected.
  • PICMG 3.0 defines the switching interconnect topology for three switching interfaces, Full Mesh, Dual Fabric Star, and Dual Dual Fabric Star.
  • switch interconnect topologies in a system configuration of 16 slots or 14 slots, two The interconnection between the gang boards provides eight pairs of differential signals (transmitting 4 pairs of differential signals and receiving 4 pairs of differential signals).
  • the physical link working rate of the switching interconnect technology is mainly 2.5 Gb/s, 3.125 Gb/s, 5 Gb/s, and 6.25 Gb/s.
  • the fully interconnected topology is directly interconnected between all of the node boards 11 ( Figure 1 shows the full interconnect structure for an eight-node board configuration).
  • PICMG 3.0 supports up to 16 node boards for full interconnection.
  • the communication bandwidth between the two node boards is only 20 Gb/s.
  • the cost of implementing 16-node boards full interconnection is very high.
  • the full interconnection is only used for system interconnection of less than 8 nodes, and cannot meet the requirements of larger capacity equipment.
  • the node board 21 is interconnected with the switch board section 22, and the communication between the node boards 21 is performed through the switch board node.
  • PICMG 3.0 stipulates that the two switching networks work as the primary backup mode (PICMG 3.0 Specification, Page 294, Section 6.2).
  • PICMG 3.0 Specification, Page 294, Section 6.2.
  • the primary backup operation only the primary switching board can perform the switching function, and the standby switching board does not perform the switching function;
  • the switch board can perform the switching function, but the LUN board only receives the data of the main switch board and does not receive the data of the standby switch board. Therefore, in the dual-star interconnect topology, even with a physical link rate of 6.25 Gb/s, the node board can only provide 20 Gb/s of bandwidth and can only provide one 10 Gb/s line rate user interface.
  • the dual-chain switching interconnect topology is similar to the dual-star switching interconnect topology.
  • the number of switching board nodes is increased from two to four (logical slots are 1, 2, 3, 4), and up to 12 node boards are configured.
  • the logical slots are 5 ⁇ 16 ).
  • the node boards are interconnected with the switch board nodes. The communication between the node boards is performed through the switch board nodes.
  • PICMG 3.0 stipulates that four switch boards are two independent pairs of switched interconnects (PICMG 3.0 Specification, Page 294, Section 6.2.1.2).
  • Two switch boards with logical slots of 1, 2 are a set of binary stars.
  • the switching network interconnection structure, the two switching networks with logical slots 3 and 4 are another set of double-star switching network interconnection structures.
  • the dual-chain switching interconnect topology uses two binary-chain switching fabrics, the communication bandwidth between the contiguous boards is doubled. However, since the two switch fabrics are independent, the data stream bandwidth communicated between the node boards is also the bandwidth of a binary star structure, but only supports two data streams.
  • the bandwidth of telecommunication equipment will be higher in the next few years, and the aggregation layer equipment even has to provide a 40Gb/s user interface.
  • the 40Gb/s user interface generally requires the slab backplane bandwidth to provide at least 60Gb/s. Therefore, as mentioned above, under the current definition of the PICMG 3.0 standard, the ATCA system cannot provide sufficient inter-node boards, regardless of the full interconnection, the dual-star exchange interconnection, and the dual-pair exchange interconnection. Communication bandwidth.
  • the present invention provides a switching system and method for improving switching bandwidth to extend the switching interconnect bandwidth between node boards to meet the bandwidth requirements of the user interface.
  • An exchange system for improving the switching bandwidth which is compatible with the ATCA/ATCA 300 architecture, and includes: a backplane, a plurality of node boards, and at least two switch boards, wherein the node boards and the switch boards are connected through the backplane;
  • Each node board is connected to at least two switch boards
  • the node board transmits different data on at least two data links formed by connecting the at least two switch boards, and the at least two switch boards jointly complete data exchange between the node boards.
  • An exchange method for improving switching bandwidth comprising:
  • the node board distributes data to the entry end of at least two switch boards
  • the at least two switch boards collectively exchange data input by the respective ingress terminals to respective outlet ends, and output to another node board to implement data exchange between the node boards.
  • the embodiments of the present invention extend the inter-node board by multi-plane switching in a manner compatible with the physical structure defined by the current ATCA/ATCA 300 and the backplane connector layout.
  • Exchange interconnect bandwidth to provide sufficient communication bandwidth between the node boards to meet the bandwidth requirements of the user interface.
  • the switching interconnect bandwidth can be linearly increased with the number of switchboard configurations.
  • the switch board and the node board can be flexibly configured according to the different bandwidth requirements of the application.
  • FIG. 1 is a schematic structural diagram of a full interconnect switching interconnect topology in the prior art ATCA;
  • FIG. 2 is a schematic structural diagram of a topology of a binary star exchange interconnection in the prior art ATCA;
  • Figure 3 is a block diagram showing the principle of the first embodiment (two-plane switching) of the system of the present invention
  • 4 is a schematic diagram of a backplane connection of two switchboard dual plane switching configurations in the first embodiment of the system of the present invention
  • FIG. 5 is a block diagram showing the second embodiment of the system of the present invention (three-plane switching);
  • FIG. 6 is a top view of a backplane connection of three switchboard configurations in a second embodiment of the system of the present invention
  • FIG. 7 is a top view of a backplane connection of four switchboard configurations in a second embodiment of the system of the present invention
  • It is a backplane connection topology diagram of five switchboard configurations in the second embodiment of the system of the present invention.
  • the fabric interface of the second zone includes four connectors, P20, P21, P22, and P23, and provides up to 15 switching channels to interconnect with other boards.
  • the node board 31 includes a service processing module 311, an uplink processing module 312, and a downlink processing module 313.
  • the uplink processing module 312 and the downlink processing module 313 are respectively connected to the service processing module 311.
  • a pair of uplink processing modules and downlink processing modules together form a transmission module, and each node board includes at least one of the transmission modules.
  • the uplink processing module 312 is used for data scheduling and distributes the data to each switchboard 32.
  • the downlink processing module 313 receives the data of each switchboard 32 and completes the aggregation and sequential reorganization of the data.
  • the service processing module 311 mainly performs processing of services or provides an interface for network interconnection.
  • the switch board 32 includes a switch matrix 323, a plurality of entry terminals 321 and a plurality of exit ports 322.
  • the switch board 32 exchanges data input by the entry terminal 321 through its switch matrix 323 according to routing information of the data packets to the output end 322.
  • the uplink processing module 312 of each node board 31 is respectively connected to the ingress end 321 of the plurality of switch boards 32, and the downlink processing module 313 of each node board is respectively connected to the exit end 322 of the plurality of switch boards 32.
  • the node board 31 serves as an input stage and an output stage when data communication is performed, and the switch board 32 functions as a switching plane to implement the switching function.
  • the uplink processing module 312 of the node board 31 distributes the data to the ingress end 321 of each switch board 32 through data scheduling.
  • the switch board 32 exchanges the data input by the ingress terminal 321 through the switching matrix 323 according to the routing information of the data packet to the egress end.
  • the gang plate provides 8 pairs of differential signals, where Row processing module 312 provides four pairs of transmit signals, and downlink processing module 313 provides four pairs of receive signals.
  • the differential signals are interconnected using serial data.
  • the transmission module distributes data to the plurality of data links formed by the connection module and the other switch boards except the first switch board; and receives the transmission module and The data on the multiple data links formed by the other switch boards connected to the first switch board completes the data aggregation and reassembly.
  • the other switch boards except the first switch board complete the data exchange function between the node boards.
  • FIG. 4 it is a backplane connection topology diagram in the first embodiment of the system of the present invention shown in FIG. 3, wherein the backplane is connected with two switchboard slots (each table entry represents 8 pairs of differential signals, 4 pairs receive signals and 4 pairs send signals).
  • the system is in the dual-plane switching mode.
  • the logical slot number of the switch board 32 is 1, 2, and the logical slot number of the node board 31 is 3-16.
  • the data in the table of Figure 4 represents the slot-channel. For example, the data of the first channel (Slot: 1; Channe: 1) of slot 1 is "2-1", indicating the channel and the second slot.
  • the first channel of the bit is connected.
  • the node board 31 uses only the switching channel 1 and the switching channel 2, so that the communication bandwidth between the node boards is 8 times the physical link operating rate (Link Speed 8). If the "Link Speed" is 2.5Gb/s, the inter-node interconnect bandwidth is 20Gb/s (including 8B/10B overhead). The node board provides a 10Gb/s line rate user interface. If one switch board fails, the communication between the node boards can continue through the remaining one, and the communication bandwidth is 8Gb/s.
  • three switch boards can be configured in the system, in which case the system operates in a three-switch plane (also referred to as "2 + 1"), as shown in FIG.
  • the logical slots 1, 2, and 3 are the switch board 52
  • the logical slots 4 to 16 are the node boards 51.
  • the structure of the node board 51 is the same as that of the embodiment shown in FIG. 3, and includes: a service processing module 511, an uplink processing module 512, and a downlink processing module 513.
  • the structure of the switch board 52 is the same as that of the embodiment shown in FIG. 3, and includes: a switch fabric 523, an ingress port 521, and an egress port 522.
  • the stencil board slot uses channels 1, 2, and 3, and the backplane connection topology is shown in Figure 6.
  • the communication bandwidth between the node boards is "Link Speed ⁇ 12". If the "Link Speed" is 2.5Gb/s, the inter-node interconnect bandwidth is 30Gb/s (including 8B/10B overhead).
  • the switch board slot also provides the node board switch interface interconnect resources.
  • the switch board slot can also be inserted into the node board without requiring large-capacity switching bandwidth.
  • the logical slot 3 can also be inserted into the node board.
  • the interconnection topology is the same as that when the two switching boards are configured, and is compatible with the node board in the first embodiment.
  • four switch boards can be configured on the backplane switch interface, and the system operates in a four-switch plane (also referred to as "3 + 1,").
  • Logical slots 1, 2. 3, 4 is the switch board
  • logical slots 5 ⁇ 16 are node boards
  • the node board slots use channels 1, 2, 3, 4, and the backplane connection topology is shown in Figure 7.
  • the communication bandwidth between the node boards is "Link Speed ⁇ 16", if "Link Speed" is 2.5Gb/s, the inter-node interconnect bandwidth is 40Gb/s (including 8B/10B overhead).
  • the interconnection is The topology is the same as that of the three switch boards, and is compatible with the LUNs in the second embodiment. If the logical slots 3 and 4 are inserted into the node board, the interconnection topology is the same as when configuring the two switch boards. Configure the node board of 1.
  • five switch boards can be configured on the backplane switch interface, and the system operates in a five-switch plane (also referred to as "4 + 1,").
  • the logical slots 1 ⁇ 5 are For the switch board, logical slots 6 to 16 are node boards, and the node board slots use channels 1, 2, 3, 4, and 5.
  • the backplane connection topology is shown in Figure 8.
  • the communication bandwidth between the node boards is "Link.” Speed ⁇ 20", if "Link Speed" is 2.5Gb/s, the inter-node interconnect bandwidth is 50Gb/s (including 8B/10B overhead). If the logical slot 5 is inserted into the node board, then the topology is interconnected.
  • the configuration of the four switch boards is the same, and is compatible with the node boards in the third embodiment. If the logical slots 5 and 4 are inserted into the node board, the interconnection topology is the same as that when the three switch boards are configured. The node board in the embodiment. If the logical slots 5, 4, and 3 are inserted into the node board, then the interconnection topology is the same as that when the two switching boards are configured, and the gusset board in the first embodiment is compatible.
  • each switch board is not limited to the function of completing one switching plane, and can also complete the exchange of multiple switching planes (such as a switch board completion) Switching function of 2 switching planes).
  • the physical link working rate of the system interconnection is also not limited to 2.5Gb/s, 3.125Gb/s, 5Gb/s, 6.25Gb/s, and can work under other rates. The higher the working rate, the higher the switching bandwidth of the node board.
  • each of the node boards in the above embodiments is not limited to using 8 pairs of differential signals (4 pairs of received signals and 4 pairs of transmitted signals) to be interconnected with the switch board, and only a small number of differential signals can be used to implement the node board and the switch.
  • the interconnection between the boards, the signal definition can also use different layouts.
  • the number of slots (the slab slot plus the switchboard slot) of the system is not limited to 16, and may be other values (for example, 14 slots rejected by the 19-inch machine).

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Telephonic Communication Services (AREA)

Description

一种提高交换带宽的交换系统及方法
本申请要求于 2006 年 6 月 23 日提交中国专利局、 申请号为 200610061326.0、 发明名称为"在 ATCA/ATCA300扩展交换带宽的交换结构" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信领域， 更具体地说， 涉及一种兼容 ATCA/ATCA300架构 提高交换带宽的交换系统及方法。
背景技术
ATCA ( Advanced Telecommunications Computing Architecture , 先进电信 计算架构）是 PICMG ( PCI Industrial Computer Manufacturers Group, PCI工业 计算机厂家协会）组织制定并发展的开放工业标准架构， 定位为通信设备和计 算服务器通用的硬件平台技术， 包括机框结构、 电源、 散热、 单板结构、 背板 互连拓朴、 系统管理及交换网建议等规范。 ATCA适用于 600mm深机拒， 为 了适应 300mm深机拒的应用需求， PICMG还制定了 ATCA300的平台架构标 准， 且 ATCA和 ATCA300的背板兼容。
ATCA为中间背板、前后插板结构， 交换板（ Hub Board )和节点板（ Node Board )都为前插板， 节点板通过全互连（Full Mesh )相连或者通过交换板互 连。 ATCA最多支持 16个槽位（21英寸机拒）， 在 19英寸机拒中支持 14个槽 位。 ATCA每个槽位分为 1区 （ Zone 1 )、 2区 （ Zone 2 )和 3区 （ Zone 3 )三 个区域， Zone 1为电源和管理互连区， Zone 3为前插板与对应后插板互连区， Zone 2 为节点板之间 （ Full Mesh拓朴）或节点板与交换板之间 (双星型交换 网互连） 互连区。 如果釆用全互连， 则 ATCA最多支持 16个节点板； 如果釆 用双星型结构交换网互连， 则 ATCA最多支持 14个节点板和 2个交换板， 每 个交换板需要与另外 15个单板（ 14个节点板和 1个交换板）互连； 如果釆用 双双星型结构交换网互连， 则 ATCA最多支持 12个节点板和 4个交换板， 每 个交换板需要与另外 15个单板（ 12个节点板和 3个交换板） 互连。
PICMG 3.0 定义了 3 种交换接口的交换互连拓朴， 分别为全互连（Full Mesh )、 双星型交换互连（Dual Fabric Star ), 双双星型交换互连（Dual Dual Fabric Star ), 这几种交换互连拓朴在 16个槽位或 14个槽位的系统配置下， 两 个节点板之间的互连提供 8对差分信号（发送 4对差分信号，接收 4对差分信 号）。目前交换互连技术的物理链路工作速率主要为 2.5Gb/s、 3.125Gb/s、 5Gb/s、 6.25Gb/s。
如图 1所示， 全互连拓朴为所有节点板 11之间直接互连（图 1所示为 8 个节点板配置情况下的全互连结构）。 PICMG 3.0最多可支持 16个节点板实现 全互连。 然而在全互连拓朴结构下， 即使物理链路工作速率为 6.25Gb/s, 两个 节点板之间的通信带宽也只有 20Gb/s。 此外在具体应用中， 实现 16个节点板 全互连的成本是非常高的， 一般全互连只用于少于 8个节点的系统全互连， 不 能满足较大容量的设备要求。
如图 2所示， 在双星型交换互连拓朴结构中有两个交换板节点 22 (逻辑 槽位号为 1、 2 ), 最多配置 14个节点板（逻辑槽位号为 3 ~ 16 ), 节点板 21 都与交换板节 22点互连，节点板 21之间的通信通过交换板节点进行。 PICMG 3.0规定两个交换网为主备份工作方式（PICMG 3.0 Specification, Page 294, 第 6.2丄 1节 ), 主备份工作时只有主交换板能执行交换功能， 备交换板不执行 交换功能； 或者两个交换板都能执行交换功能，但节点板只接收主交换板的数 据， 不接收备交换板的数据。 因此， 在双星型互连拓朴中， 即使釆用 6.25Gb/s 的物理链路速率， 节点板也只能提供 20Gb/s的带宽， 只能提供 1路 10Gb/s线 速的用户接口。
双双星型交换互连拓朴结构与双星型交换互连拓朴相似，交换板节点从两 个增加到 4个（逻辑槽位为 1、 2、 3、 4 ), 最多配置 12个节点板（逻辑槽位 为 5 ~ 16 ), 节点板都与交换板节点互连， 节点板之间的通信通过交换板节点 进行。 PICMG 3.0 规定 4 个交换板为两组独立的双星型交换互连工作方式 ( PICMG 3.0 Specification, Page 294 , 第 6.2.1.2节）， 逻辑槽位为 1、 2的两 个交换板为一组双星型交换网互连结构， 逻辑槽位为 3、 4的两个交换网为另 一组双星型交换网互连结构。尽管双双星型交换互连拓朴釆用了两个双星型的 交换结构，节点板之间的通信带宽增加一倍。但是由于两个交换结构是独立的， 所以节点板之间通信的数据流带宽还是一个双星型结构的带宽，只是可以支持 两路数据流而已。
目前作为电信平台应用， 在城域网汇聚层提供 10Gb/s用户接口已经成为 基本的需求。 随着互联网的快速发展， 未来几年将对电信设备的带宽提出更高 的要求， 汇聚层设备甚至要提供 40Gb/s的用户接口。 考虑到交换网和业务处 理的加速比和处理开销， 40Gb/s 用户接口一般要求节点板背板带宽至少提供 60Gb/s。 因此如上所述， ATCA系统在目前 PICMG3.0标准的定义之下， 无论 釆用全互连， 还是釆用双星型交换互连、 双双星型交换互连， 都无法提供节点 板之间足够的通信带宽。
发明内容
本发明提供一种提高交换带宽的交换系统及方法，以扩展节点板间的交换 互连带宽， 满足用户接口的带宽需求。
为此， 本发明实施例提供如下的技术方案：
一种提高交换带宽的交换系统， 兼容 ATCA/ATCA 300架构， 包括： 背板、 多个节点板及至少两个交换板， 所述节点板和交换板通过所述背板 相连；
每一个节点板与至少两个交换板连接；
所述节点板与所述至少两个交换板连接形成的至少两条数据链路上传输 不同的数据， 所述至少两个交换板共同完成节点板之间的数据交换。
一种提高交换带宽的交换方法， 所述方法包括：
节点板把数据分发给至少两个交换板的入口端；
所述至少两个交换板共同将各自入口端输入的数据交换到各自出口端，并 输出到另一节点板， 实现节点板之间的数据交换。
由以上本发明实施例提供的技术方案可以看出，本发明实施例在兼容目前 ATCA/ATCA 300定义的物理结构和背板连接器布局情况下， 通过多平面交换 的方式扩展了节点板间的交换互连带宽，提供节点板之间足够的通信带宽， 满 足用户接口对带宽的需求。且交换互连带宽可以随着交换板配置的数量线性增 长， 交换板和节点板可以根据应用场合对带宽的不同需求， 灵活进行配置。 附图说明
图 1是现有技术 ATCA中全互连交换互连拓朴的结构示意图；
图 2是现有技术 ATCA中双星型交换互连拓朴的结构示意图；
图 3是本发明系统第一实施例 （双平面交换） 的原理框图； 图 4 是本发明系统第一实施例中两个交换板双平面交换配置的背板连接 拓朴图；
图 5是本发明系统第二实施例 （三平面交换） 的原理框图；
图 6是本发明系统第二实施例中三个交换板配置的背板连接拓朴图； 图 7是本发明系统第二实施例中四个交换板配置的背板连接拓朴图； 图 8是本发明系统第二实施例中五个交换板配置的背板连接拓朴图。 具体实施方式
如图 3所示， 本发明系统第一实施例中， 配置中有 14个节点板 31以及 2 个交换板 32, 每个节点板均通过背板（图中未示出）与这两个交换板连接。 背板第二区 （zone 2 ) 的交换接口 （ fabric interface ) 包括有 4个连接器， 分别 为 P20、 P21、 P22、 P23 , 最多提供 15个交换通道与其他单板互连。
在本实施例中， 节点板 31 包括有业务处理模块 311、 上行处理模块 312 和下行处理模块 313 , 其中上行处理模块 312和下行处理模块 313分别与业务 处理模块 311 连接。 一对上行处理模块和下行处理模块一起构成一个传输模 块，每个节点板至少包括一个所述传输模块。上行处理模块 312用于数据调度 并把数据均衡分发到各个交换板 32 , 下行处理模块 313接收各个交换板 32的 数据并完成数据的汇聚和按序重组。业务处理模块 311主要完成业务的处理或 提供网络互连的接口。
交换板 32包括有交换矩阵 323、 多个入口端 321和多个出口端 322, 该交 换板 32通过其交换矩阵 323将入口端 321输入的数据根据数据包的路由信息 交换到出口端 322输出。
在本实施例中， 每一节点板 31的上行处理模块 312分别连接到多个交换 板 32的入口端 321且每一节点板的下行处理模块 313分别连接到多个交换板 32的出口端 322。 从而， 在进行数据通信时节点板 31作为输入级和输出级， 而交换板 32作为交换平面实现交换功能。节点板 31的上行处理模块 312通过 数据调度把数据均衡分发到各个交换板 32的入口端 321 , 交换板 32通过其交 换矩阵 323 将入口端 321 输入的数据根据数据包的路由信息交换到出口端 322, 并输出到下行处理模块 313 , 并完成数据的汇聚和按序重组， 从而完成 节点板 31间的数据通信。 在本实施例中， 节点板提供 8对差分信号， 其中上 行处理模块 312提供 4对发送信号， 下行处理模块 313提供 4对接收信号。 差 分信号釆用串行数据互连。
当第一交换板出现故障时 ,所述传输模块将数据分布到所述传输模块与除 第一交换板外的其他交换板连接所形成的多条数据链路上；并接收所述传输模 块与除第一交换板外的其他交换板连接所形成的多条数据链路上的数据，完成 数据汇聚重组，除第一交换板外的其他交换板共同完成节点板之间的数据交换 功能。
如图 4所示， 为图 3所示本发明系统的第一实施例中的背板连接拓朴图， 其中背板连接有两个交换板槽位（每个表格项代表 8对差分信号， 其中 4对接 收信号， 4对发送信号）。 此时系统为双平面交换工作方式， 其中交换板 32的 逻辑槽位号为 1、 2 , 而节点板 31的逻辑槽位号为 3-16。 图 4表格中的数据表 示槽位 -通道 ( Slot-Channel ), 例如槽位 1的第 1通道 ( Slot: 1 ; Channe: 1 ) 的数据为" 2-1", 表示该通道与第 2槽位的第 1通道相连。
由于使用了两个交换板， 节点板 31仅使用交换通道 1和交换通道 2 , 从 而节点板间的通信带宽为 8倍物理链路工作速率（ Link Speed 8 )。 如果" Link Speed"为 2.5Gb/s, 则节点间互连带宽为 20Gb/s (包括 8B/10B开销）。 从而节 点板可提供 10Gb/s线速用户接口。 如果一个交换板故障， 节点板之间可通过 剩下的一个交换板继续通信， 其通信带宽为 8Gb/s。
在本发明的第二实施例中， 可在系统中配置三个交换板， 此时系统为三交 换平面工作方式（也称为" 2 + 1" ), 如图 5所示。 逻辑槽位 1、 2、 3为交换板 52 , 逻辑槽位 4 ~ 16为节点板 51。 节点板 51的结构与图 3所示实施例相同， 包括： 业务处理模块 511、 上行处理模块 512和下行处理模块 513。 交换板 52 的结构与图 3所示实施例相同， 包括： 交换矩阵 523、入端口 521、出端口 522。 节点板槽位使用通道 1、 2、 3 , 背板连接拓朴如图 6所示。 节点板之间的通信 带宽为 "Link Speed χ 12", 如果" Link Speed"为 2.5Gb/s, 则节点间互连带宽为 30Gb/s (包括 8B/10B开销）。 交换板槽位也提供节点板交换接口互连资源， 在 不需要大容量交换带宽的情况下， 交换板槽位也可以插入节点板。例如逻辑槽 位 3也可以插节点板， 则此时互连拓朴与配置两个交换板时相同， 可兼容第一 实施例中的节点板。 在本发明的第三实施例中， 可在背板交换接口配置四个交换板， 此时系统 为四交换平面工作方式（也称为" 3 + 1，，）。 逻辑槽位 1、 2、 3、 4为交换板， 逻 辑槽位 5 ~ 16为节点板， 节点板槽位使用通道 1、 2、 3、 4 , 背板连接拓朴如 图 7所示。 节点板之间的通信带宽为" Link Speed χ 16", 如果" Link Speed"为 2.5Gb/s, 则节点间互连带宽为 40Gb/s (包括 8B/10B开销）。 如果逻辑槽位 4 插节点板， 则此时互连拓朴与配置三个交换板时相同， 可兼容第二实施例中的 节点板。 如果逻辑槽位 3、 4插节点板， 这时候互连拓朴与配置两个交换板时 相同， 可兼容配置 1的节点板。
在本发明的第四实施例中， 可在背板交换接口配置五个交换板， 此时系统 为五交换平面工作方式（也称为" 4 + 1，，）。 逻辑槽位 1 ~ 5为交换板， 逻辑槽位 6 ~ 16为节点板， 节点板槽位使用通道 1、 2、 3、 4、 5 , 背板连接拓朴如图 8 所示。节点板之间的通信带宽为 "Link Speed χ20",如果" Link Speed"为 2.5Gb/s, 则节点间互连带宽为 50Gb/s (包括 8B/10B开销）。 如果逻辑槽位 5插节点板， 则此时互连拓朴与配置四个交换板时相同， 可兼容第三实施例中的节点板。如 果逻辑槽位 5、 4插节点板， 则此时互连拓朴与配置三个交换板时相同， 可兼 容第二实施例中的节点板。 如果逻辑槽位 5、 4、 3插节点板， 则此时互连拓朴 与配置两个交换板时相同， 可兼容第一实施例中的节点板。
依此类推， 还可以配置更多的交换板槽位（5个以上）来获得更多的交换 互连带宽。
在各种配置情况下，不同物理链路的工作速率达到的节点板之间通信带宽
(不包括 8B/10B开销）如表 1所示：
Figure imgf000008_0001
正常工作 40Gb/ s 50Gb/ s 80Gb/ s l OOGb/ s
5个交换板
1个故障 32Gb/ s 40Gb/ s 64Gb/ s 80Gb/ s 在上述的实施例中，每个交换板不限于完成一个交换平面的功能，也可以 完成多个交换平面的交换（比如一个交换板完成 2个交换平面的交换功能）。 而系统互连的物理链路工作速率也不限于 2.5Gb/s、3.125Gb/s、5Gb/s、6.25Gb/s, 也可以工作在其他速率之下。 工作速率越高， 节点板的交换带宽越高。
此外， 上述实施例中的每个节点板也不限于使用 8对差分信号（4对接收 信号和 4对发送信号）与交换板互连， 也可以只使用其他数量的差分信号实现 节点板和交换板之间的互连， 信号定义也可以釆用不同的布局。
此外， 上述实施例中， 系统的槽位（节点板槽位加上交换板槽位）数量不 限于 16 , 也可以是其他数值 (例如 19英寸机拒的 14个槽位）。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局 限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应该以权利要求的保护范围为准。

Claims

权 利 要 求
1、 一种提高交换带宽的交换系统， 兼容 ATCA/ATCA 300架构， 其特征 在于， 包括：
背板、 多个节点板及至少两个交换板， 所述节点板和交换板通过所述背板 相连；
每一个节点板与至少两个交换板连接；
所述节点板与所述至少两个交换板连接形成的至少两条数据链路上传输 不同的数据， 所述至少两个交换板共同完成节点板之间的数据交换。
2、 根据权利要求 1所述的提高交换带宽的交换系统， 其特征在于， 所述 每一个节点板包括至少一个传输模块。
3、 根据权利要求 2所述的提高交换带宽的交换系统， 其特征在于， 每一 个所述交换板包括多个端口， 所述端口与所述传输模块连接， 形成多条数据链 路。
4、 根据权利要求 3所述的提高交换带宽的交换系统， 其特征在于， 每一 个所述端口包括一入口端和一出口端。
5、 根据权利要求 4所述的提高交换带宽的交换系统， 其特征在于， 所述 传输模块包括：
一上行处理模块， 将处理数据分发到所述多条数据链路上；
一下行处理模块，接收所述多条链路上传输的不同数据， 并完成数据的汇 聚重组。
6、 根据权利要求 5所述的提高交换带宽的交换系统， 其特征在于， 所述 上行处理模块分别与至少两个所述交换板上的所述入端口连接，形成至少两条 上行数据链路；
所述下行处理模块与分别与至少两个所述交换板上的所述出端口连接，形 成至少两条下行数据链路。
7、 根据权利要求 2所述的提高交换带宽的交换系统， 其特征在于， 当一个或多个所述交换板出现故障时，与出现故障的交换板相连的传输模 块将其需要传输的数据分布到与未出故障的交换板连接所形成的多条数据链 路上， 并接收与未出故障的交换板连接所形成的多条数据链路上的数据， 完成 数据的汇聚与重组。
8、 根据权利要求 7所述的提高交换带宽的交换系统， 其特征在于， 当一 个或多个所述交换板出现故障时，除出现故障的交换板外的其他交换板共同完 成节点板之间的数据交换功能。
9、 根据权利要求 1所述的提高交换带宽的交换系统， 其特征在于， 所述 背板包括至少两个交换板槽位和多个节点板槽位，所述交换板槽位之间互相连 接， 所述交换板槽位和所述节点板槽位连接， 所述交换板槽位用于配置交换板 或节点板， 所述节点板槽位用于配置节点板。
10、 根据权利要求 9所述的提高交换带宽的交换系统， 其特征在于， 根据交换带宽和节点板数量的需求配置交换板和节点板的数量。
11、 一种提高交换带宽的交换方法， 其特征在于， 所述方法包括： 节点板把数据分发给至少两个交换板的入口端；
所述至少两个交换板共同将各自入口端输入的数据交换到各自出口端，并 输出到另一节点板， 实现节点板之间的数据交换。
12、 根据权利要求 11所述的提高交换带宽的交换方法， 其特征在于，
13、根据权利要求 11或 12所述的提高交换带宽的交换方法，其特征在于， 当一个交换板出现故障时， 所述节点板与未出现故障的交换板交换数据。
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EP1981206B1 (en) 2012-08-15
US20080279094A1 (en) 2008-11-13
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CN101313513A (zh) 2008-11-26
US20130343177A1 (en) 2013-12-26
JP2009542053A (ja) 2009-11-26
EP1981206A1 (en) 2008-10-15
CN101094125A (zh) 2007-12-26
JP4843087B2 (ja) 2011-12-21
EP1981206A4 (en) 2009-03-04

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