WO2008089227A1

WO2008089227A1 - Non-volatile memory cell manufactured with cmos process steps

Info

Publication number: WO2008089227A1
Application number: PCT/US2008/051153
Authority: WO
Inventors: Fariborz Assaderaghi; Reza Navid
Original assignee: Rambus Inc
Current assignee: Rambus Inc
Priority date: 2007-01-17
Filing date: 2008-01-16
Publication date: 2008-07-24
Anticipated expiration: 2009-07-17

Abstract

A semiconductor device, among other embodiments, includes a non-volatile memory cell that is manufactured using 'standard' CMOS manufacturing processes steps. The non-volatile memory cell comprises a substrate having a drain and source. A floating gate is disposed over the substrate. A metal fringe capacitor is between the floating gate and a terminal to receive a control voltage. In an embodiment, a metal fringe capacitor includes a first metal region coupled to the floating gate and a second metal region coupled to the terminal. In another embodiment, an N-WeII capacitor on an SOI substrate is formed instead of the metal fringe capacitor. An array of non-volatile memory cells, such as NAND, AND and NOR memory cell arrays may likewise be manufactured.

Description

Non-Volatile Memory Cell Manufactured with CMOS

Process Steps

FIELD OF THE INVENTION

The present invention generally relates to integrated circuit semiconductor devices and/or high speed signaling of such devices.

BACKGROUND OF THE RELATED ART

A non-volatile memory cell is an integrated circuit memory cell that retains stored information when the power source is removed. Types of non-volatile memory cells include read-only memory ("ROM") and electrically erasable programmable read-only memory ("EEPROM") cells. A version of EEPROM that allows for blocks of information to be written or read, as opposed to bytes of information, is referred to as flash memory.

Manufacturing a non-volatile memory cell is typically more complex and expensive than manufacturing conventional/standard Complementary Metal Oxide Semiconductor ("CMOS") circuits/transistors, such as a CMOS memory cell that may be used in static random access memory ("SRAM"). Often, in a system, non-volatile memory cells are on separate semiconductor chips from other circuits manufactured using standard CMOS fabrication processes. Embedded non-volatile memory cells may be embedded into a semiconductor chip that includes CMOS circuits; however, significantly modified and additional manufacturing process steps, including additional mask steps, are typically required.

Therefore, it is desirable to manufacture a non-volatile memory cell, or an array of non-volatile memory cells, using conventional or "standard" CMOS manufacturing process steps that do not require additional and/or significantly modified fabrication steps.

BRIEF DESCRIPTION OF THE DRAWING

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing. Like reference numerals refer to similar elements.

Fig. 1 is an equivalent circuit representation of a non-volatile memory cell according to an embodiment.

Fig. 2A illustrates a non-volatile memory cell circuit having a metal fringe capacitor according to an embodiment.

Fig. 2B illustrates a cross section of the metal fringe capacitor shown in Fig. 2A according to an embodiment.

Figs. 3, 3A, and 3B illustrate top views of a semiconductor device including a non-volatile memory cell having a metal fringe capacitor according to an embodiment.

Fig. 4 illustrates a cross section view of the semiconductor device shown in Fig. 3 along line A-B in Fig. 3.

Fig. 5 illustrates a cross section view of the semiconductor device shown in Fig. 3 along line A1-B1 in Fig. 3.

Fig. 6 illustrates a cross section view of the semiconductor device shown in Fig. 3 along line A2-B2 in Fig. 3.

Fig. 7 illustrates a cross section view of the semiconductor device shown in Fig. 3 along line C-D in Fig. 3.

Fig. 8 illustrates a top view of a semiconductor device including a non-volatile memory cell having a N+ polysilicon on N-well capacitor according to an embodiment.

Fig. 9 illustrates a cross section view of the semiconductor device shown in Fig. 8 along the line E-F. Figs. 10A-C illustrate arrays of non-volatile NAND, AND and NOR memory cells having one or more memory cells according to an embodiment.

Fig. 11 illustrates a monolithic integrated circuit having an array of non-volatile memory cells and application logic/circuit including CMOS transistors according to an embodiment.

Figs. 12A-B are flow charts that illustrate methods of manufacturing a non-volatile memory cell, according to embodiments, using "standard" CMOS manufacturing processing steps.

DETAILED DESCRIPTION

A semiconductor device, among other embodiments, includes a non-volatile memory cell that can be manufactured using "standard" CMOS manufacturing processes steps. The non-volatile memory cell comprises a substrate having a drain and source. A polysilicon gate is disposed over the substrate. A first insulating region is disposed between the polysilicon gate and the substrate. A capacitor is formed between the gate and a terminal to receive a control voltage. In an embodiment, the capacitor is a metal fringe capacitor including first metal region(s) and second metal region(s) separated by a dielectric region. The first and second metal regions and the dielectric region form a capacitor having a predetermined capacitance between the floating gate and the terminal. In another embodiment, an N+ polysilicon on an N-well in an SOI substrate is used to form the capacitor between the floating gate and the terminal. An array of non-volatile memory cells, such as NAND, AND and NOR memory cell arrays may likewise be manufactured. A monolithic integrated circuit may include a non-volatile memory cell array for storing a value used by application logic/circuit, including CMOS transistors, which are both disposed on a single substrate.

Fig. 1 is an equivalent circuit representation of a non-volatile memory cell 100 according to an embodiment. The non-volatile memory cell 100 may be a EEPROM or flash memory cell, and includes a source (S) and drain (D) formed in a substrate, and a control gate 160 coupled to a control terminal Vc. A floating gate 120 is disposed over the substrate to store a charge or voltage value that may represent a logical value or bit of information when predetermined voltages are provided to the source S, drain D and control terminal Vc. The non-volatile memory cell 100 further includes a capacitor C1 between the floating gate 120 and the control terminal Vc. The floating gate 120 and the substrate form a second capacitor C2. Thus, the floating gate 120 is separated from the control terminal Vc and the substrate by capacitors C1 and C2, respectively, so that the charge may remain in the floating gate 120 when power is removed. The charge or voltage value on the floating gate 120 may be sensed when predetermined voltages are provided to the source S, drain D and control terminal Vc. Fig. 2A illustrates a nonvolatile memory cell 190 having a metal fringe capacitor that functions as capacitor C1 according to an embodiment. Metal fringe capacitor C1 includes a plurality of metal regions or members, which can be in a single layer or multiple layers separated by dielectric matehal/region(s). In alternate embodiments, other types of material that conduct current are used in combination with or instead of metal. As described above, a predetermined control voltage may be provided to control terminal Vc in storing/removing or sending a charge on/from floating gate 120.

Fig. 2B illustrates a cross section of metal fringe capacitor C1 in which a first plurality of substantially rectangular shaped regions (+) is coupled to control terminal Vc and a second plurality of rectangular shaped regions (-) is coupled to floating gate 120. In an embodiment, the first plurality of metal regions extend from a first metal region and the second plurality of metal regions extend from a second metal region. In an embodiment, the first and second pluralities of rectangular shaped regions are separated by dielectric material in one or more dielectric regions/layers.

Metal fringe capacitor C1 , along with other elements of the nonvolatile memory cell 190, can be formed using "standard" CMOS manufacturing processing steps. Because non-volatile memory cell 190 is able to be manufactured with "standard" CMOS processing steps, non-volatile memory cell 190 may be embedded with other CMOS circuits on a single monolithic circuit without the use of specialized, complicated and expensive manufacturing process steps, as described below.

Fig. 3 illustrates a top view of a non-volatile memory cell 300, such as an EEPROM or flash memory cell, including a metal fringe capacitor 302. Non-volatile memory cell 300 includes numerous regions disposed in and over a semiconductor substrate 301 , including source/drain diffusion regions 304 and 305, and a floating gate 307 coupled to metal fringe capacitor 302. In one embodiment, the floating gate comprises polysilicon.

In an embodiment, a metal fringe capacitor 302 includes a plurality of metal regions separated by dielectric regions/layers 330 made of, for example, silicon dioxide. Other types of insulator materials, such as silicon oxynitride, low-k dielectrics or the like, may be also be used for the dielectric layers 330. In particular, a metal fringe capacitor 302 includes metal regions 331 and 332 in a first metal layer, and metal regions 334 and 335 in a second metal layer. In various embodiments, more or less metal regions and layers may be used to form a metal fringe capacitor. Metal region 331 is coupled to floating gate 307 by a via (or contact) 340. In an embodiment, a via may include metal. In embodiments, other vias, such as vias 341 and 342 as described below, are formed between the first and second metal layers. Fig. 3A illustrates a top view of the nonvolatile cell 300 without showing the second layer of metal lines. Fig. 3B illustrates a top view of the metal regions 334 and 335 without showing the source/drain regions, the gate and the first layer of metal lines.

Figs. 4-7 illustrate cross section views of nonvolatile memory cell 300 taken across lines A-B, A1-B1 . A2-B2. and C-D, respectively, in Figs. 3, 3A, and 3B. Terminal (Vc) 312, which may be a pad of an integrated circuit including the nonvolatile memory cell, is coupled to the metal fringe capacitor and used to provide a control voltage to nonvolatile memory cell 300. In particular, terminal (Vc) 312 is coupled to metal regions 335 and 332 as shown in Figs. 3A, 3B, and 4-6. In particular, metal region 332 is coupled to metal region 335 by via 341. In contrast, metal regions 334 and 331 are coupled to floating gate 307. In particular, via 342 couples metal region 334 to metal region 331 , while metal region 331 is coupled to floating gate 307 by via (or contact) 340. Nonvolatile memory cell 300 further includes metal region 333 in the first metal layer. Metal region 333 is coupled to source/drain diffusion region 305 through a contact 343. Similarly, a predetermined voltage may be provided to source/drain diffusion region 305 through metal region 333 and contact 343 as shown in Figs. 3 and 4. Also, a voltage such as a reference voltage or ground may be provided to source/drain diffusion region 304 in an embodiment.

Fig. 4 shows a cross section of a non-volatile memory cell 300 along the line A-B in Fig. 3. In an embodiment, a semiconductor substrate 301 has a first conductive type, such as a P conductive type. For example, semiconductor substrate 301 may be a silicon substrate. In an embodiment, substrate 301 is a bulk substrate being entirely formed of a P conductivity type material. In another embodiment, substrate 301 is formed of a P conductivity type material having an epitaxial layer on a top surface where the epitaxial layer is formed of a P conductivity type material. P and N conductivity type materials, also known as doped semiconductor materials, are those materials typically known to have altered conductivity from an intrinsic semiconductor material by having mainly either holes (P type) or electrons (N type) to conduct electricity. Other doped regions, either of a different type (or polarity) or of a higher dopant concentration from that of the substrate, such as N+ and P+ regions, are typically referred to as diffusion regions. For silicon substrates, the dopants, such as arsenic, phosphorus or boron, are generally found in Groups III and V of the periodic table. In alternate embodiments, substrate 301 may consist of germanium, germanium/silicon, gallium arsenide, polysilicon, silicon-on-insulator ("SOI") or an equivalent.

As described above, memory cell 300 may be formed using a set of conventional CMOS manufacturing process steps. These processing steps may include, but are not limited to, masking, implantation, etching, chemical vapor depositing, sputtering and annealing. In one embodiment, P-well 303 may be formed in the substrate 301 , and N-type diffusion regions 304 and 305 are disposed or formed in substrate 301 , in particular P-well 303, to function as a source and drain of memory cell 300. In an embodiment, diffusion regions 304 and 305 correspond to source S and drain D shown in Fig. 2A.

Gate dielectric 306 and floating gate 307 are also disposed or formed thereafter. For example, growing an oxide layer or other dielectric layer, such as silicon dioxide, silicon nitride, silicon oxynithde, on a substrate surface, may form gate dielectric 306. A polysilicon layer may then be deposited on top of the oxide layer and etched afterwards to form a floating gate 307. In an embodiment, the gate dielectric 306 and the floating gate 307 are formed using the same process steps for forming the gates of CMOS transistors in a same integrated circuit. Typically, the gates of the CMOS transistors are not left floating but are generally connected to a supply voltage or ground reference voltage through a conductive path. In contrast, floating gate 307 is used in a non-volatile memory cell 300.

In some embodiments, a suicided silicon/polysilicon layer 318 may be formed on floating gate 307 and regions 304 and 305. Spacers 109 are also formed adjacent to floating gate 307.

Fig. 4 also illustrates that dielectric regions/layers 330 separate metal regions 333, 331 , 332, 335 and 334. Multiple layers of an insulator material, such as silicon dioxide, may form dielectric regions 330. In an embodiment, dielectric regions 330 may include a material that is a poor conductor of current, but an efficient supporter of electrostatic fields. In embodiments, dielectric regions 330 may include nitrided oxides, "low-k" dielectric material or even an organic insulator.

Figs. 5 and 6 show cross sections of a non-volatile memory cell 300 along the lines A1 -B1 and A2-B2 in Fig. 3. In particular, Fig. 5 illustrates how metal regions 334 and 331 are coupled by way of via 342 and thus have the same voltage as floating gate 307 because metal region 331 is coupled to floating gate 307 by way of via (or contact) 340 as shown in Fig. 6. Fig. 6 illustrates how metal regions 332 and 335 are coupled by way of via 341 and thus have the same voltage as the terminal Vc.

Fig. 7 shows a cross section of a non-volatile memory cell 300 along the line C-D in Fig. 3. In an embodiment, metal regions 335, 334, 331 and 332 form a matrix of metal regions separated by dielectric regions 330 to increase capacitance per unit area/volume. Similar to Fig. 2B, metal regions 335 and 332 have a first voltage, such as a positive voltage (+), based on voltage applied to terminal (Vc) 312, while adjacent and parallel rectangular shaped metal regions 331 and 334 have a second voltage, such as a negative voltage (-), based on the voltage provided by floating gate 307. In an embodiment, a metal fringe capacitor with a capacitance as high as approximately 1 to approximately 2 fF/μm² can be achieved using the metal fringe capacitor 302. In an embodiment, metal regions 331 , 332, 334, and 335 and dielectric layers 330 shown in Fig. 7 are formed using the same process steps for forming the metal lines and dielectric layers in a CMOS circuit. The metal regions 331 , 332, 334, and 335 may have a near rectangular cross section with dimensions and spacing limited by the same design rules used for forming the metal lines of a corresponding CMOS circuit in a same integrated circuit. Accordingly, metal regions 335, 334, 331 and 332 form a metal fringe capacitor that provides a predetermined capacitance when voltages are provided from terminal (Vc) 312 and floating gate 307.

A variety of different types of programming, erasing and reading methods may be used in operating non-volatile memory cell 300, such as Fowler-Nordheim tunneling, hot electron injection or an equivalent. Applying a variety of voltage values to elements or regions of nonvolatile memory cell 300 allow for programming, erasing and/or reading of non-volatile memory cell 300. To store a logical zero, electrons may be injected onto floating gate 307 to provide a negative voltage or charge on floating gate 307 thus increasing the threshold voltage needed to turn on the transistor. Similarly, in order to erase a zero logical value in non-volatile memory cell 300, electrons may be removed from floating gate 307 thereby decreasing the threshold voltage and a logical one stored on floating gate 307. A logical value may be read by sensing or measuring a charge associated with floating gate 307 of nonvolatile memory cell 300.

Fig. 8 illustrates a top view of non-volatile memory cell 800 having an N+ polysilicon on N-well capacitor 810, such as used in bypass capacitors. Fig. 9 illustrates a cross-section portion of nonvolatile memory cell 800 along the line E-F. Fig. 9 illustrates signal lines/paths rather than actual metal layers and vias to clearly illustrate how the semiconductor components are coupled. Non-volatile memory cell 800 is similar to non-volatile memory cell 300 except that a metal fringe capacitor is replaced with an N+ polysilicon on N-well capacitor 810. An isolation region 320, such as a STI region or an equivalent, is formed to isolate N+ polysilicon on N-well capacitor 810 from floating gate 307, region (source) 304 and region (drain) 305. Spacers 919, similar to spacers 309, are formed adjacent to floating gate 817; while suicided silicon/polysilicon layers/regions 918, similar to suicided silicon/polysilicon layers/regions 318, are formed on regions 814 and 815 as well as floating gate 817.

N+ polysilicon on N-well capacitor 810 includes region (source) 814, region (N-WeII) 903, region (drain) 815, gate oxide 916 and polysilicon or floating gate 817 that are formed using "standard" CMOS SOI manufacturing processing steps on buried oxide 904 over substrate 901. In an embodiment, elements or regions of N+ polysilicon on N-well capacitor 810 are fabricated concurrently with other regions of nonvolatile memory cell 800. Manufacturing a non-volatile memory cell with an SOI substrate allows for applying a voltage to regions 814, 815 and 903 which may reduce leakage concerns. If the non-volatile memory cell is manufactured using a conventional bulk CMOS process (instead of SOI), further isolation of region 903 may be needed (i.e. by using one extra well). In that case, the reverse junction leakage of region 903 to the substrate or to another well becomes a concern. Therefore, use of an SOI substrate enables creation of a non-volatile memory cell in an embodiment.

Floating gate 307 is coupled to floating gate 817 by a conductive path, such as a metal layer 830, by way of vias 840 and 841 coupled to floating gates 307 and 817. Similarly, regions 814 and 815 are coupled to terminal (Vc) 312 by a conductive path 831 , such as a metal layer, and vias 842 and 843 coupled to regions 814 and 815.

Non-volatile memory cell 800 may be similarly programmed, erased and read as described above in regard to non-volatile memory cell 300.

Figs. 10A-C schematically illustrate NAND, AND and NOR arrays 1000, 1020 and 1030 of non-volatile memory cells as described herein. In an embodiment, memory cells 1001-1003 correspond to non-volatile memory cells 300 or 800 as described above. For example, a schematic representation of a memory cell 1001 is represented by two portions 1001 a and 1001 b of a non-volatile memory cell. Portion 1001 a may represent metal fringe capacitor coupled to terminal (Vc) 312, which is in turn coupled to word line 1004a. Alternatively, portion 1001 a represents N+ polysilicon on N-well capacitor 810, as shown in Figs. 8 and 9, which is also coupled to word line 1004a via terminal (Vc) 312. In an embodiment, source line 1005 is coupled to a ground reference. Accordingly, non-volatile memory cells 1001 -1003 have corresponding floating gates coupled to word lines 1004a-c.

In regard to Fig. 10A, non-volatile memory cell 1001 has a region (drain) 305 coupled to bit line 1006 and a region 304 (source) coupled to a drain of non-volatile memory cell 1002. A source of non-volatile memory cell 1002 is coupled to a drain of non-volatile memory cell 1003 while a source of non-volatile memory cell 1003 is coupled to source line 1005. Accordingly, non-volatile memory cells 1001-1003 are coupled in a NAND memory cell array 1000.

In regard to Fig. 10B, drains of non-volatile memory cell 1001 - 1003 are coupled to bit line 1006 by way of selector transistor 1021. Similarly, sources of non-volatile memory cell 1001-1003 are coupled to source line 1005 via selector transistor 1022. Control signals are provided to the gates of selector transistors 1021 and 1022 during operation of non-volatile memory cells 1001-1003. Accordingly, nonvolatile memory cells 1001 -1003 are coupled in an AND non-volatile memory cell array 1020.

In regard to Fig. 10C, drains of each non-volatile memory cells 1001-1003 are coupled to bit line 1006 and sources of each non-volatile memory cells 1001-1003 are coupled to source line 1005. Accordingly, memory cells 1001-1003 are coupled in an NOR non-volatile memory cell array 1030.

Word, bit and source lines are conductive paths that may be formed by metal or an equivalent conductive material. In an embodiment, word, bit and source lines are coupled to non-volatile read/write operational circuits.

Having an embedded non-volatile memory array using a "standard" CMOS process may provide many advantages and may enable many functions in embodiments. For example, on a transceiver chip/integrated circuit, instead of using the same transmit and/or receive equalization coefficients for all manufactured chips, unique coefficients (values) can be used per chip by using the non-volatile memory to store these unique values in each chip.

In another embodiment, part or an entire initialization/boot code may be stored inside a chip instead of relying on a separate chip and transferring the code from that separate chip after power up. This may speed up the power-up sequence and may reduce system cost.

In yet another embodiment, the embedded non-volatile memory may be used to assign chip ID to each individual chip for tracking, identification and other purposes.

In still a further embodiment, the embedded non-volatile memory may be used to train/trim/adjust settings of sensitive circuits after their manufacturing on a per-chip basis, to the desired values so that yield and functionality improves.

Fig. 11 illustrates monolithic CMOS integrated circuit 1 100 including an array of non-volatile memory cells 1 101 and application logic/circuit 1 103 coupled by way of conductive path 1 104. In an embodiment, circuit 1 100 is fabricated using "standard" CMOS manufacturing steps. In an embodiment, an array of non-volatile memory cells 1 101 includes one of the non-volatile memory cell arrays illustrated in Figs. 10A-C. A multi-bit value 1 102 is stored in an array of nonvolatile memory cells 1 101 and used by application logic 1 103. In an embodiment, an array of non-volatile memory cells 1 101 further includes read/write operational circuits to provide value 1 102 to application logic 1103 in response to a control signal 1 107. In embodiments, control signal 1 106 is generated by application logic 1 103 or from an external circuit. In an embodiment, application logic 1 103 is an equalization circuit for adjusting the transfer of read and write data to and from transmitter 1 106 and receiver 1 105 and value 1 102 is an equalization coefficient (or tap value) used by the equalization circuit in transferring the data.

In an embodiment, logic circuit 1 103 includes CMOS transistors each having a source, a drain and a gate. Logic circuit 1 103 further includes metal lines interconnecting the CMOS transistors. In an embodiment, at least some of the sources, drains and floating gates of the CMOS transistors and the sources, drains and floating gates of the non-volatile memory cells 1 101 are formed in the same manufacturing process steps. In an embodiment, first and second metal regions (forming a fringe capacitor) of the respective non-volatile memory cells 1 101 are formed in the same manufacturing process steps in which at least some of the metal lines are formed. Figs. 12A-B illustrate methods 1200 and 1210 for fabricating a non-volatile memory cell, such as non-volatile memory cell 300 or 800, using "standard" CMOS manufacturing processing steps. In embodiments, logic blocks illustrated in Figs. 12A-B are carried out by CMOS semiconductor manufacturing equipment, software, an individual or a combination thereof. In embodiments, logic blocks illustrated in Figs. 12A-B illustrate actions or manufacturing steps. Other logic blocks that are not shown may be included in various embodiments. Similarly, logic blocks that are shown may be excluded in various embodiments. Also, while methods 1200 and 1210 are described in sequential logic blocks, steps of logic blocks of methods 1200 and 1210 may be completed concurrently in embodiments.

Method 1200 begins by forming STI regions in a substrate as illustrated by logic block 1201 . A gate oxide layer and floating gates are formed as illustrated by logic blocks 1202 and 1203. In an embodiment, a "standard" CMOS manufacturing process step, such as a masking and/or etching step, is used to form the floating gates. Source and drain regions are formed in the substrate as illustrated by logic block 1204. In an embodiment, an active region is formed in a substrate to act as a source and/or drain by using a "standard" CMOS manufacturing process step, such as implantation of a dopant. A first dielectric layer is formed as illustrated in logic block 1205. Contacts through the first dielectric layer are formed and a first metal layer connected to the floating gate is formed as illustrated by logic block 1206. A second dielectric layer is formed as illustrated in logic block 1207. In logic block 1208, vias through the second dielectric layer are formed as well as a second metal layer.

In an embodiment, multiple metal layers are formed to provide a metal fringe capacitor between the floating gate and a terminal. In an embodiment, the drain is coupled to a bit line, the source is coupled to a ground and the terminal is coupled to a word line. In embodiments, predetermined voltage values are applied to the drain, source and a terminal in programming, erasing and/or reading the non-volatile memory cell.

Method 1210, similar to method 1200, disposes an STI region, a first drain, first source and first floating gate over a gate oxide on a SOI substrate as illustrated by logic blocks 121 1-1214. A second floating gate is formed as illustrated by logic block 1214. For example, N+ polysilicon on N-well capacitor is disposed on the substrate. In an embodiment, the first source and first drain, as well as the second source and second drain are formed concurrently. Similarly, the first and second floating gates may be formed concurrently. A first conductive path is formed between the first and second floating gates as illustrated in logic block 1215 and a second conductive path is formed between the second drain and second source as illustrated by logic block 1216. Also similar to method 1200, predetermined voltage values are applied to the first drain, first source and a terminal in programming, erasing and/or reading the non-volatile memory cell.

Integrated circuits described herein may be included in various systems or subsystems such as personal computers, graphics cards, set-top boxes, cable modems, cellular telephones, game consoles, digital television sets (for example, high definition television ("HDTV")), fax machines, cable modems, digital versatile disc ("DVD") players or network routers. Integrated circuits described herein may be housed in a variety of different types of packages having different types of external contacts.

In embodiments, conductive paths described herein may include one or a plurality of wires and/or metal traces/regions/signal lines. Multiple conductive paths may replace a single conductive path illustrated in the figures and a single conductive path may replace multiple conductive paths illustrated in the figures.

It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented) as data and/or instructions embodied in various computer- readable media, in terms of their behavior, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to: formats supporting behavioral languages such as C, Verilog, and HLDL; formats supporting register level description languages like RTL; formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES; and any other suitable formats and languages. Computer- readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.). When received within a computer system via one or more computer-readable media, such data and/or instruction- based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, netlist generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

The foregoing description of the preferred embodiments has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to understand the invention for various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

What is claimed is:

1. A semiconductor device including a non-volatile memory cell, the non-volatile memory cell comprising: a source; a drain; a floating gate; a first metal region coupled to the floating gate; a second metal region coupled to a terminal to receive a control voltage; and a dielectric region formed between the first and second metal regions.

2. The semiconductor device of claim 1 , wherein the first and second metal regions form at least part of a metal fringe capacitor.

3. The semiconductor device of claim 1 , wherein the first metal region is included in a first metal layer, wherein the second metal region is included in a second metal layer, wherein the first and second metal regions are parallel and separated by the dielectric region.

4. The semiconductor device of claim 3, further comprising: a third metal region connected to the first metal region; a fourth metal region connected to the second metal region, wherein the first, second, third and fourth rectangular metal regions form at least part of the metal fringe capacitor.

5. The semiconductor device of claim 1 , wherein the first and second metal regions are included in a metal layer of the semiconductor device.

6. The semiconductor device of claim 1 , wherein the nonvolatile memory cell is one of a plurality of non-volatile memory cells that store values for the semiconductor device, the values being selected from the group consisting of transmit equalization coefficients, receive equalization coefficients, at least part of an initialization/boot code, a chip identification code, values for training the semiconductor device, values for adjusting settings of the semiconductor device, values for trimming settings of the semiconductor device, and combinations thereof.

7. The semiconductor device of claim 1 , further comprising: a CMOS circuit including CMOS transistors each having a source, a drain and a gate, the CMOS circuit further including metal lines interconnecting the CMOS transistors, wherein the source, drain and floating gate of the non-volatile memory cell are formed in the same process steps in which the sources, drains, and gates of at least some of the CMOS transistors are formed, and wherein the first and second metal regions of the respective non-volatile memory cell are formed in the same process steps in which at least some of the metal lines are formed.

8. The semiconductor device of claim 7, wherein the CMOS circuit includes logic to retrieve a value stored in the non-volatile memory cells.

9. The semiconductor device of claim 1 , wherein the non-volatile memory cell is one of a plurality of non-volatile memory cells forming an array selected from the group consisting of NAND, AND and NOR memory arrays, wherein the array includes word lines and bit lines and wherein the terminal is coupled to a word line and the drain is coupled to a bit line.

10. The semiconductor device of claim 1 , further comprising: a contact region connecting the first metal region to the floating gate.

1 1. A semiconductor device including a non-volatile memory cell, the non-volatile memory cell comprising: a source; a drain; a first gate; a first diffusion region; a second diffusion region having the same polarity as the first diffusion region; a second gate coupled the first gate; and a terminal, coupled to the first and second diffusion regions, to provide a control voltage.

12. The semiconductor device of claim 1 1 , wherein the source and drain are formed in a P-WeII region, wherein the first and second diffusion regions are formed in an N-WeII region.

13. The semiconductor device of claim 1 1 , further comprising: a CMOS circuit including CMOS transistors each having a source, a drain and a gate, wherein the source, drain, and first and second diffusion regions of the respective non-volatile memory cell are formed in the same process steps in which the sources and drains of the CMOS transistors are formed.

14. The semiconductor device of claim 13, wherein the CMOS circuit includes logic to retrieve a value stored in the non-volatile memory cells.

15. The semiconductor device of claim 1 1 , wherein the non-volatile memory cell is one of a plurality of non-volatile memory cells forming an array selected from the group consisting of NAND, AND and NOR memory arrays, wherein the array includes word lines and bit lines and wherein the terminal is coupled to a word line and the drain is coupled to a bit line.

16. The semiconductor device of claim 1 1 , wherein the nonvolatile memory cell is one of a plurality of non-volatile memory cells that store values for the semiconductor device, the values being selected from the group consisting of transmit equalization coefficients, receive equalization coefficients, at least part of an initialization/boot code, a chip identification code, values for training the semiconductor device, values for adjusting settings of the semiconductor device, values for trimming settings of the semiconductor device, and combinations thereof.

17. A method to manufacture a semiconductor device having a non-volatile memory cell, the method comprising: forming a floating gate of the nonvolatile memory cell; forming a first metal region coupled to the floating gate; forming a dielectric region; forming a second metal region separated from the first metal region by the dielectric region, and forming a terminal coupled to the second metal region to receive a control voltage.

18. The method of claim 17, wherein the method is performed using one or more CMOS manufacturing process steps to provide a single monolithic integrated circuit including the non-volatile memory cell and a CMOS circuit.

19. The method of claim 17, further comprising: applying a voltage to the terminal to cause the floating gate to be charged to represent a stored value through a mechanism selected from the group consisting of Fowler-Nordheim tunneling and hot electron injection.

20. A method to manufacture a semiconductor device, the method comprising: forming a first drain; forming a first source; forming a first diffusion region; forming a second diffusion region; forming a first gate between the first drain and first source; forming a second gate between the first and second diffusion regions; forming a first conductive path between the first and second gates; and forming a second conductive path between the first and second diffusion regions and a terminal to provide a control voltage.

21. Machine-readable media to store executable instructions that represent a semiconductor device, the represented semiconductor device including non-volatile memory cells, a respective non-volatile memory cell comprising: a source; a drain; a floating gate; a first metal region coupled to the floating gate; a second metal region coupled to a terminal to receive a control voltage; and a dielectric region formed between the first and second metal regions.