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WO2008062515A1 - Système de fabrication de semiconducteurs - Google Patents

Système de fabrication de semiconducteurs Download PDF

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Publication number
WO2008062515A1
WO2008062515A1 PCT/JP2006/323209 JP2006323209W WO2008062515A1 WO 2008062515 A1 WO2008062515 A1 WO 2008062515A1 JP 2006323209 W JP2006323209 W JP 2006323209W WO 2008062515 A1 WO2008062515 A1 WO 2008062515A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor manufacturing
bay
controller
scheduling
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2006/323209
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English (en)
Japanese (ja)
Inventor
Tatsushi Iimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SYSTEMV MANAGEMENT Inc
Original Assignee
SYSTEMV MANAGEMENT Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SYSTEMV MANAGEMENT Inc filed Critical SYSTEMV MANAGEMENT Inc
Priority to JP2008545273A priority Critical patent/JP5075835B2/ja
Priority to PCT/JP2006/323209 priority patent/WO2008062515A1/fr
Publication of WO2008062515A1 publication Critical patent/WO2008062515A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10P72/3304—
    • H10P72/0464—
    • H10P72/0612—

Definitions

  • Patent Document 2 JP 2005-197521
  • Patent Document 4 Japanese Patent Laid-Open No. 2001-143979
  • Patent Document 5 Japanese Patent Application Laid-Open No. 11-145022
  • Patent Document 6 Japanese Patent Laid-Open No. 7-237095
  • the invention disclosed in the above patent document discloses a semiconductor manufacturing system using a flow shop system, and by using this system, the problems caused by the conventional job shop system can be solved.
  • a sufficiently short TAT can still be realized for a semiconductor production line that requires a short lot and a variety of small lots such as SOC. ⁇ .
  • the next processing step is started by an event based on a request from each semiconductor manufacturing apparatus, so that the conveyance efficiency is poor.
  • the processing time is determined by the processing time in the apparatus and the transport time to the semiconductor manufacturing apparatus that performs the next processing step. Since the processing time in the equipment depends on the specifications of the semiconductor manufacturing equipment, the processing time will not be shortened unless the semiconductor manufacturing equipment is improved. However, the conveyance time can be improved.
  • the conventional process has an event-type processing structure based on the demands of semiconductor manufacturing equipment as described above. Therefore, when a mounting Z removal request from a certain semiconductor manufacturing equipment triggers, transportation is started. The Rukoto. Therefore, means for solving the problem that waste is still occurring in the transport time
  • a control instruction is sent to the inter-bay transfer device, and the bay controller sends a control instruction to the semiconductor manufacturing apparatus and the intra-bay transfer device based on scheduling in the scheduler, Scheduling calculates the number of installed units and the number of flow steps for each of the semiconductor manufacturing apparatuses based on the operating rate of the lithography apparatus among the semiconductor manufacturing apparatuses, and is set based on the calculated number of installed units and the number of flow steps. It is a semiconductor manufacturing system.
  • the semiconductor manufacturing system can be a system based on scheduling. This makes it possible to achieve a shorter TAT than the conventional event type.
  • the number of installations, the number of flow steps, and the like are calculated based on the lithography apparatus during this scheduling, it is possible to make maximum use of an expensive and high-throughput lithography apparatus.
  • the flow shop controller and the bay controller are one or more of the semiconductor manufacturing apparatus, the intra-bay transfer apparatus, the bay, and the inter-bay transfer apparatus.
  • the flow shop controller receives one or more pieces of information of failure information, recovery information, and remaining processing time information, and the flow shop controller performs rescheduling at the timing of accessing the entrance of the flow shop.
  • This is a semiconductor manufacturing system that performs rescheduling at the timing of accessing the entrance of the bay.
  • each scheduler executes rescheduling at a predetermined timing. As a result, various kinds of information can be received in real time, and it becomes possible to flexibly cope with failures of semiconductor manufacturing equipment.
  • a semiconductor manufacturing system in which a shorter TAT is realized can be realized by using a conventional scheduling method that does not use the event type. Also, because scheduling is performed, no unnecessary WiP (Work in Progress) occurs.
  • FIG. 1 is a diagram schematically showing an example of a semiconductor manufacturing system according to the present invention.
  • FIG. 2 is a diagram schematically showing an example of a semiconductor manufacturing system when a belt conveyor is used as an inter-pay transport device.
  • FIG. 7 is a diagram schematically showing a case where an assumed operating rate is set for each semiconductor manufacturing apparatus.
  • FIG. 9 is a diagram schematically showing a case where the throughput on the four powers for each semiconductor manufacturing apparatus is calculated.
  • the semiconductor manufacturing system 1 has a plurality of pays 2 and an inter-pay transport device 3 for transporting between the pay bays.
  • the bay 2 includes at least one semiconductor manufacturing apparatus 21 that performs processing of each process in the wiring process of semiconductor manufacturing, and an intra-pay transfer apparatus that transfers between the semiconductor manufacturing apparatuses 21 in the bay 2.
  • the semiconductor manufacturing system 1 has a computer system called a flow shop controller that controls the transfer between the bay 2 and the bay, and the flow shop controller has a scheduler that schedules the transfer between the bay 2 and the bay. It has been.
  • Each bay 2 has its bay 2
  • the bay controller is equipped with a computer system called a bay controller that controls the semiconductor manufacturing device 21 and the bay transport device 22 in the bay.
  • the bay controller includes the semiconductor manufacturing device 21 and the bay transport device 22 in the bay 2. There is a schedule ruler for scheduling.
  • Predetermined data communication is possible between the bay controller and the intrabay transport controller. Therefore, the transfer command from the bay controller to the transfer controller in the bay, the transfer response to the transfer controller in the bay, the transfer response to the bay controller, the transfer robot in the bay 22 from the transfer controller in the bay to the bay controller Location information reports are performed.
  • each bay 2 includes the semiconductor manufacturing apparatus 21 and the intra-bay transfer apparatus 22, but various semiconductor manufacturing apparatuses 21 can be used for the semiconductor manufacturing apparatus 21.
  • various semiconductor manufacturing apparatuses 21 can be used for the semiconductor manufacturing apparatus 21.
  • lithography equipment (“litho” in FIG. 1) etching equipment (“etch” in FIG. 1), CVD (chemical vapor deposition) equipment (“CVD” in FIG. 1), inspection equipment (“inspection” in FIG. 1) ), Cleaning device (“Clean” in FIG. 1), annealing device (“Annel” in FIG. 1), PVD (Physical Vapor Deposition) device (“PVD” in FIG. 1), and measuring device (“Meching” in FIG. 1). )
  • Each semiconductor manufacturing apparatus 21 is provided with at least one load port for carrying out carrier loading / unloading Z with the in-pay transport apparatus 22.
  • the intra-bay transfer device 22 has a mechanism that can continuously carry out the carrier loading Z removal with the inter-bay buffer 4 and the load port of the semiconductor manufacturing device 21. For example, there are two arms in the transfer device 22 in the bay, the carrier that has been processed by one arm is taken out (received) from the semiconductor manufacturing device 21, and the carrier that has been transferred by the other arm is mounted (delivered) There is a mechanism.
  • the inter-bay transfer device 3 for transferring between the bays is shown using a transfer robot.
  • the inter-bay buffer 4 may be a transfer device on a belt conveyor.
  • the inter-bay transport places the processed carrier in the inter-bay buffer 4 and the intra-bay transport device 22 is equipped with a carrier that performs the next processing from the inter-bay buffer 4. By doing so, it can also be configured to realize the inter-bay conveyance.
  • the lithographic apparatus power used in the lithographic process S is the most expensive and has other throughputs. Higher than 21. Therefore, it is necessary to set the lithographic apparatus to have the highest operating rate based on investment efficiency.
  • the general wiring process as shown in FIG. 6, there are two lithographic processes, so two lithography apparatuses are required.
  • a processing number ratio is set that indicates how many of the mounted carriers are actually processed. This is because, in a general processing process in the wiring process, not all carriers are inspected in a force inspection process that processes all carriers, so the processing number ratio is set.
  • Figure 8 shows how this is set. Fig. 8 shows the case where the ratio of the number of processed sheets per 25 sheets is set. This is because one carrier is often composed of 25 sheets.
  • the necessary number of installed semiconductor manufacturing apparatuses 21 can be calculated as the number of installations satisfying Equation 2.
  • FIG. 10 shows the required number of installed semiconductor manufacturing apparatuses 21 used for each processing step. By performing the above processing, the required number of installed semiconductor manufacturing devices 21 can be calculated. Next, a process for determining the number of flow steps will be described.
  • t be the maximum value of the transfer time between devices by the transfer device 22 in the bay (t includes the time for taking out the carrier loaded Z with the semiconductor manufacturing device 21). If the throughput of each semiconductor manufacturing apparatus 21 is P (Wph), the processing time per one is 3600 ZP (seconds). In the process of determining the required number of installed semiconductor manufacturing apparatuses 21 described above, the models other than the lithography apparatus are set to have a larger throughput than the lithography apparatus (from Expression 2). 21 is a lithography apparatus.
  • Equation 3 the number of flow steps that satisfies Equation 3 is determined.
  • the transfer time between apparatuses is 10 seconds and each processing step is performed in the order of a CVD apparatus, a lithography apparatus, an annealing apparatus, a CMP apparatus, a cleaning apparatus, an etching apparatus, and an inspection apparatus (inspection 1)
  • the throughput is 60 Wph based on the throughput values shown in FIG. In other words, the processing time per sheet is 60 seconds.
  • Equation 3 it can be calculated from Equation 3 that the number of flow steps is 6. That is, in each processing step, six semiconductor manufacturing apparatuses 21 can be constructed to be transported by one intra-bay transport apparatus 22. This is schematically shown in Fig. 11.
  • the number of semiconductor manufacturing apparatuses 21 in charge of transport is inevitably determined by one in-bay transport apparatus 22, and therefore, how many semiconductor manufacturing apparatuses are in each bay 2. 21 can be installed, ie the layout is determined.
  • the in-bay transfer device 22 sequentially removes the carrier from each semiconductor manufacturing device 21 on the basis of a preset schedule. t Shift the time.
  • the subsequent carrier can be delivered at the timing of completion of the processing of the preceding carrier, and the apparent carrier time is the first carrier for each semiconductor manufacturing device. Except for the time to pass to 21 and the transport time to return the last carrier, it will be almost concealed.
  • Information that is the basis of scheduling is set as described above.
  • scheduling is set by the scheduler of the flow shop controller and the scheduler of the bay controller so that the transport time is concealed. Then, based on the scheduler of the flow controller, instructions related to the control processing in each bay 2 and instructions related to the control processing of the inter-bay transport device 3 are sent to the flow shop controller bay controller and inter-bay transport.
  • the bay controller controls the bay 2 based on the instruction, and the inter-pay transport controller controls the inter-pay transport device 3.
  • the bay controller sends instructions regarding control processing in the semiconductor manufacturing apparatus 21 in the bay 2 and instructions regarding control processing in the intra-pay transport apparatus 22 based on the scheduler of the bay controller. Based on the instruction, the apparatus controller controls the semiconductor manufacturing apparatus 21 and the intra-pay transport controller controls the intra-pay transport apparatus 22.
  • the scheduling in the bay controller and the flow shop controller only powers the same algorithm at different levels, so in the case of processing in the inter-bay transport device 3, the intra-bay transport device described above.
  • the processing in 22 can be similarly set by replacing the intra-bay transport device 22 with the inter-bay transport device 3 and the semiconductor manufacturing device 21 with the bay 2.
  • the semiconductor manufacturing system 1 By operating the semiconductor manufacturing system 1 using the scheduler set as described above, the semiconductor manufacturing system 1 with a shorter TAT than the conventional event-type semiconductor manufacturing system 1 is realized. I can do it.
  • the CMP apparatus has a throughput of 30 Wph, and the other semiconductors.
  • the body manufacturing apparatus 21 is 60 Wph.
  • the flattening of the processing time can be determined by the same method as the necessary algebra determination processing for each semiconductor manufacturing apparatus 21 as described above.
  • only the throughput of the CMP apparatus is affected by the other apparatus. Therefore, if two CMP devices are installed, the processing time can be flattened.
  • the throughput is 1Z3
  • three semiconductor manufacturing apparatuses 21 may be installed, and when the throughput is 1Z4, four semiconductor manufacturing apparatuses 21 may be installed.
  • the intra-bay transfer apparatus 22 sequentially transfers the carriers.
  • the in-bay transport apparatus 22 transports the carrier alternately to the two transport apparatuses.
  • the waiting time on the load port in the semiconductor manufacturing equipment 21 after processing is eliminated by alternately transferring to the three units and transferring to four units when four units are installed. I can do it.
  • rescheduling is performed at a predetermined timing.
  • Semiconductor manufacturing apparatus 21 May stay at the load port. The rescheduling in that case will be described.
  • FIG. 14 schematically shows this.
  • each semiconductor manufacturing apparatus 21 reports information on the remaining processing time of each process to the bay controller, and using this time information, the transport scheduling of the intra-pay transport apparatus 22 is performed.
  • a treatment method will be described in which the semiconductor manufacturing apparatus 21 does not stay on the load port even when a failure occurs.
  • GEM300 defined in SEMI Standard
  • each semiconductor manufacturing equipment 21 reports information on the remaining processing time of each process to the bay controller. To be configured.
  • the bay controller monitors the remaining processing time in each semiconductor manufacturing apparatus 21 and should not stay on the load port of the semiconductor manufacturing apparatus 21. Judgment is made as to whether or not the delivery is in time, and if it is judged that it is not in time, processing for changing the scheduling is performed. In the changed scheduling at this time, the retention on the load port is eliminated by performing a process of giving priority to the transfer in the semiconductor manufacturing apparatus 21 that should not stay.
  • the bay controller determines that the bay controller is not in time, if the in-bay transport apparatus 22 already has a carrier to be transported to another semiconductor manufacturing apparatus 21, priority transport cannot be performed. Therefore, if it is determined that the intra-bay transport device 22 is not in time before the access timing to the inter-bay noffer 4, it is set so that no carrier is taken from the inter-bay noffer 4. However, if it has already passed through the entrance of the bay 2, the carrier 22 in the bay needs to place this carrier in the inter-bay buffer 4 in this case. Accordingly, the determination timing is a time including this time. In the case of Figure 14, it shows the case where the time between the annealing apparatus and the CMP apparatus is constant even if a failure occurs in the lithography apparatus!
  • the semiconductor manufacturing system 1 in the flow shop method capable of processing with a shorter TAT than the conventional event type semiconductor manufacturing system 1 can be realized.
  • the semiconductor manufacturing system 1 in which a shorter TAT is realized can be realized by using a conventional scheduling method that does not use the event type. . Schedule again!
  • the flow shop controller and the bay controller can perform real-time processing by performing rescheduling at each timing. And since it is real-time processing, interrupt processing can be realized in an efficient state. That is, the shortest HotLot can be realized.

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

L'invention concerne un système de fabrication de semiconducteurs employant un système d'atelier de production en continu pour obtenir un délai d'exécution court lors de la fabrication de semiconducteurs dans une installation correpondante. Le système de fabrication de semiconducteurs est pourvu de plusieurs appareils de transfert de baies et entre baies. Le système de fabrication de semiconducteurs est également pourvu d'un dispositif de commande de fabrication en continu ayant un programmateur pour effectuer la programmation pour le transfert des baies et entre baies. La baie est pourvue d'un dispositif de commande de baie ayant un programmateur pour effectuer la programmation pour l'appareil de fabrication de semiconducteurs et un appareil de transfert entre baies. Le dispositif de commande de fabrication en continu transmet une instruction de commande sur la base de la programmation, et le dispositif de commande de baie transmet une instruction de commande sur la base de la programmation. La programmation est définie sur la base de la vitesse de fonctionnement d'un appareil de lithographie prise comme référence et du calcul du nombre d'appareils de lithographie destinés à chaque appareil de fabrication de semiconducteurs et du nombre d'opérations de fabrication en continu.
PCT/JP2006/323209 2006-11-21 2006-11-21 Système de fabrication de semiconducteurs Ceased WO2008062515A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008545273A JP5075835B2 (ja) 2006-11-21 2006-11-21 半導体製造システム
PCT/JP2006/323209 WO2008062515A1 (fr) 2006-11-21 2006-11-21 Système de fabrication de semiconducteurs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/323209 WO2008062515A1 (fr) 2006-11-21 2006-11-21 Système de fabrication de semiconducteurs

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WO2008062515A1 true WO2008062515A1 (fr) 2008-05-29

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225992A (ja) * 2009-03-25 2010-10-07 Dainippon Screen Mfg Co Ltd 基板処理装置のスケジュール作成方法及びそのプログラム
JP2010238919A (ja) * 2009-03-31 2010-10-21 Dainippon Screen Mfg Co Ltd 基板処理装置のスケジュール作成方法及びそのプログラム
CN114500488A (zh) * 2022-01-05 2022-05-13 珠海埃克斯智能科技有限公司 半导体清洗设备通讯方法、系统以及计算机可读存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751580A (en) * 1996-07-26 1998-05-12 Chartered Semiconductor Manufacturing, Ltd. Fuzzy logic method and system for adjustment of priority rating of work in process in a production line
JPH11145022A (ja) * 1997-11-13 1999-05-28 Matsushita Electron Corp 半導体製造設備
JP2002026106A (ja) * 2000-07-07 2002-01-25 Matsushita Electric Ind Co Ltd 半導体装置製造施設
JP2005190031A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体デバイス製造におけるボトルネック発生回避方法およびシステム
JP2006269449A (ja) * 2005-03-22 2006-10-05 Renesas Technology Corp 半導体製造システム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751580A (en) * 1996-07-26 1998-05-12 Chartered Semiconductor Manufacturing, Ltd. Fuzzy logic method and system for adjustment of priority rating of work in process in a production line
JPH11145022A (ja) * 1997-11-13 1999-05-28 Matsushita Electron Corp 半導体製造設備
JP2002026106A (ja) * 2000-07-07 2002-01-25 Matsushita Electric Ind Co Ltd 半導体装置製造施設
JP2005190031A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体デバイス製造におけるボトルネック発生回避方法およびシステム
JP2006269449A (ja) * 2005-03-22 2006-10-05 Renesas Technology Corp 半導体製造システム

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225992A (ja) * 2009-03-25 2010-10-07 Dainippon Screen Mfg Co Ltd 基板処理装置のスケジュール作成方法及びそのプログラム
JP2010238919A (ja) * 2009-03-31 2010-10-21 Dainippon Screen Mfg Co Ltd 基板処理装置のスケジュール作成方法及びそのプログラム
CN114500488A (zh) * 2022-01-05 2022-05-13 珠海埃克斯智能科技有限公司 半导体清洗设备通讯方法、系统以及计算机可读存储介质
CN114500488B (zh) * 2022-01-05 2023-09-15 珠海埃克斯智能科技有限公司 半导体清洗设备通讯方法、系统以及计算机可读存储介质

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JPWO2008062515A1 (ja) 2010-03-04
JP5075835B2 (ja) 2012-11-21

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