WO2008044750A1 - Low-noise amplifier - Google Patents
Low-noise amplifier Download PDFInfo
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- WO2008044750A1 WO2008044750A1 PCT/JP2007/069901 JP2007069901W WO2008044750A1 WO 2008044750 A1 WO2008044750 A1 WO 2008044750A1 JP 2007069901 W JP2007069901 W JP 2007069901W WO 2008044750 A1 WO2008044750 A1 WO 2008044750A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
- H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/144—Indexing scheme relating to amplifiers the feedback circuit of the amplifier stage comprising a passive resistor and passive capacitor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/156—One or more switches are realised in the feedback circuit of the amplifier stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/252—Multiple switches coupled in the input circuit of an amplifier are controlled by a circuit, e.g. feedback circuitry being controlling the switch
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Definitions
- the present invention relates to a low-noise amplifier, and is particularly suitable for use in a source-grounded low-noise amplifier having a feedback circuit.
- a radio receiver such as a radio receiver or a television receiver uses an amplifier that amplifies a weak high-frequency signal received by an antenna.
- L N A Low Noise Amplifier
- L N A can be broadly divided into types that do not constitute a feedback circuit and types that constitute a feedback circuit.
- the input resistance becomes high impedance, so when connecting an antenna circuit to such L N A, it is necessary to perform impedance matching using an input transformer or the like.
- the desired input impedance can be obtained by using the feedback type configuration, it is possible to directly connect the antenna circuit and LNA without using an input transformer or the like.
- FIG. 1 is a diagram showing a configuration example of a conventional feedback LNA.
- the conventional LNA shown in Figure 1 has a source grounded transistor (input transistor) N 1 connected between the signal input terminal IN and output terminal OUT, and the input terminal IN and output.
- the feedback resistor RN and capacitor CN connected to the terminal OUT It is configured with.
- Source ground Transistor N 1 gate is connected to signal input i IN via capacitor C 1 and drain is connected to signal output terminal o UT Source ground transistor N 1 drain Is connected to the power supply VDD via the load resistor RL.
- Transistor N 2 and current source transistor 1 constitute a current mirror circuit. That is, the gate of transistor N 2 is diode-connected to its drain and the source ground transistor N
- a radio receiver normally has an AGC (Automatic Gain Control) circuit power S to adjust the gain of the received signal.
- the RF (Radio Frequency) A G C circuit adjusts the gain of the high-frequency signal received by the antenna and keeps the level of the received signal constant.
- the R F—A G C circuit does not operate unless the field strength of the antenna input signal is greater than the threshold, and does not reduce the gain of the received signal. However, if a signal with a strong electric field is input to the antenna and the electric field strength exceeds the threshold, excessive power is applied to the wireless receiver by operating the RF-AGC circuit and reducing the gain of the received signal. Try not to. This la la r F-
- AGC The operation of AGC can be realized by controlling the gain of LNA, for example.
- the LNA gain (by the control voltage applied from the control terminal PG to the gate of the transistor N2 via the resistor R1)
- the gain of the received signal is variable. Specifically, it is usually set so that the gain of the LNA is maximized, and when a large level signal is input, the control voltage is changed according to the level, so that the LNA gain is appropriately adjusted. The value is lowered to a reasonable value.
- a high-frequency amplifier circuit that makes the gain variable by switching the level of the gate voltage of the transistor is also disclosed in Patent Document 1, for example.
- Patent Document 1 FIG. 3 of Japanese Patent Laid-Open No. 8-30 17 15
- Patent Document 2 FIG. 2 1 of the Japanese Patent Application Laid-Open No. 2000-26 6 30 09
- the gain of the amplifier can be controlled by controlling the source resistance as in Patent Document 2.
- the open-circuit gain of the amplifier changes when the source resistance is changed, which reduces the dynamic range of the input transistor. For this reason, there is a problem that a desired signal-to-noise ratio with excellent linearity cannot be realized.
- the field ⁇ using the amplifier of Patent Document 2 for F ⁇ radio receivers> LNA, etc. of the machine, and the impedance matching between the NA and the antenna input circuit from the viewpoint of noise figure can be realized by resistance.
- an impedance matching is required by tuning to the frequency of the desired station that is rarely received from multiple stations.
- the configuration of the receiver becomes complicated.
- the present invention has been made to solve such problems.
- the receiver configuration is not complicated, and the input dynamics of the amplifier can be obtained even when a large level signal is input.
- the purpose is to achieve a desired signal-to-noise ratio with excellent linearity by preventing the range from decreasing.
- a source-grounded amplifier including a source-grounded transistor in which a gate is connected to a signal input terminal
- the signal input terminal is connected to the output terminal.
- a plurality of feedback resistors' and a switch for selecting one of the plurality of feedback resistors are selected, and gain control is performed by selecting one of the feedback resistors by switching the switch. I am trying to do it.
- the gain is controlled by switching the feedback resistance of the feedback amplifier, instead of switching the gate voltage and source resistance of the ranstar.
- the gate bias voltage of the input transistor is constant, the drain current is constant, and the open-circuit gain of the amplifier does not change by switching the feedback resistor.
- the input dyna The linearity can be improved by suppressing the decrease of the microphone range, and the desired signal-to-noise ratio can be realized.
- the input impedance can be set to a desired value by configuring a feedback amplifier with multiple feedback resistors selectable, eliminating the need for a matching circuit using an LC circuit.
- the configuration of a receiver using an amplifier can be simplified.
- FIG. 1 is a diagram showing the configuration of a conventional LNA.
- FIG. 2 is a diagram showing a configuration example of LNA according to the present embodiment.
- FIG. 3 is a diagram showing another configuration example of LNA according to the present embodiment.
- FIG. 4 is a diagram showing another configuration example of the feedback resistor and the analog switch used in the present embodiment. Best Mode for Invention
- FIG. 2 is a diagram showing a configuration example of LNA according to the present embodiment. Please refer to Fig. 2.
- N 1 is a common-source input transistor, and its gate is connected to the signal input terminal IN through the capacitor C 1, the source is connected to the drain, and the drain is the signal output. Connected to terminal OUT.
- R is a load resistance, and is connected between the output (K line) of the common source transistor N 1 and the power source V DD.
- N 2 is a transistor that forms a current mirror circuit together with the source ground transistor N 1. That is, the gate of transistor N 2 is diode-connected to its own drain and source grounded transistor N Connected to 1 gate via resistor R2. The drain of transistor N 2 is connected to power supply VDD through resistor R 1 and the source is connected to ground. By configuring the current mirror circuit in this way, the drain current flowing through the source grounded transistor N 1 is determined by the size ratio of the source grounded transistor N 1 and the transistor N 2.
- a feedback circuit is provided between the signal output terminal OU T (drain of the common source transistor N 1) and the signal input terminal I N (gate of the common source transistor N 1).
- the feedback circuit includes a plurality of feedback resistors RN 1, RN 2,..., RN n (where n is an integer greater than or equal to 2) provided in parallel between the signal input terminal IN and the output terminal OUT, .., ASW n, which are connected in series to the feedback resistors RN 1 to RN n, respectively, of the analog switches A SW l, A SW 2,.
- the resistance values of the plurality of feedback resistors R N l to R N n are different.
- the plurality of analog switches ASW 1 to AS Wn are turned on / off by the control voltage applied from the control terminals PG 1 to PG n, and only one of them is selectively turned on. It has become so.
- the gate bias voltage of the common source transistor N 1 is constant when the gain of L N A is changed.
- the analog switches ASW l to ASW n are turned on / off to selectively select one of the feedback resistors RN 1 to RN n connected in series with the analog switches ASW l to ASW n. By using it, LNA gain control is performed.
- Is supplied to L N A This is when impedance matching is achieved.
- the resistance values of the feedback resistors RN1 to RNn are set so that the value of the input impedance Ri is 1.5 Rs at the maximum, the loss due to impedance mismatch Is almost negligible.
- the feedback circuit is constituted by a plurality of feedback resistors RN 1 to RN n, and any of them is selected.
- An analog switch ASW l to ASW n is provided to select either of them, and the LNA gain is controlled by selecting one of the feedback resistors.
- the gain is controlled by switching the feedback resistance value of the feedback amplifier, the gate bias voltage of the source grounded transistor N1, which is the input transistor, is constant, and the drain current is constant. .
- switching the feedback resistance value does not change the open gain of the LNA. others Therefore, even when a large level of signal is input, the desired signal-to-noise ratio with excellent linearity can be realized by suppressing the decrease of the input dynamic range of the LNA. In particular, the signal-to-noise ratio can be improved when two interference signals are input.
- a plurality of feedback resistors RN l to RN n having different resistance values are provided as a feedback circuit, and any one of these is selected and connected.
- the input impedance of the LNA can be set to a desired value. This eliminates the need for a matching circuit using an LC circuit and simplifies the configuration of a receiver using an LNA.
- FIG. 3 is a diagram showing another configuration example of the LNA according to the present embodiment.
- the amplification stage is composed of two transistors connected in cascade. In this case, a feedback circuit is provided from the output (drain) of the gate ground transistor located above the cascode connection to the signal input terminal I N.
- N 3 is a gate-grounded transistor, which is cascade-connected to the source-grounded transistor N 1 and has its drain connected to the signal output terminal OU T.
- the drain of the gate ground transistor N 3 is also connected to the power supply V DD via the load resistor R L.
- the common source transistor N 1 functions as a first-stage amplifier, and the common gate transistor N 3 functions as a next-stage amplifier.
- N 4 and N 5 are transistors constituting the bias circuit, and determine the bias of the gate ground transistor N 3.
- One end of this bias circuit is connected to the power supply VDD via the resistor R3, and the other end is connected to the ground.
- Other configurations are the same as those in FIG.
- Cascade connection of the registers Nl and N3 makes it possible to obtain a stable gain over a wide band.
- a configuration has been described in which a plurality of feedback resistors R N1 to R N n having different resistance values are provided in parallel and any one of them is selected.
- the present invention is not limited to this.
- a plurality of feedback resistors RN l to RN n and a plurality of analog switches A SW l to A SWn are connected in a ladder shape, and one of the analog switches A SW l to A SWn is connected.
- the combined resistance value of one or more feedback resistors may be made variable.
- the resistance values of the plurality of feedback resistors R N l to R N n may be different from each other or the same.
- the present invention is useful for a common source low noise amplifier having a feedback circuit.
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Abstract
Description
明 細 書 低雑音増幅器 技術分野 Description Low Noise Amplifier Technical Field
'本発明は低雑音増幅器に関し、 特に、 帰還回路を有するソース接地型 の低雑音増幅器に用いて好適なものである。 背景技術 'The present invention relates to a low-noise amplifier, and is particularly suitable for use in a source-grounded low-noise amplifier having a feedback circuit. Background art
一般に、 ラジオ受信機やテ レビ受像機などの無線受信機では、 アンテ ナで受信した微弱な高周波信号を増幅する増幅器が用いられる。 ただし 、 増幅の際に増幅器から出力されるノイズが大きく なると、 受信機の感 度が悪化してしま う。 そこで、 受信機の増幅器には、 ノイズの発生が少 ない L N A (Low Noise Amplifier: 低雑音増幅器) が用いられることが 多レ、。 In general, a radio receiver such as a radio receiver or a television receiver uses an amplifier that amplifies a weak high-frequency signal received by an antenna. However, if the noise output from the amplifier increases during amplification, the sensitivity of the receiver will deteriorate. Therefore, L N A (Low Noise Amplifier), which generates less noise, is often used as the receiver amplifier.
L N Aは大別して、 帰還回路を構成しないタイプと、 帰還回路を構成 するタイプとがある。 帰還回路を構成しない L N Aの場合、 入力抵抗は ハイインピーダンスになるため、 そのよ うな L N Aにアンテナ回路を接 続するときは、 入力 トランス等を用いてインピーダンス整合を行う必要 が出てく る。 一方、 帰還型の構成にすることによ り、 所望の入力インピ —ダンスを得ることができるので、 入力 トランス等を介さずにアンテナ 回路と L N Aとを直接接続することが可能となる。 L N A can be broadly divided into types that do not constitute a feedback circuit and types that constitute a feedback circuit. In the case of L N A that does not constitute a feedback circuit, the input resistance becomes high impedance, so when connecting an antenna circuit to such L N A, it is necessary to perform impedance matching using an input transformer or the like. On the other hand, since the desired input impedance can be obtained by using the feedback type configuration, it is possible to directly connect the antenna circuit and LNA without using an input transformer or the like.
図 1は、 従来の帰還型 L N Aの構成例を示す図である。 図 1 に示す従 来の L N Aは、 信号の入力端 I Nと出力端 O U Tとの間に接続されたソ —ス接地ト ラ ンジス タ (入力 ト ラ ンジス タ) N 1 と、 入力端 I Nと出力 端 O U Tとの間に接続された帰還用の抵抗 R Nおよびキャパシタ C Nと を備えて構成されている。 FIG. 1 is a diagram showing a configuration example of a conventional feedback LNA. The conventional LNA shown in Figure 1 has a source grounded transistor (input transistor) N 1 connected between the signal input terminal IN and output terminal OUT, and the input terminal IN and output. The feedback resistor RN and capacitor CN connected to the terminal OUT It is configured with.
ソ ス接地 トランジスタ N 1のゲ トはキャパシタ C 1 を介して信号 入力 i I Nに接続され、 ド レイ ンは信号出力端 o U Tに接続されている よ ソース接地 ト ラ ンジスタ N 1 の ド レイ ンは、 負荷抵抗 R Lを介 して電源 V D Dにも接続されている ソ ス接地 ト ラ ンジスタ N 1 のソ Source ground Transistor N 1 gate is connected to signal input i IN via capacitor C 1 and drain is connected to signal output terminal o UT Source ground transistor N 1 drain Is connected to the power supply VDD via the load resistor RL.
—スはグラン ドに接続されている。 —S is connected to ground.
卜ランジスタ N 2は、 ソース接地 ランジスタ 1 と共に電流ミ ラー 回路を構成している。 すなわち、 トランジスタ N 2のゲー トが、 自身の ドレインにダイォー ド接続されると と もに、 ソ一ス接地トランジスタ N 卜 Transistor N 2 and current source transistor 1 constitute a current mirror circuit. That is, the gate of transistor N 2 is diode-connected to its drain and the source ground transistor N
1 のゲ一トに抵抗 R 2を介して接続されている。 トランジスタ N 2のソConnected to the gate of 1 through resistor R2. Transistor N 2
—スはグラン ドに接続されている。 このよ うに電流ミ ラー回路を構成す ることによ り、 ソース接地トランジスタ N 1 と トランジスタ N 2 とのサ ィズ比で 、 ソース接地トランジスタ N 1 を流れる ド レイ ン電流が決まる と ころで、 無線受信機では通常、 受信信号の利得を調整するために A G C ( Automatic Gain Control) 回路力 S設けられてレ、る。 R F ( Radio Frequency) A G C回路は、 アンテナで受信された高周波信号の利得を調 節して、 受信信号のレベルを一定に保つよ うにするものである。 —S is connected to ground. By configuring the current mirror circuit in this way, the drain current flowing through the common-source transistor N 1 is determined by the size ratio between the common-source transistor N 1 and the transistor N 2. A radio receiver normally has an AGC (Automatic Gain Control) circuit power S to adjust the gain of the received signal. The RF (Radio Frequency) A G C circuit adjusts the gain of the high-frequency signal received by the antenna and keeps the level of the received signal constant.
すなわち、 R F— A G C回路は、 ア ンテナ入力信号の電界強度が閾値 よ り大き く ないと きは動作せず、 受信信号の利得を下げるこ とはない。 しかし 、 ァンテナに強電界の信号が入力されて電界強度が閾値を超える と、 R F - A G C回路が動作して受信信号の利得を下げるこ とによ り 、 無線受信機に過大な電力が加えられないよ うにする 。 このよ ラな R F - In other words, the R F—A G C circuit does not operate unless the field strength of the antenna input signal is greater than the threshold, and does not reduce the gain of the received signal. However, if a signal with a strong electric field is input to the antenna and the electric field strength exceeds the threshold, excessive power is applied to the wireless receiver by operating the RF-AGC circuit and reducing the gain of the received signal. Try not to. This la la r F-
A G Cの動作は、 例えば L N Aの利得を制御するこ とで実現できる。 The operation of AGC can be realized by controlling the gain of LNA, for example.
図 1 に示す従来の L NAでは、 制御端子 P Gから抵抗 R 1 を介して ト ラ ンジスタ N 2のゲー トに印加する制御電圧によって、 L N Aの利得 ( 受信信号の利得) を可変と している。 具体的には、 通常は L N Aの利得 が最大となるよ うに設定しておき、 レベルの大きな信号が入力されたと きに、 そのレベルに応じて制御電圧を変化させることで、 L N Aの利得 を適切な値まで下げるよ うにしている。 このよ うに ト ラ ンジス タのゲ一 ト電圧のレベルを切り替えることによって利得を可変とする高周波増幅 回路は、 例えば特許文献 1 にも開示されている。 In the conventional LNA shown in Fig. 1, the LNA gain (by the control voltage applied from the control terminal PG to the gate of the transistor N2 via the resistor R1) The gain of the received signal is variable. Specifically, it is usually set so that the gain of the LNA is maximized, and when a large level signal is input, the control voltage is changed according to the level, so that the LNA gain is appropriately adjusted. The value is lowered to a reasonable value. A high-frequency amplifier circuit that makes the gain variable by switching the level of the gate voltage of the transistor is also disclosed in Patent Document 1, for example.
特許文献 1 : 特開平 8— 3 0 7 1 5 9号公報の図 3 Patent Document 1: FIG. 3 of Japanese Patent Laid-Open No. 8-30 17 15
利得を可変とする別の方式と して、 増幅器のソース抵抗の大きさを切 り替えることによって利得を可変とする技術も存在する (例えば、 特許 文献 2参照) 。 特許文献 2に記載の可変利得増幅回路では、 複数のソー ス接地増幅回路を構成する複数組の M O S ト ラ ンジス タのソース側に複 数のスィ ツチを接続し、 このスィ ツチによ り何れかの増幅回路を選択し て電圧利得を制御する。 As another method for making the gain variable, there is a technique for making the gain variable by switching the magnitude of the source resistance of the amplifier (see, for example, Patent Document 2). In the variable gain amplifier circuit described in Patent Document 2, a plurality of switches are connected to the source side of a plurality of sets of MOS transistors constituting a plurality of source grounded amplifier circuits. Select the amplifier circuit to control the voltage gain.
特許文献 2 : 特開 2 0 0 4— 2 6 6 3 0 9号公報の図 2 1 発明の開示 Patent Document 2: FIG. 2 1 of the Japanese Patent Application Laid-Open No. 2000-26 6 30 09
しかしながら、 図 1 または特許文献 1 のよ うにゲ一 ト電圧を制御する ことで増幅器の利得を可変とする方式では、 入力 ト ラ ンジス タの ド レイ ン電流が変化するため、 入力 ト ラ ンジス タのダイナミ ック レンジが低下 してしま う。 例えば図 1 の場合、 トランジスタ N 2のゲー ト電圧を変え ると、 電流ミ ラ一の入力回路を構成する ト ラ ンジスタ N 2に流れる基準 電流が変わるため、 出力回路のソース接地 トランジスタ N 1 に流れる ド レイ ン電流も変わってしま う。 このため、 大きなレベルの信号が入力さ れたときの歪み特性が悪化し、 線形性に優れた所望の信号対雑音比を実 現することができないという問題があった。 However, in the method of making the gain of the amplifier variable by controlling the gate voltage as shown in Fig. 1 or Patent Document 1, the drain current of the input transistor changes, so the input transistor is changed. The dynamic range of the camera will be reduced. For example, in the case of Figure 1, changing the gate voltage of transistor N 2 changes the reference current flowing in transistor N 2 that forms the input circuit of the current mirror. The drain current that flows will also change. For this reason, there is a problem that a distortion characteristic when a signal of a large level is inputted deteriorates and a desired signal-to-noise ratio excellent in linearity cannot be realized.
また、 特許文献 2のよ うにソース抵抗を制御するこ とで増幅器の利得 を可変とする方式では、 ソース抵抗を変えたときに増幅器の開放利得が 変化するため、 入力 トランジスタのダイナミ ック レンジが低下してしま う。 このため、 線形性に優れた所望の信号対雑音比を実現するこ とがで きないという問題があった。 Also, the gain of the amplifier can be controlled by controlling the source resistance as in Patent Document 2. In the method with variable, the open-circuit gain of the amplifier changes when the source resistance is changed, which reduces the dynamic range of the input transistor. For this reason, there is a problem that a desired signal-to-noise ratio with excellent linearity cannot be realized.
また 、 特許文献 2の増幅器を F Μラジオ受 >コ機の L N A等に用いた場 α 、 雑音指数の観点からァンテナ入力回路と し N Aとの間のイ ンピーダ ンス整合を抵抗で実現するこ とは困難で、 L c回路を用レ、た トラ ンス 合の整合回路が必要となる この場合、 複数の局の中から受信を希 す る希望局の周波数に同調をとつてィ ンビーダンスマッチングをする手段 が必要となり、 受信機の構成が複雑になるという問題もあった。 In addition, the field α using the amplifier of Patent Document 2 for FΜ radio receivers> LNA, etc. of the machine, and the impedance matching between the NA and the antenna input circuit from the viewpoint of noise figure can be realized by resistance. In this case, an impedance matching is required by tuning to the frequency of the desired station that is rarely received from multiple stations. There is also a problem that the configuration of the receiver becomes complicated.
本発明は、 このよ う な問題を解決するために成されたものであり、 受 信機の構成が複雑にならず、 かつ、 大きなレベルの信号が入力されたと きでも増幅器の入力ダイナミ ック レンジが低下することを抑止して線形 性に優れた所望の信号対雑音比を実現できるよ うにするこ とを目的とす る。 The present invention has been made to solve such problems. The receiver configuration is not complicated, and the input dynamics of the amplifier can be obtained even when a large level signal is input. The purpose is to achieve a desired signal-to-noise ratio with excellent linearity by preventing the range from decreasing.
上記した課題を解決するために 、 本発明では、 信号の入力端にゲー ト が接続されたソース接地 トランジスタを備えたソ ―ス接地型増幅器にお いて、 信号の入力端と出力端との間に、 複数の帰還抵抗'と、 当該複数の 帰還抵抗の中から何れかを選択するスィ クチとを け、 スィ ツチの切り 替えによ り何れかの帰還抵抗を選択するこ とで利得制御を行う よ うにし ている。 In order to solve the above-described problems, in the present invention, in a source-grounded amplifier including a source-grounded transistor in which a gate is connected to a signal input terminal, the signal input terminal is connected to the output terminal. In addition, a plurality of feedback resistors' and a switch for selecting one of the plurality of feedback resistors are selected, and gain control is performed by selecting one of the feedback resistors by switching the switch. I am trying to do it.
上記のよ う に構成した本発明によれば 、 卜ランンスタのゲ一 ト電圧や ソ一ス抵抗を切り替える方式ではなく 、 帰還型增幅器の帰還抵抗を切り 替えて利得を制御しているため、 入力 トランジスタのゲー トバイ アス電 圧は一定で、 ド レイ ン電流は一定となる また、 帰還抵抗の切り替えに よって増幅器の開放利得が変化するこ と ちない。 このため、 入力ダイナ ミ ック レンジの低下を抑止して線形性を改善するこ とができ、 所望の信 号対雑音比を実現することができる。 さ らに、 選択可能に複数の帰還抵 抗を設けて帰還型増幅器を構成するこ とによ り、 入力インピーダンスを 所望の値にするこ とができるため、 L C回路を用いた整合回路が不要と なり、 増幅器を用いた受信機の構成を簡素化することができる。 図面の簡単な説明 According to the present invention configured as described above, the gain is controlled by switching the feedback resistance of the feedback amplifier, instead of switching the gate voltage and source resistance of the ranstar. The gate bias voltage of the input transistor is constant, the drain current is constant, and the open-circuit gain of the amplifier does not change by switching the feedback resistor. For this reason, the input dyna The linearity can be improved by suppressing the decrease of the microphone range, and the desired signal-to-noise ratio can be realized. In addition, the input impedance can be set to a desired value by configuring a feedback amplifier with multiple feedback resistors selectable, eliminating the need for a matching circuit using an LC circuit. Thus, the configuration of a receiver using an amplifier can be simplified. Brief Description of Drawings
図 1 は 、 従来の L N Aの構成を示す図である。 FIG. 1 is a diagram showing the configuration of a conventional LNA.
図 2は 、 本実施形態による L N Aの構成例を示す図であ FIG. 2 is a diagram showing a configuration example of LNA according to the present embodiment.
図 3は 、 本実施形態による L N Aの他の構成例を示す図であ Ό。 FIG. 3 is a diagram showing another configuration example of LNA according to the present embodiment.
図 4は 、 本実施形態で用いる帰還抵抗とアナログスィ クチの他の構成 例を示す図である。 発明を 施するための最良の形態 FIG. 4 is a diagram showing another configuration example of the feedback resistor and the analog switch used in the present embodiment. Best Mode for Invention
以下 、 本発明の一実施形態を図面に基づいて説明する 。 図 2は 、 本実 施形態による L N Aの構成例を示す図である。 なお この図 2におレゝて Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a diagram showing a configuration example of LNA according to the present embodiment. Please refer to Fig. 2.
、 図 1 に示した構成要素と同一の機能を有する構成 素には同一の符号 を付してレ、 •3 , Components having the same functions as those shown in Fig. 1 are given the same reference numerals, and
図 2において、 N 1 はソース接地型の入力 トランジスタであり 、 その ゲー トがキャパシタ C 1 を介して信号の入力端 I Nに接続され、 ソ一ス がダラン ドに接続され、 ドレインが信号の出力端 O U Tに接続されてい る。 Rしは負荷抵抗であり、 ソース接地 トランジスタ N 1 の出力 ( K レ ィン) と電源 V D Dとの間に接続されている。 In FIG. 2, N 1 is a common-source input transistor, and its gate is connected to the signal input terminal IN through the capacitor C 1, the source is connected to the drain, and the drain is the signal output. Connected to terminal OUT. R is a load resistance, and is connected between the output (K line) of the common source transistor N 1 and the power source V DD.
N 2はソ —ス接地 トランジスタ N 1 と共に電流ミ ラ一回路を構成する トランジスタである。 すなわち、 トランジスタ N 2のゲ — トが、 自身の ドレイ ンにダイオー ド接続されると と もに、 ソ ―ス接地トランジスタ N 1のゲー トに抵抗 R 2を介して接続されている。 トランジスタ N 2の ド レインは抵抗 R 1 を介して電源 VD Dに接続され、 ソースはグラン ドに 接続されている。 このよ う に電流ミ ラー回路を構成することによ り、 ソ ース接地トランジスタ N 1 と トランジスタ N 2 とのサイズ比で、 ソース 接地 ト ラ ンジス タ N 1 を流れる ドレイ ン電流が決まる。 N 2 is a transistor that forms a current mirror circuit together with the source ground transistor N 1. That is, the gate of transistor N 2 is diode-connected to its own drain and source grounded transistor N Connected to 1 gate via resistor R2. The drain of transistor N 2 is connected to power supply VDD through resistor R 1 and the source is connected to ground. By configuring the current mirror circuit in this way, the drain current flowing through the source grounded transistor N 1 is determined by the size ratio of the source grounded transistor N 1 and the transistor N 2.
また、 信号の出力端 O U T (ソース接地 トランジスタ N 1の ドレイ ン ) と信号の入力端 I N (ソース接地トランジスタ N 1 のゲー ト) と間に は、 帰還回路が設けられている。 帰還回路は、 信号の入力端 I Nと出力端 O U Tとの間に並列に設けられた複数の帰還抵抗 R N 1 , R N 2 , · · · , R N n ( nは 2以上の整数) と、 当該複数の帰還抵抗 R N 1〜R N nに対してそれぞれ直列に接続された複数のアナログスィ ッチ A SW l , A SW 2 , · · · , A S W n とを備えて構成されている。 Further, a feedback circuit is provided between the signal output terminal OU T (drain of the common source transistor N 1) and the signal input terminal I N (gate of the common source transistor N 1). The feedback circuit includes a plurality of feedback resistors RN 1, RN 2,..., RN n (where n is an integer greater than or equal to 2) provided in parallel between the signal input terminal IN and the output terminal OUT, .., ASW n, which are connected in series to the feedback resistors RN 1 to RN n, respectively, of the analog switches A SW l, A SW 2,.
こ こで、 複数の帰還抵抗 R N l〜R N nは、 その抵抗値がそれぞれ異 なっている。 複数のアナログスィ ッチ A SW l〜A S Wnは、 制御端子 P G 1 〜 P G nから印加される制御電圧によ ってオン Zオフが制御され 、 何れか 1つのみが選択的にオンと されるよ うになっている。 Here, the resistance values of the plurality of feedback resistors R N l to R N n are different. The plurality of analog switches ASW 1 to AS Wn are turned on / off by the control voltage applied from the control terminals PG 1 to PG n, and only one of them is selectively turned on. It has become so.
本実施形態では、 L N Aの利得を変える と きに、 ソース接地 トランジ ス タ N 1 のゲー トバイ アス電圧は一定とする。 その代わり に、 アナログ スィ ッ チ A S W l 〜A S W nのオン/オフ を切り替えて、 当該アナロ グ スィ ツチ A S W l 〜A S W nに直列接続された帰還抵抗 R N 1 〜 R N n の何れかを選択的に用いることにより、 L N Aの利得制御を行う。 In the present embodiment, the gate bias voltage of the common source transistor N 1 is constant when the gain of L N A is changed. Instead, the analog switches ASW l to ASW n are turned on / off to selectively select one of the feedback resistors RN 1 to RN n connected in series with the analog switches ASW l to ASW n. By using it, LNA gain control is performed.
この場合、 帰還抵抗 R N l〜R N nの選択によ り負帰還量 (帰還抵抗 値) を変化させると、 L NAの入力インピーダンスが変わることから、 イ ンピーダンス不整合によるロスが生じるかも しれない。 しかし、 AG C動作で L N Aの利得を減少させるときは入力信号のレベルが大きいと きであり、 下記の理由から上述のよ うなロ スの問題は起こ らない。 すなわち、 信号源電圧を E、 信号源抵抗を R s、 L N Aの入力イ ンピ —ダンスを R i と したとき、 R s = R i のときに最大電力 In this case, if the negative feedback amount (feedback resistance value) is changed by selecting feedback resistors RNl to RNn, the input impedance of LNA will change, which may cause a loss due to impedance mismatch. However, when the LNA gain is reduced in AGC operation, the input signal level is high, and the above-mentioned loss problem does not occur for the following reasons. That is, if the signal source voltage is E, the signal source resistance is R s, and the input impedance of the LNA is R i, then the maximum power when R s = R i
P max= E 2 / ( 4 R s ) P max = E 2 / (4 R s)
が L N Aに供給される。 これがイ ン ピーダンス整合のとれたときである いま、 L N Aの利得を変えるために帰還抵抗 R N 1〜R N nの何れか をアナログスィ ッチ A S W l〜A S Wnによ り選択して帰還抵抗値を変 えたとする。 このときイ ン ピーダンス不整合が生じ、 R i = l . 5 R s になったとすると、 そのとき L N Aに供給される電力 P 1 は、 Is supplied to L N A. This is when impedance matching is achieved.To change the gain of the LNA, select one of the feedback resistors RN 1 to RN n with the analog switch ASW l to AS Wn and set the feedback resistance value. Suppose it has changed. If impedance mismatch occurs at this time and R i = l 5 R s, then the power P 1 supplied to L N A is
P 1 = E 2 / ( 6. 2 5 R s ) P 1 = E 2 / (6.25 R s)
となる。 It becomes.
よ って、 イ ンピーダンス不整合によ る ロ スは、 Therefore, the loss due to impedance mismatch is
P loss= 1 0 XL0G(P max/ P 1 ) = 2 [ d B ] P loss = 1 0 XL0G (P max / P 1) = 2 [d B]
となり 、 問題にならないレベルである。 したがって、 例えば入力イ ンピ 一ダンス R i の値が最大でも 1 . 5 R s となるよ うに帰還抵抗 R N 1〜 R N nの抵抗値を設定しておけば、 ィ ン ピ一ダンス不整合によるロスは ほぼ無視できる。 At a level that does not become a problem. Therefore, for example, if the resistance values of the feedback resistors RN1 to RNn are set so that the value of the input impedance Ri is 1.5 Rs at the maximum, the loss due to impedance mismatch Is almost negligible.
以上詳しく説明したよ う に、 本実施形態では、 帰還回路を有する ソー ス接地型の L N Aにおいて、 当該帰還回路を複数の帰還抵抗 R N 1〜R N nで構成する と と もに、 その中から何れかを選択するアナ口 グスィ ッ チ A S W l〜A S W nを設け、 何れかの帰還抵抗を選択するこ とで L N Aの利得制御を行う よ うにしている。 As described above in detail, in the present embodiment, in a source grounded LNA having a feedback circuit, the feedback circuit is constituted by a plurality of feedback resistors RN 1 to RN n, and any of them is selected. An analog switch ASW l to ASW n is provided to select either of them, and the LNA gain is controlled by selecting one of the feedback resistors.
このよ うに、 帰還型増幅器の帰還抵抗値を切り替えて利得を制御して いるため、 入力 ト ランジスタである ソース接地 トランジスタ N 1 のゲ一 トバイ アス電圧は一定で、 ド レイ ン電流は一定となる。 また、 帰還抵抗 値の切り替えによって L N Aの開放利得が変化するこ と もない。 このた め、 大きなレベルの信号が入力されたとき でも L N Aの入力ダイナミ ッ ク レンジが低下するこ とを抑止して線形性に優れた所望の信号対雑音比 を実現できる。 特に、 2信号の妨害波が入力されたと きにおける信号対 雑音比を改善することができる。 In this way, since the gain is controlled by switching the feedback resistance value of the feedback amplifier, the gate bias voltage of the source grounded transistor N1, which is the input transistor, is constant, and the drain current is constant. . In addition, switching the feedback resistance value does not change the open gain of the LNA. others Therefore, even when a large level of signal is input, the desired signal-to-noise ratio with excellent linearity can be realized by suppressing the decrease of the input dynamic range of the LNA. In particular, the signal-to-noise ratio can be improved when two interference signals are input.
さ らに、 本実施形態によれば、 帰還回路と して抵抗値が異なる複数の 帰還抵抗 R N l 〜 R N nを設け、 この中から何れかを選択して接続する 構成とするこ とによ り 、 L N Aの入力イ ンピーダンスを所望の値にする こ とができる。 このため、 L C回路を用いた整合回路が不要となり 、 L NAを用いた受信機の構成を簡素化することができる。 Furthermore, according to the present embodiment, a plurality of feedback resistors RN l to RN n having different resistance values are provided as a feedback circuit, and any one of these is selected and connected. Thus, the input impedance of the LNA can be set to a desired value. This eliminates the need for a matching circuit using an LC circuit and simplifies the configuration of a receiver using an LNA.
図 3は、 本実施形態による L NAの他の構成例を示す図である。 なお 、 この図 3において、 図 2に示した符号と同一の符号を付したものは同 —の機能を有するものであるので、 こ こでは重複する説明を省略する。 図 3の例は、 カスコ ド接続した 2つの トランジスタによ り増幅段を構 成したものである。 この場合は、 カスコー ド接続の上側に位置するゲー ト接地 トランジスタの出力 ( ドレイン) から信号の入力端 I Nに帰還回 路を設ける。 FIG. 3 is a diagram showing another configuration example of the LNA according to the present embodiment. In FIG. 3, since components having the same reference numerals as those shown in FIG. 2 have the same functions, redundant description is omitted here. In the example in Fig. 3, the amplification stage is composed of two transistors connected in cascade. In this case, a feedback circuit is provided from the output (drain) of the gate ground transistor located above the cascode connection to the signal input terminal I N.
図 3において、 N 3はゲー ト接地 トランジスタであり、 ソース接地ト ランジスタ N 1 にカスコ一 ド接続されると と もに、 その ドレインが信号 の出力端 O U Tに接続されている。 ゲー ト接地 トランジスタ N 3の ドレ インは、 負荷抵抗 R Lを介して電源 V D Dにも接続されている。 ソース 接地 トランジスタ N 1 は初段増幅器と して機能し、 ゲー ト接地トランジ スタ N 3は次段増幅器と して機能する。 In FIG. 3, N 3 is a gate-grounded transistor, which is cascade-connected to the source-grounded transistor N 1 and has its drain connected to the signal output terminal OU T. The drain of the gate ground transistor N 3 is also connected to the power supply V DD via the load resistor R L. The common source transistor N 1 functions as a first-stage amplifier, and the common gate transistor N 3 functions as a next-stage amplifier.
N 4 , N 5はバイアス回路を構成する トラ ンジズタであり、 ゲー ト接 地トランジスタ N 3のバイアスを決定する。 このバイアス回路は、 その 一端が抵抗 R 3を介して電源 V D Dに接続され、 他端がグラ ン ドに接続 されている。 その他の構成は図 2 と同様である。 以上のよ うに、 トラン ジスタ N l , N 3をカ スコー ド接続することによ り、 広帯域で安定した 利得を得ることができるよ うになる。 N 4 and N 5 are transistors constituting the bias circuit, and determine the bias of the gate ground transistor N 3. One end of this bias circuit is connected to the power supply VDD via the resistor R3, and the other end is connected to the ground. Other configurations are the same as those in FIG. As mentioned above, Cascade connection of the registers Nl and N3 makes it possible to obtain a stable gain over a wide band.
なお、 上記実施形態では、 並列接続した複数の帰還抵抗 R N 1〜 R N nに対してそれぞれ直列に複数のアナログスィ ッチ A S W l〜A SW n を接続する構成について説明したが、 スィ ツチの構成はこれに限定され ない。 例えば、 並列接続した複数の帰還抵抗 R N 1 〜 R N nをパス上に 含む複数の信号線の中から何れかを選択するセ レク タによ り構成しても 良い。 In the above embodiment, the configuration in which a plurality of analog switches ASW 1 to A SW n are connected in series to the plurality of feedback resistors RN 1 to RN n connected in parallel has been described. Is not limited to this. For example, a selector that selects any one of a plurality of signal lines including a plurality of feedback resistors R N 1 to R N n connected in parallel on the path may be used.
また、 上記実施形態では、 抵抗値の異なる複数の帰還抵抗 R N 1〜 R N nを並列に設け、 この中から何れか 1つを選択する構成について説明 したが、 これに限定されない。 例えば、 図 4に示すよ うに、 複数の帰還 抵抗 R N l〜R N n と複数のアナログスィ ツチ A SW l〜A SWn とを ラダー状に接続し、 何れかのアナログスィ ツチ A SW l〜A SWnを選 択することによ り、 1個以上の帰還抵抗の合成抵抗値を可変とするよ う にしても良い。 この場合、 複数の帰還抵抗 R N l〜 R N nの抵抗値はそ れぞれ異なっていても良いし、 同じであっても良い。 In the above embodiment, a configuration has been described in which a plurality of feedback resistors R N1 to R N n having different resistance values are provided in parallel and any one of them is selected. However, the present invention is not limited to this. For example, as shown in FIG. 4, a plurality of feedback resistors RN l to RN n and a plurality of analog switches A SW l to A SWn are connected in a ladder shape, and one of the analog switches A SW l to A SWn is connected. By selecting, the combined resistance value of one or more feedback resistors may be made variable. In this case, the resistance values of the plurality of feedback resistors R N l to R N n may be different from each other or the same.
その他、 上記実施形態は、 本発明を実施するにあたっての具体化の一 例を示したものに過ぎず、 これによつて本発明の技術的範囲が限定的に 解釈されてはならないものである。 すなわち、 本発明はその精神、 また はその主要な特徴から逸脱することなく 、 様々な形で実施することがで さる。 産業上の利用可能性 In addition, the above-described embodiment is merely an example of the embodiment for carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the spirit or the main features thereof. Industrial applicability
本発明は、 帰還回路を有するソース接地型低雑音増幅器に有用である The present invention is useful for a common source low noise amplifier having a feedback circuit.
Claims
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| JP2006275499A JP2008098771A (en) | 2006-10-06 | 2006-10-06 | Low noise amplifier |
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| US7902920B1 (en) | 2009-09-10 | 2011-03-08 | Media Tek Singapore Pte. Ltd. | Amplifier circuit, integrated circuit and radio frequency communication unit |
| US7952430B1 (en) | 2009-09-10 | 2011-05-31 | Mediatek Singapore Pte. Ltd. | Amplifier circuit, integrated circuit and radio frequency communication unit |
| US8503960B2 (en) | 2011-07-29 | 2013-08-06 | Mediatek Singapore Pte. Ltd. | Amplifier and associated receiver |
| EP3391538B1 (en) * | 2015-12-18 | 2022-07-20 | Nordic Semiconductor ASA | Radio frequency receiver |
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| WO2019031184A1 (en) * | 2017-08-10 | 2019-02-14 | 株式会社村田製作所 | Amplification circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01311612A (en) * | 1988-06-09 | 1989-12-15 | Anritsu Corp | Wide dynamic linear amplifier circuit |
| JPH03187609A (en) * | 1989-12-18 | 1991-08-15 | Hamamatsu Photonics Kk | I-v conversion circuit |
| JP2001102877A (en) * | 1999-09-28 | 2001-04-13 | Sony Corp | Amplifier circuit and radio equipment using the same |
| JP2005312016A (en) * | 2004-03-25 | 2005-11-04 | Sharp Corp | Cascode connection amplifier circuit and communication apparatus using the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161109A (en) * | 1983-03-04 | 1984-09-11 | Fujitsu Ltd | Variable gain amplifier |
| JPH0681000B2 (en) * | 1985-06-18 | 1994-10-12 | 富士通株式会社 | Gain control circuit |
| JP2000261265A (en) * | 1999-03-10 | 2000-09-22 | Toshiba Microelectronics Corp | Feedback variable gain amplifier circuit |
-
2006
- 2006-10-06 JP JP2006275499A patent/JP2008098771A/en active Pending
-
2007
- 2007-09-21 TW TW96135573A patent/TW200818694A/en unknown
- 2007-10-04 WO PCT/JP2007/069901 patent/WO2008044750A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01311612A (en) * | 1988-06-09 | 1989-12-15 | Anritsu Corp | Wide dynamic linear amplifier circuit |
| JPH03187609A (en) * | 1989-12-18 | 1991-08-15 | Hamamatsu Photonics Kk | I-v conversion circuit |
| JP2001102877A (en) * | 1999-09-28 | 2001-04-13 | Sony Corp | Amplifier circuit and radio equipment using the same |
| JP2005312016A (en) * | 2004-03-25 | 2005-11-04 | Sharp Corp | Cascode connection amplifier circuit and communication apparatus using the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902920B1 (en) | 2009-09-10 | 2011-03-08 | Media Tek Singapore Pte. Ltd. | Amplifier circuit, integrated circuit and radio frequency communication unit |
| WO2011029492A1 (en) * | 2009-09-10 | 2011-03-17 | Mediatek Singapore Pte. Ltd. | Amplifier circuit, integrated circuit and radio frequency communication unit |
| US7952430B1 (en) | 2009-09-10 | 2011-05-31 | Mediatek Singapore Pte. Ltd. | Amplifier circuit, integrated circuit and radio frequency communication unit |
| US8503960B2 (en) | 2011-07-29 | 2013-08-06 | Mediatek Singapore Pte. Ltd. | Amplifier and associated receiver |
| EP3391538B1 (en) * | 2015-12-18 | 2022-07-20 | Nordic Semiconductor ASA | Radio frequency receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008098771A (en) | 2008-04-24 |
| TW200818694A (en) | 2008-04-16 |
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