WO2007116463A1 - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device comprising a support substrate (10), a multi-layered wiring structure formed on the support substrate and having a plurality of wiring lines (36, 42, 48, 54, 60 and 66) laminated through insulating layers (26, 28, 38, 44, 50, 56, 62 and 68), an electrode pad (78) formed on the multi-layered wiring structure, and a structure of a cross-shaped or Y-shaped section reaching the support substrate through the multi-layered wiring structure for supporting the electrode pad. The electrode pad is supported by the cross-shaped or Y-shaped section structure so that a constituent element existing below the electrode pad can be freed, when bonded, from a serious stress. Even if, therefore, an interlayer insulating film having a relatively low mechanical strength is used at a portion of the multi-layered wiring structure, it is possible to prevent the breakage or the like of a transistor, such as the deformation or breakage of a fine wiring pattern, thereby to provide a semiconductor device having high integration and reliability.

Description

 Specification

 Semiconductor device

 Technical field

 The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure.

 Background art

 [0002] Recently, a multilayer wiring structure in which a wiring and an interlayer insulating film for providing a highly integrated semiconductor device are sequentially stacked has been used. In a powerful multi-layer wiring structure, the wiring is very miniaturized and the wiring interval is set very narrow. As the wiring interval becomes narrower, the parasitic capacitance between the wirings increases, and signal delay becomes a problem.

 [0003] As a technique for reducing the parasitic capacitance between wirings, it has been proposed to use a low dielectric constant film having a relatively low relative dielectric constant in place of a conventional silicon oxide film. Yes. As such a low dielectric constant film, for example, a hydrocarbon-based or fluorocarbon-based organic insulating film is known. Such a low dielectric constant film generally has a relative dielectric constant of about 2.3 to 2.5, and has a relative dielectric constant of about 40 to 50% lower than that of a general silicon oxide film.

 [0004] It should be noted that such a low dielectric constant film generally does not necessarily have sufficient adhesion to wiring, and cannot be said to have sufficiently high moisture resistance.

 For this reason, in the lower layer portion of the multilayer wiring structure in which fine wiring is formed and the problem of signal delay becomes serious, such a low dielectric constant film is used, while the upper layer of the multilayer wiring structure having a relatively wide wiring interval. In the part, a general silicon oxide film having excellent adhesion and moisture resistance is used.

 [0006] Electrode pads (bonding pads) are formed on the multilayer wiring structure, and the electrode pads are electrically connected to any wiring in the multilayer wiring structure.

 [0007] The following is a background art of the present invention.

 Patent Document 1: Japanese Patent Laid-Open No. 2004-282000

 Patent Document 2: JP-A-2005-142553

 Disclosure of the invention

Problems to be solved by the invention However, in such a proposed semiconductor device, when a wire is bonded to the electrode pad, a large stress may be applied to the components existing below the electrode pad. For this reason, when the wiring width is reduced to, for example, about 0 .: m, the wiring may be deformed or disconnected. In some cases, transistors under the electrode pads were damaged. Here, it is conceivable that fine wiring, transistors, and the like are not formed below the electrode pads. In recent years, however, there has been a demand for miniaturization of semiconductor devices. Do not form fine wiring, transistors, etc. below the electrode pads. It will be contrary.

 An object of the present invention is to provide a highly reliable semiconductor device having a high degree of integration even when a material having a relatively low mechanical strength is used as a material for an interlayer insulating film. Means for solving the problem

[0010] According to one aspect of the present invention, a support substrate, a multilayer wiring structure formed on the support substrate, in which a plurality of wirings are stacked via an insulating layer, and formed on the multilayer wiring structure The electrode pad and a structure that reaches the support substrate through the multilayer wiring structure and supports the electrode pad, the structure having a cross-shaped or Y-shaped cross section A semiconductor device is provided.

 [0011] Further, according to another aspect of the present invention, a support substrate, a multilayer wiring structure formed on the support substrate and having a plurality of wirings stacked via an insulating layer, and the multilayer wiring structure An electrode pad formed thereon, a structure that reaches the support substrate through the multilayer wiring structure and supports the electrode pad, a plurality of columns, and a beam that connects the columns to each other There is provided a semiconductor device comprising: The invention's effect

[0012] According to the present invention, since the electrode pad is supported by the structure having a cross-shaped or Y-shaped cross section, a large stress is applied to the components existing below the electrode pad when bonding is performed. Can be prevented. Therefore, according to the present invention, even when an interlayer insulating film having a relatively low mechanical strength is used as a part of the multilayer wiring structure, the breakdown of the transistor such as fine deformation of the wiring pattern or disconnection is caused. Etc. can be prevented. For this reason, according to the present invention, an interlayer insulating film having a relatively low mechanical strength is used. Accordingly, a highly reliable semiconductor device with high integration can be provided.

 In addition, according to the present invention, a plurality of columns are embedded in the interlayer insulating film below the electrode pad, and these columns are supported by the beam, and the electrode pad is formed by a structure including the column and the beam. Therefore, when bonding is performed, it is possible to prevent a large stress from being applied to the components existing below the electrode pad. Therefore, according to the present invention, even when an interlayer insulating film having a relatively low mechanical strength is used in a part of the multilayer wiring structure, it is possible to prevent a strong stress from being applied to the components of the semiconductor device. It is possible to provide a highly reliable semiconductor device.

 Brief Description of Drawings

FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

 FIG. 2 is a plan view showing the semiconductor device according to the first embodiment of the present invention.

 FIG. 3 is a perspective view showing a part of the semiconductor device according to the first embodiment of the present invention.

 [FIG. 4] FIG. 4 is a graph (No. 1) showing a relationship between a structure embedded in an interlayer insulating film below an electrode pad and stress applied to a component below the electrode pad.

 FIG. 5 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

 FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

 FIG. 7 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

 FIG. 8 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

 FIG. 9 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

 FIG. 10 is a process cross-sectional view (No. 6) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.

FIG. 11 is a cross-sectional view showing a semiconductor device according to a modification (Part 1) of the first embodiment of the present invention. FIG. 12 is a plan view showing a semiconductor device according to a modification (Part 1) of the first embodiment of the present invention.

 FIG. 13 is a perspective view showing a part of a semiconductor device according to a modification (Part 2) of the first embodiment of the present invention.

 FIG. 14 is a process cross-sectional view (No. 1) showing the method for manufacturing a semiconductor device according to the modification (No. 2) of the first embodiment of the present invention.

 FIG. 15 is a process cross-sectional view (No. 2) showing the method for manufacturing a semiconductor device according to the modification (No. 2) of the first embodiment of the present invention.

 FIG. 16 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.

 FIG. 17 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

 FIG. 18 is a graph (No. 2) showing the relationship between the structure embedded in the interlayer insulating film below the electrode pad and the stress applied to the component below the electrode pad.

 FIG. 19 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

 FIG. 20 is a process cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

Explanation of symbols

10. Semiconductor substrate, support substrate

 12. Element area

 14 · Element isolation region

 16 ... Gate insulation film

 18 '' Gate electrode

 20 ··· Sidewall insulation film

 22 · '· Source z Drain diffusion layer

 24 · "Transistor

 26 · Interlayer insulation film

 28 · Interlayer insulation film

30 '' Contact hole 32 ... Conductor plug

34 · “Groove

 36 · "Wiring

 38 · Interlayer insulation film

40 · “Groove

 42 · "Wiring

 44. Interlayer insulation film

46 · “Groove

 48 ··· Wiring

 50 · Interlayer insulation film

52

 54 · "Wiring

 56 · Interlayer insulation film

58

 60 · "Wiring

 62 · Interlayer insulation film

64 ··· Groove

 66 · '"Wiring

 68 '-Interlayer insulation film

70.

72 ··· Conductor plug

74, 74a ... Opening 76, 76a ... Structure 77 ... Partial structure 78 ... Electrode pad 80 ... Photoresist film 82 ... Opening hole 84 ... Conductor plug 88 ... groove

 90 ... groove

 92 ... Contact hole

 94 ... Conductor plug

 96 ... groove

 98a-98d ... support

 100a ~;! OOd ...

 101 ... Structure

 102 ... groove

 103 ... groove

 104 ... groove

 106 ... groove

 107

 108 ... Contact hole

 110 ... Conductor plug

 112 ... groove

 114 ... groove

 116… Interlayer insulation film

 118 ··· Contact Honoré

 120… Conductor plug

 BEST MODE FOR CARRYING OUT THE INVENTION

[0016] [First embodiment]

 The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.

[0017] (Semiconductor device)

First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment. FIG. 2 shows the semiconductor according to the present embodiment. It is a top view which shows an apparatus. The A–A ^ line in Fig. 2 corresponds to the A–A ^ line in Fig. 1. FIG. 3 is a perspective view showing a part of the semiconductor device according to the present embodiment.

 As shown in FIG. 1, an element isolation region 14 that defines an element region 12 is formed in a semiconductor substrate (support substrate) 10. As the semiconductor substrate 10, for example, a silicon substrate is used.

 A gate electrode 18 is formed on the element region 12 via a gate insulating film 16.

[0020] In the semiconductor substrate 10 on both sides of the gate electrode 18, a low concentration diffusion layer (not shown) constituting a shallow region of the extension source Z drain structure is formed.

A sidewall insulating film 20 is formed on the side wall portion of the gate electrode 18.

[0022] In the semiconductor substrate 10 on both sides of the gate electrode 18 on which the sidewall insulating film 20 is formed, a high concentration diffusion layer (not shown) constituting a deep region of the extension source Z drain structure is formed. . The low concentration diffusion layer and the high concentration diffusion layer constitute the source Z drain diffusion layer 22 of the extension source Z drain structure.

Thus, the transistor 24 having the gate electrode 18 and the source Z drain diffusion layer 22 is formed.

 On the semiconductor substrate 10 on which the transistor 24 is formed, an interlayer insulating film 26 made of, for example, a 300 nm thick silicon oxide film is formed.

[0025] On the interlayer insulating film 26, an interlayer insulating film 28 having a thickness of 200 nm is formed. For the interlayer insulating film 28, a material having a relatively low relative dielectric constant is used. More specifically, a material having a relative dielectric constant smaller than 3.0 is used as the material of the interlayer insulating film 28. For example, SiLK (registered trademark), which is an organic insulating material manufactured by Dow Chemical Co., Ltd., is used as the material for the interlayer insulating film 28. The reason why such a material having a relatively low dielectric constant is used as the material of the interlayer insulating film 28 is to realize high-speed operation by reducing the parasitic capacitance between the wirings. The Young's modulus of the interlayer insulating film 28 is, for example, 30 GPa or less. Here, since SiLK (registered trademark) is used as the material of the interlayer insulating film 28, the Young's modulus of the interlayer insulating film 28 is very small, about 2.5 GPa. That is, the mechanical strength of the interlayer insulating film 28 is very weak. A contact hole 30 reaching the source / drain diffusion layer 22 is formed in the interlayer insulating film 28 and the interlayer insulating film 26.

[0027] In the contact hole 30, a conductor plug 32 made of, for example, tungsten (W) is embedded.

 In the interlayer insulating film 28 in which the conductor plug 32 is embedded, a groove 34 for embedding the wiring 36 is formed. A wiring 36 made of, for example, copper (Cu) is embedded in the groove 34 to be applied. The wiring 36 is electrically connected to the source Z drain diffusion layer 22 via the conductor plug 32.

 The wiring 36 is formed by forming a conductive film in the trench 34 and on the interlayer insulating film 28, and CMP (Chemical Mechanical Polishing) until the surface of the interlayer insulating film 28 is exposed. It can be formed in the groove 34 by polishing by the method.

 An interlayer insulating film 38 having a thickness of 200 nm is formed on the interlayer insulating film 28 on which the wiring 36 is formed. For the interlayer insulating film 38, for example, the same material as that of the interlayer insulating film 28 is used.

 In the interlayer insulating film 38, a groove 40 for embedding the wiring 42 is formed. A wiring 42 made of, for example, Cu is embedded in the groove 40. The wiring 42 is electrically connected to the wiring 36 through a conductor plug (not shown) embedded in the interlayer insulating film 38.

 An interlayer insulating film 44 having a thickness of 200 nm is formed on the interlayer insulating film 38 on which the wiring 42 is formed. For the interlayer insulating film 44, for example, the same material as the interlayer insulating films 28 and 38 is used.

 In the interlayer insulating film 44, a groove 46 for embedding the wiring 48 is formed. A wiring 48 made of Cu, for example, is buried in the groove 46. The wiring 48 is electrically connected to the wiring 42 through a conductor plug (not shown) embedded in the interlayer insulating film 44.

 On the interlayer insulating film 44 on which the wiring 48 is formed, a layer interlayer insulating film 50 having a thickness of 200 nm is formed. As the interlayer insulating film 50, for example, the same material as the interlayer insulating films 28, 38, and 44 is used.

In the interlayer insulating film 50, a groove 52 for embedding the wiring 54 is formed. In the groove 52, a wiring 54 made of Cu, for example, is embedded. The wiring 54 is embedded in the interlayer insulating film 50. It is electrically connected to the wiring 48 through the inserted conductor plug (not shown).

An interlayer insulating film 56 having a thickness of 400 nm is formed on the interlayer insulating film 50 in which the wiring 54 is embedded. As the interlayer insulating film 56, for example, a SiO 2 film or a SiOC film formed by a plasma CVD method is used. The interlayer insulating film 56 made of such a material is

2

 Although the dielectric constant is relatively high, it has high adhesion, high moisture resistance, and high mechanical strength. An interlayer insulating film 56 made of such a material is used in the upper layer portion of the multilayer wiring structure. Since the distance between the wirings 60 is relatively wide in the upper layer portion of the multilayer wiring structure, the relative dielectric constant is relatively high, and even when the material is used as the material of the interlayer insulating film 56, the parasitic capacitance between the wirings 60 is low. There is no serious signal delay when it becomes too large. Since the interlayer insulating film 56 made of such a material is used in the upper layer portion of the multilayer wiring structure, it becomes possible to contribute to improvement of adhesion to the base, improvement of moisture resistance and improvement of mechanical strength.

In the interlayer insulating film 56, a groove 58 for embedding the wiring 60 is formed. In the groove 58, a wiring 60 made of, for example, Cu is embedded. The wiring 60 is electrically connected to the wiring 54 via a conductor plug (not shown) embedded in the interlayer insulating film 56.

 An interlayer insulating film 62 is formed on the interlayer insulating film 56 in which the wiring 60 is embedded.

 As the material of the interlayer insulating film 62, for example, the same material as that of the above-described interlayer insulating film 56 is used.

 In the interlayer insulating film 62, a groove 64 for embedding the wiring 66 is formed. In the groove 64, a wiring 66 made of Cu, for example, is embedded. The wiring 66 is electrically connected to the wiring 60 through a conductor plug (not shown) embedded in the interlayer insulating film 62.

 An interlayer insulating film 68 is formed on the interlayer insulating film 62 in which the wiring 66 is embedded.

 As the material of the interlayer insulating film 56, for example, the same material as that of the above-described interlayer insulating films 56 and 58 is used.

 [0041] As a material of the interlayer insulating films 56, 62, 68, when the SiO film or the SiOC film formed by, for example, the plasma CVD method as described above is used, the Young's modulus of these laminated bodies is

 2

It is relatively large, about 60-70 GPa. That is, the mechanical strength of the interlayer insulating films 56, 62, and 68 is relatively high. [0042] Thus, the wirings 36, 42, 48, 54, 60, 66 and the interlayer insulating films 26, 28, 38, 44, 50, 56, 6

A multilayer wiring structure is formed by sequentially stacking 2 and 68.

In the interlayer insulating film 68, a contact hole 70 reaching the wiring 64 is formed. In the contact hole 70, for example, a conductor plug 72 made of tungsten is embedded.

In the interlayer insulating films 68, 62, 56, 50, 44, 38, 28, and 26, an opening 74 that reaches the element isolation region 14 is formed.

As shown in FIG. 2, the planar shape of the opening 74 is a cross shape.

[0046] In the opening 74, a structure 76 having a cross-shaped cross section made of, for example, Cu is embedded.

. The cross section of the structure 76 has a cross shape, and a part of the structure 76 has a wall shape as shown in FIG. In other words, as shown in FIG. 3, the four wall-shaped partial structures 77a to 77d are integrally formed so as to be connected to each other on one side.

[0047] On the interlayer insulating film 68 in which the structure 76 having a cross-shaped cross section is embedded, for example, a film thickness of 20

An interlayer insulating film 116 made of an Onm silicon oxide film is formed. The interlayer insulating film 116 is for insulating the cross-shaped structure 76 from an electrode pad 78 described later.

In the interlayer insulating film 116, a contact hole 118 reaching the conductor plug 72 is formed. A conductor plug 120 made of tungsten, for example, is buried in the contact hole 118.

 An electrode pad (bonding pad) 78 is formed on the interlayer insulating film 116 in which the conductor plug 120 is embedded. A bonding wire (not shown) is connected to the electrode pad 78.

 [0050] In the present embodiment, the structure 76 is formed for the following reason.

[0051] First, since the structure 76 is formed so that the end of the cross-section of the structure 76 is located below the edge of the electrode pad 78, the cross section is thin and square. The cross-sectional area of the structure 76 is relatively large as compared with the case where the column is used as the structure. Since the cross-sectional area of the structure 76 is relatively large, it can sufficiently withstand the impact during bonding. Therefore, it is possible to prevent a large stress from being applied to a structure such as a wiring existing below the electrode pad 78. Second, since the cross section of the structure 76 has a cross shape, only a part of the lower region of the electrode pad 78 is occupied by the structure 76. For this reason, wiring can be appropriately formed in a region below the electrode pad 78 that is not occupied by the structure 76.

 [0053] Third, since the cross section of the structure 76 has a cross shape, the structure 76 is not easily deformed even when a force from an oblique direction is applied to the electrode pad 78 during bonding. It can sufficiently withstand the impact during bonding. For this reason, even if an oblique force is applied during bonding, it is possible to prevent a large stress from being applied to a structure such as a wiring existing below the electrode pad 78.

 For this reason, in the present embodiment, the cross-sectional structure 76 is formed.

Thus, the semiconductor device according to the present embodiment is configured.

 [0056] (Evaluation result)

 FIG. 4 is a graph showing the relationship between the structure embedded in the interlayer insulating film below the electrode pad and the stress applied to the components below the electrode pad. The ▲ marks in FIG. 4 indicate the case of Comparative Example 1, that is, the case where a single structure having a square cross section is embedded in the interlayer insulating film below the electrode pad. In FIG. 4, the ♦ mark in Example 1 indicates that the cross section of the interlayer insulating films 26, 28, 38, 44, 50, 56, 62, and 68 below the electrode pad 78 is sufficient as in the present embodiment. The case where the character-shaped structure 76 is embedded is shown. The horizontal axis in FIG. 4 indicates the area ratio of the structure with respect to the area of the electrode pad 78. The vertical axis in FIG. 4 indicates the maximum value of stress applied to the components below the electrode pad 78.

 [0057] As shown in FIG. 4, in the case of Example 1, compared to the case of Comparative Example 1, the area ratio with respect to the pad is the same as that of Comparative Example 1, but exists below electrode pad 78. The stress applied to the components is significantly reduced.

[0058] According to the present embodiment, since the electrode pad 78 is supported by the structure 76 having a cross-shaped cross section, a large stress is applied to the components existing below the electrode pad 78 when bonding is performed. Can be prevented from being added. Therefore, according to this embodiment, the interlayer insulating films 28, 38, 44, and 50 having relatively weak mechanical strength are used as part of the multilayer wiring structure. Even in such a case, it is possible to prevent the breakdown of the transistor, such as a fine wiring pattern deformation or disconnection. Therefore, according to the present embodiment, a semiconductor device having a high degree of integration and high reliability can be provided even when the interlayer insulating films 28, 38, 44, and 50 having relatively weak mechanical strength are used. can do.

[0059] (Method for Manufacturing Semiconductor Device)

 Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 5 to 10 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment.

 First, as shown in FIG. 5, an element isolation region 14 that defines an element region 12 is formed on a semiconductor substrate (support substrate) 10 by, for example, an STI (Shallow Trench Isolation) method. For example, a silicon substrate is used as the semiconductor substrate 10.

 Next, a gate electrode 18 is formed on the element region 12 via a gate insulating film 16.

 Next, a dopant impurity is introduced into the semiconductor substrate 10 on both sides of the gate electrode 18 by, eg, ion implantation, using the gate electrode 18 as a mask. As a result, a low concentration diffusion layer (not shown) constituting a shallow region of the extension source Z drain structure is formed.

 Next, for example, a silicon oxide film is formed on the entire surface. The strong silicon oxide film becomes the sidewall insulating film 18.

 Next, a sidewall insulating film 20 made of a silicon oxide film is formed on the sidewall portion of the gate electrode 18 by anisotropic etching.

 Next, a dopant impurity is introduced into the semiconductor substrate 10 on both sides of the gate electrode 18 by, for example, ion implantation, using the gate electrode 18 and the sidewall insulating film 20 as a mask. As a result, a high concentration diffusion layer (not shown) constituting a deep region of the extension source Z drain structure is formed. Thus, the source Z drain diffusion layer 22 of the extension source Z drain structure is constituted by the low concentration diffusion layer and the high concentration diffusion layer.

 Thus, the transistor 24 having the gate electrode 18 and the source Z drain diffusion layer 22 is formed.

Next, an interlayer insulating film 26 made of, for example, a 300 nm-thickness silicon oxide film is formed on the entire surface by, eg, CVD. Next, an interlayer insulating film 28 having a thickness of lOOnm is formed on the entire surface by, eg, spin coating. A material having a relatively low relative dielectric constant is used for the interlayer insulating film 28. More specifically, a material having a relative dielectric constant smaller than 3.0 is used as the material of the interlayer insulating film 28. As the material of the interlayer insulating film 28, for example, Si LK (registered trademark), which is an organic insulating material manufactured by Dow Chemical Company, or the like can be used. The reason why a material having a relatively low dielectric constant is used as the material of the interlayer insulating film 28 is to realize high-speed operation by reducing the parasitic capacitance between the wirings as described above. When the above-described SiLK (registered trademark) is used as the material of the interlayer insulating film 28, as described above, the Young's modulus of these laminates is relatively small, about 2.5 GPa, and the mechanical strength is relatively small. Low.

 Next, a contact hole 30 reaching the source Z drain diffusion layer 22 is formed in the interlayer insulating film 28 and the interlayer insulating film 26.

 Next, a NOR film made of TaN having a thickness of, eg, 50 nm is formed on the entire surface by, eg, sputtering.

 Next, a conductive film made of tungsten having a thickness of 1 μm is formed on the entire surface by, eg, CVD.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 28 is exposed. Thus, the conductor plug 32 made of, for example, tungsten is buried in the contact hole 30.

 [0073] Next, an interlayer insulating film 28 having a thickness of lOOnm is further formed on the entire surface by, eg, spin coating.

 Next, a trench 34 for embedding the wiring 36 is formed in the interlayer insulating film 28 using a photolithography technique.

 Next, a conductive film made of Cu is formed on the entire surface by, eg, electroplating.

Next, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 28 is exposed. In this way, the wiring 36 made of Cu is embedded in the groove 34. The wiring 36 is electrically connected to the source Z drain diffusion layer 22 through the conductor plug 32.

Next, an interlayer insulating film 38 having a thickness of 200 nm is further formed on the entire surface by, eg, spin coating. For the interlayer insulating film 38, for example, the same material as that of the interlayer insulating film 28 is used. Next, a trench 40 for embedding the wiring 42 is formed in the interlayer insulating film 38 by using a photolithography technique.

 [0079] Next, a conductive film made of Cu is formed on the entire surface by, eg, electroplating.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 38 is exposed. Thus, the wiring 42 made of Cu is embedded in the groove 40. The wiring 42 is electrically connected to the wiring 36 through a conductor plug (not shown).

Next, an interlayer insulating film 44 having a thickness of 200 nm is further formed on the entire surface by, eg, spin coating. For the interlayer insulating film 44, for example, the same material as the interlayer insulating films 28 and 38 is used.

 Next, a trench 46 for embedding the wiring 48 is formed in the interlayer insulating film 44 by using a photolithography technique.

 Next, a conductive film made of Cu is formed on the entire surface by, eg, electroplating.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 44 is exposed. In this way, the wiring 48 made of Cu is embedded in the groove 46. The wiring 48 is electrically connected to the wiring 42 through a conductor plug (not shown).

Next, an interlayer insulating film 50 having a thickness of 200 nm is further formed on the entire surface by, eg, spin coating. For the interlayer insulating film 50, for example, the same material as the interlayer insulating films 28, 38, and 44 is used.

 Next, a trench 52 for embedding the wiring 54 is formed in the interlayer insulating film 50 by using a photolithography technique.

 Next, a conductive film made of Cu is formed on the entire surface by, eg, electroplating.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 50 is exposed. Thus, the wiring 54 made of Cu is embedded in the groove 52. The wiring 54 is electrically connected to the wiring 48 through a conductor plug (not shown).

[0089] Next, a 400 nm-thickness SiO film or SiOC film is formed on the entire surface by, eg, plasma CVD.

 2

An inter-layer insulating film 56 made of or the like is formed. The interlayer insulating film 56 made of such a material has a relatively high specific dielectric constant, but has a high adhesion and a high moisture resistance and a relatively high mechanical strength. An interlayer insulating film 56 made of such a material is used in the upper layer portion of the multilayer wiring structure. Since the distance between the wirings 60 is relatively wide in the upper layer portion of the multilayer wiring structure, the relative dielectric constant is relatively high V, and even when the material is used as the material of the interlayer insulating film 56, the parasitic capacitance between the wirings 60 is large. There is no serious signal delay when it becomes too large. Since the interlayer insulating film 56 made of such a material is used in the upper layer portion of the multilayer wiring structure, it becomes possible to contribute to improvement of adhesion to the base, improvement of moisture resistance and improvement of mechanical strength. . As the interlayer insulating film 56, for example, a SiO film or a SiOC film is formed by a plasma CVD method.

 2

 In this case, the Young's modulus of the interlayer insulating film 56 is relatively large, about 60 to 70 GPa.

Next, a trench 58 for embedding the wiring 60 is formed in the interlayer insulating film 56 by using a photolithography technique.

 Next, a conductive film made of Cu is formed on the entire surface by, eg, electroplating.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 50 is exposed. Thus, the wiring 60 made of Cu is embedded in the groove 58. The wiring 60 is electrically connected to the wiring 54 through a conductor plug (not shown).

[0093] Next, a 400 nm-thickness SiO film or SiOC film is formed on the entire surface by, eg, plasma CVD.

 2

 An interlayer insulating film 62 made of or the like is formed.

Next, a trench 64 for embedding the wiring 66 is formed in the interlayer insulating film 62 by using a photolithography technique.

 Next, a conductive film made of Cu is formed on the entire surface by, eg, electroplating.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 62 is exposed. Thus, the wiring 66 made of Cu is embedded in the groove 64. The wiring 66 is electrically connected to the wiring 60 through a conductor plug (not shown).

[0097] Next, a 400 nm thick SiO film or SiOC film is formed on the entire surface by, eg, plasma CVD.

 2

 An interlayer insulating film 68 made of, for example, is formed.

Next, a contact hole 70 reaching the wiring 64 is formed in the interlayer insulating film 68 by using a photolithography technique.

 Next, a NOR film made of TaN, for example, with a thickness of 50 nm is formed on the entire surface by, eg, sputtering.

[0100] Next, a conductive film made of tungsten having a thickness of 1 μm is formed on the entire surface by, eg, CVD. To do.

 Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 68 is exposed. Thus, the conductor plug 72 made of, for example, tungsten is buried in the contact hole 70.

 Next, a photoresist film 80 is formed on the entire surface by spin coating.

 Next, an opening 82 is formed in the photoresist film 80 by using a photolithography technique. In this case, an opening 74 reaching the element isolation region 14 is formed in the insulating film 68, 62, 56, 50, 44, 38, 28, 26.

Next, using the photoresist film 80 as a mask, the interlayer insulating films 68, 62, 56, 50, 44, 38, 2

Etch 8 and 26. In this way, interlayer insulating films 68, 62, 56, 50, 44, 38, 28, 26

Then, an opening 74 reaching the element isolation region 14 is formed (see FIG. 6).

Thereafter, as shown in FIG. 7, the photoresist film 80 is peeled off.

 Next, as shown in FIG. 8, a conductive film 76 made of Cu, for example, is formed on the entire surface by electroplating.

 [0107] Next, the conductive film 76 is polished by CMP until the surface of the interlayer insulating film 68 is exposed.

. Thus, a structure 76 made of a conductive film is formed in the opening 74.

Next, a 400 nm-thickness SiO film or SiOC film is formed on the entire surface by, eg, plasma CVD.

 2

 An interlayer insulating film 116 made of or the like is formed.

Next, a contact hole 118 reaching the conductor plug 72 is formed in the interlayer insulating film 116 by using a photolithography technique.

Next, a NOR film made of TaN having a thickness of, eg, 50 nm is formed on the entire surface by, eg, sputtering.

 Next, a conductive film made of tungsten having a thickness of 1 μm is formed on the entire surface by, eg, CVD.

 Next, the conductive film is polished by CMP, for example, until the surface of the interlayer insulating film 116 is exposed. Thus, the conductor plug 120 made of tungsten, for example, is buried in the contact hole 118 (see FIG. 9).

Next, a conductive film 78 is formed on the entire surface by, eg, sputtering. Conductive film 78 This is for forming an electrode pad.

 [0114] Next, the conductive film 78 is patterned into the shape of an electrode pad using a photolithography technique. Thus, an electrode pad 78 made of a conductive film is formed (see FIG. 10).

Thus, the semiconductor device according to the present embodiment is manufactured.

 In the semiconductor device according to the present embodiment, as described above, the cross-sectional structure 76 is embedded in the layer f¾ insulating films 20, 28, 38, 44, 50, 56, 62, 68, The main feature is that the electrode pad 78 is supported by a powerful structure 76.

 According to the present embodiment, since the structure 76 is formed in a wide range under the electrode pad 78, the cross-sectional area of the structure 76 is very large. In other words, the structure 76 is formed so as to extend so as to reach the edge of the electrode pad 76. Since the cross-sectional area of the structure 76 is very large, it can sufficiently withstand the impact during bonding. Therefore, it is possible to prevent a large stress from being applied to a structure such as a wiring existing below the electrode node 78.

 [0118] According to this embodiment, since the cross section of the structure 76 has a cross shape, the structure 76 is formed in a wide V range! However, it is possible to appropriately form wiring in the region. Therefore, according to the present embodiment, it is possible to provide a highly integrated semiconductor device while forming the structure 76 large.

 [0119] According to the present embodiment, since the cross section of the structure 76 has a cross shape, the structure 76 can be easily formed even when a force from an oblique direction is applied to the electrode pad 78 during bonding. It is possible to sufficiently withstand an impact during bonding. For this reason, according to the present embodiment, even when an oblique force is applied during bonding, it is possible to prevent a large stress from being applied to a structure such as a wiring existing under the electrode pad 78. .

 [0120] (Modification (Part 1))

 Next, a modification of the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 11 is a cross-sectional view showing a semiconductor device according to this modification. FIG. 12 is a plan view showing a semiconductor device according to this modification.

[0121] Fig. 11 and Fig. 12 [As shown] Layer insulation film 20, 28, 38, 44, 50, 56, 62, 68 An opening 74a whose planar shape is X-shaped is formed. In the opening 74a, a structure 76a having a cross-sectional shape, more specifically an X-shaped cross section, is embedded. The structure 76a is formed to extend to reach the edge of the electrode pad 76! RU

 [0122] Thus, the layer insulating film 20, 28, 38, 44, 50, 56, 62, 68 [the cross-sectional shape of the embedded structure 76a may be X-shaped.

 [0123] The structure 76a having an X-shaped cross section corresponds to the structure 76 having a cross-shaped cross section (see FIGS. 2 and 3) when rotated by 45 degrees. Therefore, the structure 76a having an X-shaped cross section can be grasped as a structure having a cross-shaped cross section.

 Therefore, in the specification and claims of the present application, a structure having a cross-shaped cross section also means a structure having an X-shaped cross section.

[0125] As described above, the structure 76a having an X-shaped cross section may be formed.

[0126] (Modification (Part 2))

 Next, a semiconductor device and a manufacturing method according to a modification of the present embodiment will be described with reference to FIGS. FIG. 13 is a perspective view showing a part of the semiconductor device according to the present modification. Figure

14 and 15 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present modification.

The semiconductor device according to this modification is mainly characterized in that a part of the wirings formed above the semiconductor substrate 10 is formed so as to penetrate the structure 76.

As shown in FIG. 13, the wirings 36, 42, 48 are formed so as to penetrate the structure 76.

[0129] The wiring 42 and the structure 76 are insulated from each other by the interlayer insulating films 38, 44 and the like.

Similarly, the wiring 36 and the structure 76 are insulated from each other by the interlayer insulating films 28 and 38 (see FIG. 1) or the like.

 In addition, the wiring 48 and the structure 76 are isolated from each other by the interlayer insulating films 44 and 50 (see FIG. 1) or the like.

 [0132] Further, the wirings 54, 60, and 66 are also omitted from the force formed so as to penetrate the structure 76 in FIG.

In this way, the wirings 36, 42, 48, 54, 60, 66 may be formed so as to penetrate the structure 76 as appropriate. According to this modification, the degree of freedom in forming the wirings 36, 42, 48, 54, 60, 66 can be improved, and a semiconductor device with a higher degree of integration can be provided. Next, a method for manufacturing a semiconductor device according to this modification will be described with reference to FIGS.

[0135] The manufacturing method of the semiconductor device according to this modification is mainly characterized in that the structure 76 is formed at the same time as the formation of the conductor plug and the wiring.

FIG. 14A shows a state in which the conductor plug 84 and the structure 76 are embedded in the interlayer insulating film 38. The interlayer insulating film 38 is formed by, for example, a spin coat method. In the vicinity of a region where the wiring 42 is formed in a later process, an interlayer insulating film 38 is embedded in a part of the structure 76. The interlayer insulating film 38 embedded in a part of the structure 76 is for insulating the wiring 42 and the structure 76.

[0137] Next, an interlayer insulating film 38 is further formed on the entire surface by spin coating.

Next, a trench 86 for embedding the structure 76 and a trench 88 for embedding the wiring 42 are formed in the interlayer insulating film 38 by using a photolithography technique.

[0139] Next, a conductive film made of Cu, for example, is formed on the entire surface by, eg, electroplating.

[0140] Next, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 38 is exposed. Thus, the conductor constituting a part of the structure 76 is embedded in the groove 86 and

Then, the wiring 42 is embedded in the groove 88 (see FIG. 14B).

Next, an interlayer insulating film 44 is formed on the entire surface by spin coating.

[0142] Next, the groove 90 and the conductor plug for embedding the structure 76 using photolithography technology

Contact holes 92 for embedding 94 are formed in the interlayer insulating film 44.

[0143] Next, a conductive film made of Cu, for example, is formed on the entire surface by, eg, electroplating.

Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 44 is exposed. Thus, the conductor constituting a part of the structure 76 is embedded in the groove 90 and

Then, a conductor plug 92 is embedded in the contact hole 92 (see FIG. 15 (a)).

[0145] Next, an interlayer insulating film 50 is further formed on the entire surface by spin coating.

Next, a trench 96 for embedding the structure 76 is formed in the interlayer insulating film 50 by using a photolithography technique.

 [0147] Next, a conductive film made of Cu, for example, is formed on the entire surface by, eg, electroplating.

Next, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 50 is exposed. To do. In this way, a conductor constituting a part of the structure 76 is embedded in the groove 96.

Thereafter, the semiconductor device according to the present modification is manufactured by repeating the above-described steps in the same manner.

[0150] [Second Embodiment]

 A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. Note that the same reference numerals are given to the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment, and the description will be omitted or simplified.

[0151] (Semiconductor device)

 First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. Figure 16

FIG. 3 is a cross-sectional view showing the semiconductor device according to the present embodiment. FIG. 17 is a plan view showing the semiconductor device according to the present embodiment.

The semiconductor device according to the present embodiment is mainly characterized in that the electrode pad is supported by the structure 101 composed of the columns 98a to 98d and the beams 100a to 100d.

[0153] As shown in FIG. 16, below the electrode pad 78, pillars 98a to 98d are formed so as to correspond to the four corners of the electrode pad 78 !.

[0154] Between these columns 98a to 98d, a beam 100a that supports the columns 98a to 98d appropriately.

˜100d (see FIGS. 16, 17, 19, and 20) are appropriately formed.

[0155] The beams 100a to 100d are formed so that the structure 101 composed of the columns 98a to 98d and the beams 100a to 100d can withstand an impact when bonding to the electrode pad 78. is there.

 [0156] As shown in FIG. 16, the beams 100c and lOOd are preferably provided in the vicinity of the interlayer insulating films 28, 38, 44, and 50 having a relatively low relative dielectric constant. This is because the interlayer insulating films 28, 38, 44, and 50, which have a relatively low relative dielectric constant, have relatively low mechanical strength, so it is desirable to reinforce them with beams 100c, lOOd, or the like.

 Thus, the semiconductor device according to the present embodiment is constituted.

 [0158] (Evaluation result)

FIG. 18 is a graph showing the relationship between the structure embedded in the interlayer insulating film below the electrode pad and the stress applied to the components below the electrode pad. The ▲ mark in Figure 18 In the case of Comparative Example 1, that is, the case where a single pillar having a square cross section is embedded in the interlayer insulating film below the electrode pad is shown. The country mark in FIG. 18 shows the case of Comparative Example 2, that is, the case where no four beams are embedded in the interlayer insulating film below the electrode pad corresponding to the four corners of the electrode pad. . In FIG. 4, the ♦ marks indicate the case of Example 2, that is, as in this embodiment, the interlayer insulating films 26, 28, 38, 44, 50, 56, 62, 68 below the electrode pad 78. Four corners (corresponding to four columns 98a to 98d correspondingly embedded, and two columns 98a to 98d supported by two beams). The horizontal axis in FIG. 18 indicates the area ratio of the support with respect to the area of the electrode pad 78. The vertical axis in FIG. 18 represents the maximum value of stress applied to the components existing below the electrode pad 78.

 [0159] As shown in FIG. 18, in the case of Example 2, the stress due to the components existing below the electrode node is smaller in the case of Example 2 than in the case of Comparative Examples 1 and 2. It is summer.

 As described above, according to the present embodiment, the pillars 98a to 98d are embedded in the interlayer insulating films 26, 28, 38, 44, 50, 56, 62, 68 below the electrode pads 78, and these Strut 98a ~ 98d Force S Beam 100a ~ 100d [This is supported by each other] The electrode pad 78 is supported by the structure 101 consisting of the pillars 98a-98d and the beams 100a-100d, so that bonding is performed. In this case, it is possible to suppress a large stress from being applied to the components existing below the electrode pad 78.

 [0161] Furthermore, according to the present embodiment, since the structure 101 is not formed in a wall shape, wiring can be freely formed between the columns 98a to 98d. Therefore, according to the present embodiment, it is possible to prevent a large stress from being applied to the components existing below the electrode pad 78 when bonding is performed while securing the degree of freedom of wiring.

[0162] Further, according to the present embodiment, since the columns 98a to 98d are supported by the beams 100a to 100d, even when a force from an oblique direction is applied to the electrode pad 78 during bonding. The structure composed of the pillars 98a to 98d and the beams 100a to 100d is not easily deformed and can sufficiently withstand the impact during bonding. For this reason, according to this embodiment, even if an oblique force is applied during bonding, it is possible to prevent a large stress from being applied to a structural element such as a wiring existing below the electrode pad 78. it can.

 [0163] (Method for Manufacturing Semiconductor Device)

 Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 19 and 20 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

 FIG. 19 (a) shows a state in which the conductor plug 84 and the support columns 98a to 98d are embedded in the interlayer insulating film 38. FIG. The interlayer insulating film 38 is formed by, for example, a spin coat method.

[0165] Next, an interlayer insulating film 38 is further formed on the entire surface by spin coating.

[0166] Next, a groove 10 for embedding a part of the pillars 98a to 98d using photolithography technology.

2, a groove 103 for embedding part of the beams 100 d and lOOe and a groove 104 for embedding the wiring 42 are formed in the interlayer insulating film 38.

[0167] Next, a conductive film made of Cu, for example, is formed on the entire surface by, eg, electroplating.

[0168] Next, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 38 is exposed. Thus, the conductor constituting part of the columns 98a to 98d is embedded in the groove 102, the conductor constituting part of the beams 100d and lOOe is embedded in the groove 103, and the wiring 42 is formed in the groove 10

4 (see Fig. 19 (b)).

[0169] Next, an interlayer insulating film 44 is formed on the entire surface by spin coating.

[0170] Next, using photolithography technology, a groove 106 for embedding the columns 98a to 98d, and a beam

A groove 107 for embedding 100d, lOOe and a contact hole 108 for embedding the conductor plug 94 are formed in the interlayer insulating film 44.

[0171] Next, a conductive film made of Cu, for example, is formed on the entire surface by, eg, electroplating.

Next, the conductive film is polished by, for example, a CMP method until the surface of the interlayer insulating film 44 is exposed. Thus, the conductor constituting a part of the columns 98a to 98d is embedded in the groove 106 and the beam.

A conductor constituting a part of 100d and lOOe is embedded in the groove 107, and a conductor plug 110 is embedded in the contact hole 108 (see FIG. 20 (a)).

[0173] Next, an interlayer insulating film 50 is further formed on the entire surface by spin coating.

Next, a trench 112 for embedding the pillars 98a to 98d and a trench 114 for embedding the wiring 48 are formed in the interlayer insulating film 50 by using a photolithography technique. Next, a conductive film made of Cu, for example, is formed on the entire surface by, eg, electroplating.

[0176] Next, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 50 is exposed. Thus, the conductor constituting a part of the support columns 98a to 98d is embedded in the groove 112, and the wiring 48 is embedded in the groove 114 (see FIG. 20B).

Thereafter, the semiconductor device according to the present embodiment is manufactured by repeating the above-described steps in the same manner.

 According to the present embodiment, the plurality of pillars 98a to 98d are embedded in the interlayer insulating films 26, 28, 38, 44, 50, 56, 62, and 68 below the electrode pads 78, and these pillars 98a ~ 98d force S beam 10 Oa ~: LOOd is supported by this structure, and the electrode pad 78 is supported by the structure 101 composed of these columns 98a ~ 98d and beams 100a ~ 100d. It is possible to prevent a large stress from being applied to the components existing below the electrode pad 78 when performing. Therefore, according to the present embodiment, even when the interlayer insulating films 28, 38, 44, and 50 having relatively weak mechanical strength are used as part of the multilayer wiring structure, the constituent elements of the semiconductor device Thus, a highly reliable semiconductor device can be provided.

 [0179] [Modified Embodiment]

 The present invention is not limited to the above embodiment, and various modifications can be made.

 [0180] For example, in the above-described embodiment, a cross-shaped opening 74 reaching the element isolation region 14 is formed in the interlayer insulating films 26, 28, 38, 44, 50, 56, 62, 68, and the cross-shaped The case where the structure 76 is embedded in the opening 74 has been described as an example. However, when a wiring or a conductor plug is formed, a part of the structure 76 is formed at the same time to form the structure 76 made of a laminate. You may do it.

 [0181] Further, in the above embodiment, the force wirings 36, 42, 48, 66, 42, 48, 54, 60, 66 and the force wirings 36, 42, 48, described as an example in which the same material is used for the structures 76, 76a. Different materials may be used for 54, 60, 66 and the structures 76, 76a.

[0182] In the above embodiment, the case where the cross-section structure 76 is formed has been described as an example. However, a cross-section structure having a Y-shape may be formed. Even when the electrode pad 78 is supported by a structure having a Y-shaped cross section, the bonding of the electrode pad 78 when bonding is performed. It is possible to prevent a large stress from being applied to the components existing below. Therefore, even when the electrode pad 78 is supported by a structure having a Y-shaped cross section, the interlayer dielectric films 28, 38, 44, and 50 having a relatively low relative dielectric constant are used, and the degree of integration is high and the reliability is high. Therefore, it is possible to provide a semiconductor device.

 [0183] In the above embodiment, the case where the structures 76 and 98a to 98d are formed by the electric plating method has been described as an example. However, the method of forming the structures 76 and 98 to 98d is an electric plating method. It is not limited. For example, the structures 76, 98 to 98d can be formed by CVD, electroless plating, spin coating, or the like.

 [0184] In the above embodiment, the case where Cu is used as the material of the structures 76 and 98a to 98d has been described as an example. However, the material of the structures 76 and 98a to 98d is not limited to Cu. For example, a metal such as tungsten, aluminum, or nickel may be used as the material for the structures 76 and 98a to 98d. Further, a nitride such as TaN may be used as a material for the structures 76 and 98a to 98d. Further, diamond, fullerene, carbon nanotube, or the like may be used as a material for the structures 76 and 98a to 98d.

 [0185] In the above embodiment, the case where SiLK (registered trademark) is used as the material of the interlayer insulating films 28, 38, 44, 50 has been described as an example. The material is not limited to SiLK (registered trademark). For example, as a material for the interlayer insulating films 26, 28, 38, 44, 50, for example, an SOG film or the like may be used.

 [0186] As the interlayer insulating films 28, 38, 44, and 50, a SiOC film formed by a CVD method or the like may be used. As a material for the strong SiOC film, for example, Coral (registered trademark) manufactured by Novellus Systems, Inc. can be used. Also, Black Diamond (registered trademark) manufactured by Applied Materials can be used as a material for the strong SiOC film. Also, as interlayer insulation films 28, 38, 44, 50, low dielectric constant FSG (Fluorinated Silicate Glass) film, MSQ (Methyl hydrogen; lsesQuioxane) film, H¾Q (Hydrogen Silses uioxane) | ¾, FSQ (F1 uorinated hydrogen SilsesQuioxane ) It is possible to use a membrane.

 [0187] Further, as the interlayer insulating films 28, 38, 44, 50, the following films formed by a coating method may be used.

[0188] For example, as interlayer insulating films 28, 38, 44, 50, insulation manufactured by Dow Cowing Silicone Co., Ltd. An HSQ film using a film material may be formed by a coating method. Further, as the interlayer insulating films 28, 38, 44, 50, a wholly aromatic aryl ether film using ALCAP-E (registered trademark) which is an insulating film material manufactured by Asahi Kasei Corporation may be formed by a coating method. . Further, as the interlayer insulating films 28, 38, 44, 50, an aryl ether film using FLARE (registered trademark) which is an insulating film material manufactured by Honeywell may be formed by a coating method. Further, as the interlayer insulating films 28, 38, 44, 50, a benzocyclobutene (BC B) film using an insulating film material manufactured by Dow Chemical Co. may be formed by a coating method. Also, as the interlayer insulating films 28, 38, 44, 50, an FSQ (fluorine-containing hydrogen silsesquioxane) film using an insulating film material provided by Fujitsu Limited and Trichemical Co. is formed by a coating method. Also good. In addition, an inorganic or organic methylsilsesquioxane (MSQ) film using LKD-T200 (registered trademark), an insulating film material made by JSR Corporation, is applied as an interlayer insulating film 28, 38, 44, 50. May be formed. Further, as the interlayer insulating films 28, 38, 44, and 50, an inorganic or organic MSQ film using HOSP (registered trademark) which is an insulating film material manufactured by Honeywell may be formed by a coating method. Further, as the interlayer insulating films 28, 38, 44, and 50, an inorganic porous HSQ film using porous HSQ which is an insulating film material manufactured by Dow Co., Ltd. may be formed by a coating method. Alternatively, an organic porous aryl ether film using ALS-400 (registered trademark), which is an insulating film material manufactured by Sumitomo Chemical Co., Ltd., may be formed as an interlayer insulating film 28, 38, 44, 50 by a coating method. Good. Further, as the interlayer insulating films 28, 38, 44, and 50, an inorganic or organic SiH-based porous film using IPS (registered trademark), which is an insulating film material manufactured by Catalytic Chemical Co., Ltd., may be formed by a coating method. . Further, as the interlayer insulating films 28, 38, 44, 50, an inorganic or organic SiO 2 CH 2 film using Nanoglass-E (registered trademark), which is an insulating film material manufactured by Hanel, may be formed by a coating method. Further, as the interlayer insulating films 28, 38, 44, 50, an inorganic or organic porous MSQ film using LKD-T400 (registered trademark) which is an insulating film material manufactured by JSR Corporation may be formed by a coating method. . Further, as the interlayer insulating films 28, 38, 44, 50, an inorganic porous silica film using ALCAP-S (registered trademark), which is an insulating film material manufactured by Asahi Kasei Corporation, may be formed by a coating method. Further, as the interlayer insulating films 28, 38, 44, 50, an organic porous aryl ether film using porous SiLK, which is an insulating film material manufactured by Dow Chemical Co., Ltd., may be formed by a coating method. Also, interlayer insulation films 28, 38, As for 44 and 50, an organic porous aryl ether film using porous FLARE, which is an insulating film material manufactured by Honeywell, may be formed by a coating method! /. Even in the case of V and misalignment, the dielectric constant of the interlayer insulating films 28, 38, 44, 50 is 3.0 or less.

 [0189] Further, as the interlayer insulating films 28, 38, 44, 50, an inorganic porous silica film using silica aerogel, which is an insulating film material manufactured by Kobe Steel, Ltd. may be formed by high pressure drying. Also in this case, the relative dielectric constant of the interlayer insulating films 28, 38, 44, 50 is 3.0 or less.

 [0190] Further, as the interlayer insulating films 28, 38, 44, 50, the following films formed by the CVD method may be used.

 [0191] For example, the interlayer insulating films 28, 38, 44, and 50 may be formed by CVD using benzocyclobutene (BCB) manufactured by Dow Chemical Co. as a raw material. Alternatively, the interlayer insulating films 28, 38, 44, and 50 made of an inorganic or organic SiOCH film may be formed by CVD using Black Diamond (registered trademark) manufactured by Applied Materials as a raw material. Alternatively, the interlayer insulating films 28, 38, 44, and 50 made of an inorganic or organic SiOCH film may be formed by a CVD method using Coml (registered trademark) manufactured by Novellus Systems as a raw material. Alternatively, interlayer insulating films 28, 38, 44, and 50 made of inorganic or organic SiOCH films may be formed by CVD using Aurora (registered trademark) manufactured by ASM Co., Ltd. as a raw material. Alternatively, the interlayer insulating films 28, 38, 44, and 50 made of an inorganic or organic MSQ coating film may be formed by a CVD method using HOSP (registered trademark) manufactured by Hanuel. In either case, the relative dielectric constant of the interlayer insulating films 28, 38, 44, 50 is 3.0 or less.

 Industrial applicability

[0192] The semiconductor device according to the present invention is useful for providing a highly reliable semiconductor device.

Claims

The scope of the claims  [1] a support substrate;  A multilayer wiring structure formed on the support substrate and having a plurality of wirings stacked via an insulating layer;  An electrode pad formed on the multilayer wiring structure;  A structure that penetrates the multilayer wiring structure and reaches the support substrate and supports the electrode pad, and has a cross-section or a Y-shaped cross section.  A semiconductor device comprising:  [2] In the semiconductor device according to claim 1,  An end of the cross section of the structure is located below an edge of the electrode pad. A semiconductor device, wherein: [3] In the semiconductor device according to claim 1 or 2,  One of the plurality of wirings is formed so as to penetrate the structure, and the wiring and the structure are insulated from each other  A semiconductor device. [4] a support substrate;  A multilayer wiring structure formed on the support substrate and having a plurality of wirings stacked via an insulating layer;  An electrode pad formed on the multilayer wiring structure;  A structure that penetrates through the multilayer wiring structure and reaches the support substrate and supports the electrode pad, the structure having a plurality of columns and beams connecting the columns to each other;  A semiconductor device comprising: [5] In the semiconductor device according to claim 4,  The support column is located below the corner of the electrode pad.  A semiconductor device. [6] In the semiconductor device according to claim 4 or 5, The first layer of the plurality of insulating layers included in the multilayer wiring structure is the plurality of insulating layers. Lower relative permittivity than the second of the layers  The beam is provided in the vicinity of the first layer.  A semiconductor device. [7] The semiconductor device according to any one of [1] to [6], wherein the wiring and the structure are insulated from each other.  A semiconductor device. [8] The semiconductor device according to any one of [1] to [7], wherein the structure and the wiring are made of the same material. .