WO2007113764A1

WO2007113764A1 - Method and system for signal control

Info

Publication number: WO2007113764A1
Application number: PCT/IB2007/051161
Authority: WO
Inventors: Joseph Rutkowski
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2006-03-31
Filing date: 2007-03-31
Publication date: 2007-10-11
Anticipated expiration: 2008-09-30
Also published as: TW200820609A

Abstract

An output signal is controlled using a circuit arrangement. The circuit arrangement has a transistor (108) with a gate coupled to a capacitor (106) and with an output coupled to the output signal and the capacitor. A current source (102) is coupled to the gate of the transistor (108). The current source (102) is configured to selectively provide an amount of current in response to an input signal (101) and to vary the amount current provided in response to a feedback signal. A feedback circuit (104) provides the feedback signal to the current source (102) and varies the feedback signal in response to a voltage at the gate of the transistor (108).

Description

METHOD AND SYSTEM FOR SIGNAL CONTROL

This application claims priority from earlier filed provisional application No. 60/788,211 titled, "Improved Drive Capability in a Zero-Power dissipation Edge Rate Control Circuit," filed on March 31, 2006. Field of the Invention

The present invention relates generally to a method and system for controlling an output signal and, more particularly, to the implementation of a circuit for controlling the signal-driving characteristics of an output signal.

Electrical systems often use interconnections to transmit information between components of the system. Such interconnections generally consist of one or more signal lines that taken together are also know as bus. To transmit the information the components of the system must drive the voltage level of the bus line to the appropriate level. Often there are bus specifications that limit how fast or slow the voltage can change in a particular system. For example, some systems use a bus protocol known as the Inter-Integrated Circuit bus, or I²C bus.

The I²C bus is a control bus that provides the communications link between integrated circuits in a system. Developed by Philips in the early 1980s, this simple two- wire bus with a software-defined protocol has evolved to become the de facto worldwide standard for system control, finding its way into everything from temperature sensors and voltage level translators to EEPROMs, general-purpose I/O, A/D and D/A converters, CODECs, and microprocessors of all kinds. US Patent 4,689,740 of Moelands et al. titled, "Two-Wire Bus-System Comprising a Clock Wire and a Data Wire for Interconnecting a Number of Stations" describes a computer system that comprises a number of station which are interconnected by means of a clock bus wire and a data bus wire that form a wired logic bus that is a function of the signals generated thereon by the stations, and is incorporated by reference in its entirety. The I²C -bus also saves space and lowers overall cost. Using I²C specification, designers can move quickly from a block diagram to final hardware, simplifying the addition of new devices and functions to an existing bus interface. As the system evolves over several generations, I²C devices can easily be added or removed without impacting the rest of the system. The two-line structure means fewer trace lines, so the PCB can be much smaller. Debug and test are easier, too, since there are fewer trace lines and a relatively simple protocol.

There are several reasons why the PC-bus has endured for more than 20 years. To begin, recently introduced hubs, bus repeaters, bidirectional switches and multiplexers have increased the number of devices the bus can support, extending the number of devices originally limited by a maximum bus capacitance of 40OpF. Also, software- controlled collision detection and arbitration prevent data corruption and ensure reliable performance, even in complex systems. Beyond performance, though, there is ease of use. Two simple lines connect all the ICs in a system. Any I²C device can be attached to a common PC-bus, and any master device can exchange information with any slave device. The software-controlled addressing scheme eliminates the need for address- decoding hardware, and there is no need to design and debug external control logic because it is already provided by the PC protocol. Additionally, the bus has kept pace with performance and today provides four levels of data rate transfer implemented using increasing clock speeds. For example, the clocks speeds can be up to 100 KHz in

Standard mode, up to 400 KHz in Fast mode, up to 1 Mhz in Fast mode plus and up to 3.4 MHz in High-Speed mode.

Per the Fast Mode Plus specification, the on-chip I²C interface includes an open drain n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pull-down device while a single pull-up resistor is common to all devices on the I²C bus. To compensate for the increased bus speed of the Fast Mode Plus the specification requires maximum edge transitions for the bus signals. The maximum rising edge transition can be met be selecting a suitably small pull-up resistor. The Fast Mode Plus specification requires the maximum falling-edge transition (70%-30%) to not exceed 120ns. In addition, to avoid susceptibility to Electromagnetic interference (EMI) and signal reflections, the minimum falling edge transition (70%-30%) cannot occur in less than 20ns. Thus, the NMOS pull-down device must be capable of controlling the edge rate to provide a falling-edge transition within the maximum and minimum requirements. This requirement is further complicated because the pull-up resistor values and bus capacitance values vary from one I²C mode to another and also from one I²C bus application to another.

One method used to control the edge rate of an NMOS pull-down device is to control the current supplied to the gate of the NMOS device. For instance, some conventional edge rate limited techniques require a continuously available current source, which comes at the cost of chip supply current. Also, continuously available current sources do not scale well with changes in supply voltage. This presents problems with the I C (and other) bus specification, which allows the user to define the part voltage as well as the bus voltage. Another slew rate limiting technique uses a resistor network. The classical resistor limited current approach has little static current once the transition is complete; however, it produces a nonlinear, RC falling edge with a slow turn-on.

These and other issues present problems in controlling the edge rate of signal- driver circuits. Accordingly, there is room for improvement in controlling an output signal driver.

Various aspects of the present invention are directed to methods and arrangements for output signal control in a manner that addresses and overcomes the above-mentioned issues.

Consistent with one example embodiment, an output signal is controlled using a circuit arrangement. The circuit arrangement has a transistor with a gate coupled to a capacitor and with an output coupled to the output bus signal and the capacitor. A current source is coupled to the gate of the transistor. The current source is configured to selectively provide an amount of current in response to an input signal and to vary the amount current provided in response to a feedback signal. A feedback circuit provides the feedback signal to the current source and varies the feedback signal in response to a voltage at the gate of the transistor.

Consistent with another example embodiment, a method for controlling an output signal is implemented. In response to an input signal, a first current amount is provided to a gate of a transistor. The gate is coupled to a capacitor and an output of the transistor is coupled to the output signal and to the capacitor. In response to a voltage at the gate of the transistor reaching a reference voltage, a second current amount is provided. The above summary of the present invention is not intended to describe each embodiment or every implementation of the present invention. Advantages and attainments, together with a more complete understanding of the invention, will become apparent and appreciated by referring to the following detailed description and claims taken in conjunction with the accompanying drawings. The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:

FIG. 1 is a block diagram of an output-signal control system, according to an example embodiment of the present invention; and

FIG. 2 is a circuit schematic diagram of an output-signal control system, according to an example embodiment of the present invention.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

The present invention is believed to be applicable to a variety of edge-rate control devices and approaches. While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.

Consistent with an example embodiment of the present invention, a circuit arrangement is implemented for controlling the edge-rate of a signal. The circuit arrangement includes a transistor for driving an output signal and a capacitor connected between the output signal and the gate of the transistor. A current source is coupled to the input of the pull-down transistor and is configured to supply current to the gate of the pull-down transistor in response to an enabling input signal. When enabled, the current source varies the amount of current supplied in response to a feedback signal provided by a feedback circuit. The feedback circuit varies the feedback signal in response to a voltage at the gate of the pull-down transistor.

Another example embodiment of the present invention, an I²C bus interface is implemented using device having an N-channel metal-oxide semiconductor field-effect transistor (NMOS) pull-down. For an I²C bus having a low load (e.g., low pull-up current and bus capacitance), a current source charges a feedback capacitor that is coupled between the output and the gate of the NMOS pull-down. This configuration is particularly useful for ensuring that the edge rate for a high-to-low transition on the I C bus meets the minimum edge rate requirements. For an I C bus having a high load (e.g., high pull-up current and bus capacitance), the current source increases the amount of current supplied to the gate of the NMOS pull-down. This current increase is implemented only after the voltage on the gate of the NMOS pull-down reaches a certain voltage or 'trip point'. This configuration is particularly useful for ensuring that the edge rate is between a minimum and maximum rates.

The increased current amount can be selected based upon maximum expected load conditions as well as the drive capabilities of the NMOS pull-down. In applications having a low load, if the trip point is not carefully selected, the increased current level could cause the edge rate to violate the minimum required timing. The time required to reach the trip point is a direct function of the feedback capacitor and the current provided. Thus, the selection of the trip point voltage can be selected to avoid too fast of an edge rate by guaranteeing the current will not be increased until after a minimum charge time.

In a particular embodiment, the current source is implemented using a variable resistor or a resistor network. The current is varied by changing the effective resistance of the variable resistor or resistor network. For example, an NMOS or similar transistor device can be electrically connected in parallel with one or more resistors in the resistor network. When the transistor is active, the parallel resistor is bypassed effectively reducing the resistance of the resistor network. In one instance, the circuit controls the voltage applied to the resistor network independent of the supply voltage. For example, the voltage drop of a diode, transistor or similar device can be electrically connected in parallel with the resistor network thereby maintaining a relatively constant voltage regardless of the supplied voltage.

In one instance, it is possible to implement several levels of provided current using multiple voltage levels or resistor network values that change in response to the gate voltage reaching one of several voltage levels. This allows the current source to progressively increase (or decrease) the current in response to the voltage of the feedback capacitor. Any number of current levels can be implemented in this manner, limited only by the desired granularity and complexity of the circuit. Turning now to the figures, FIG. 1 shows a block diagram of an edge rate control circuit according to an example embodiment of the present invention. The diagram contains input 101, current source 102, feedback control 104, capacitive feedback 106, signal driver 108 and load 110. The circuit drives a signal connected to load 110 in response to input 101. Load 110 represents the resistive, capacitive and inductive components related to the output signal connected to signal driver 108. In an I²C bus system, for example, the load is affected by the pull-up resistor value, the pull-up voltage, the capacitance of the various devices connected to the system and the interconnections between the devices of the system. In the case of the I²C specification, the pull-up resistor value and voltage can vary from application to application. For example, the pull-up resistor values are sometimes stronger (less resistance) for a fast mode plus system than for a standard mode system. Moreover, the number of devices in the system as well as the devices' individual load characteristics can vary significantly from system to system. In one embodiment of the present invention, the edge rate control circuit is configured to accommodate different loads on signal driver 108 and different I²C modes. For instance, the edge rate control circuit is configured to handle two load situations, a small load and a large load. Where load 110 is relatively small, signal driver 108 is capable of producing an edge rate that may be too fast for the specification. For such a load, signal driver 108 is limited by capacitive feedback 106. Current source 102 provides a current that creates a voltage on the input of signal driver 108 by charging capacitive feedback 106. Once the voltage reaches a threshold voltage (e.g., the gate voltage necessary for the device to conduct electricity), signal driver 108 becomes active and continues to increase its drive capabilities as the input voltage increases. The resulting change in the output voltage (dv/dt) affects the gate voltage by reducing the gate voltage as a function of dv/dt through capacitive feedback 106. Thus, the change in output voltage counteracts increased input voltage due to current source 102. In this manner, the edge-rate control circuit maintains a minimum edge rate based upon the current provided by the current source and the capacitance of the capacitive feedback 106.

In the situation where the load 110 is a relatively large load, the current source 102 begins charging the capacitive feedback 106 and the voltage differential increases across the input and output of the signal driver 108. Due to the large load, the change in voltage on the output signal slow, causing the gate voltage to continually increase. Where the load is sufficiently large, the rate at which the output voltage changes may be insufficient to meet the maximum edge rate. Thus, feedback control 104 senses such a condition (e.g., by monitoring the gate voltage) and provides feedback to the current source 102. In response to the feedback, current source 102 increases the current provided to the signal driver 108. The increased current results in an increased edge rate allowing the edge rate control circuit to meet the maximum edge rate requirement.

In one embodiment of the present invention, the current source 102 uses a resistor network and a voltage regulator to control the current supplied. For example, a voltage is applied to the resistor network resulting in a current I. In response to the feedback control 104, the resistance of the resistor network is changed resulting in a change in current I. In one instance, a voltage regulator determines the voltage applied to the resistor network, such as using one or more diodes and/or transistors to produce the voltage. This can be particularly useful for implementing an edge control circuit that works using variable supply voltages. The current source can modify the current supplied by changing the resistance of the resistor network and the voltage applied to the resistor network.

In another embodiment of the present invention, the current from current source 102 is provided using a voltage drop or threshold voltage of a diode, transistor, or similar device, and the feedback control is configured to detect when the voltage at the gate nears the supply voltage. In response to detecting such a voltage, feedback control 104 provides a feedback signal to current source 102. Current source 102 reduces the effective resistance of a resistor network used (in conjunction with the voltage drop) to generate the supplied current. This can be particularly useful to counteract the effects of the diode or transistor operating near its threshold voltage due to the voltage at the gate of signal driver 108 approaching the supply voltage of the device.

FIG. 2 shows a schematic diagram of a specific edge rate control circuit, according to an example embodiment of the present invention. FIG. 2 contains device M5 for driving the output, feedback capacitor CO, resistor network (Rl and R2), and feedback switch Mil.

Device MlO and the resistor pair Rl and R2 are used to create a current source independent of the voltage supply. When active, device MlO provides exhibits a voltage from source to gate equal to a threshold voltage. The resistor network, consisting of series resistor pair Rl and R2, is connected between the source and gate of device MlO. Accordingly, the effective charging current is VtZ(R 1+R2) as device MlO shunts current, which would otherwise cause the gate voltage to exceed the threshold voltage, to ground through device M4. The gate of device M4 is coupled to the output voltage, and thus, this path is disabled once the output voltage is within a threshold voltage of ground. The gate of device Mil is connected to the supply voltage of the circuit through resistor R3. Resistor R4 is connected to the drain of device M2. The inverted input signal created by devices M6 and MO ensures that device M2 is active when the input is low. When device M2 is active, resistors R3 and R4 create a voltage divider that is used to detect when the gate- source voltage of the output device M5 (node n5) is sufficiently above the threshold voltage of the output device. For example, where R3 is equal to R4, device Mi l will remain active until the voltage at node n5 is approximately one-half of the supply voltage. Once the voltage at node n5 reaches this point, device Mi l becomes inactive and node n6 is pulled to ground through resistor R4. Buffer 202 applies the voltage of node n6 to node n7. In one instance, the output of buffer 202 is either high or low based upon the input at node n6. More specifically, the output is high when node n6 is at or above the voltage determined by R3 and R4 and low when pulled low through R4. The source and drain of device M9 is connected across resistor R2 allowing device M9 to effectively remove resistor R2 from the resistor network by raising the voltage of node N8 to a threshold voltage above node N5.

Capacitor CO is used to throttle the output device M5 back when a light load is applied to the output (i.e. large external pull-up resistor and small bus capacitance). When an external bus capacitance is very large or the external pull-up resistor is very small the node n5 is charged by the internal pull-up current (Vt_M10)/(Rl+R2) faster than the voltage change from feedback capacitor CO (dv/dt). Thus, the voltage at node n5 continues to increase. Once node n5 reaches Vdd*(R3/(R3+R4)) + Vt_Mll, device Mil shuts off and node n6 is pulled to ground by resistor R4. This causes node n7 to fall to ground enabling device M9 to short out resistor R2. The new internal charging current is increased to Vt_M10/Rl. The increased charging current raises the voltage on node n5 more quickly, which drives output device M5 harder. Accordingly, the edge rate of the output is increased by increasing the dynamic current through the device.

When the input signal is high, device M8 is inactive and the current draw of the resistor network is at or near zero. Moreover, once the voltage at node n5 reaches a voltage near the supply voltage (e.g., supply voltage - (RO * (MlO threshold voltage * (Rl +R2)) - MlO threshold voltage - M8 threshold voltage), the current draw of the resistor network is near zero. This is particularly useful for minimizing the current draw of the circuit when the output signal driver needs little or no current.

In one embodiment of the present invention, the resistor network contains additional resistors. Moreover, these additional resistors can be selectively enabled to produce additional levels of current draw. In one instance, a second reference voltage circuit is provided similar to the circuit containing resistors R3 and R4, devices Mil and buffer 202. A second device similar to device M9 can be implemented to effectively remove one or more additional resistors from the resistive network. In one instance, the second reference voltage circuit can have a different reference voltage so as to allow successive increases in the current provided. In this manner, any number of additional reference voltage circuits can be implemented. This can be useful for providing additional granularity in the control of the supplied current.

The various embodiments described above and shown in the figures are provided by way of illustration only and should not be construed to limit the invention. Based on the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the present invention without strictly following the exemplary embodiments and applications illustrated and described herein. For instance, applications other than I²C devices may be amenable to implementation using similar approaches. Such modifications and changes do not depart from the true scope of the present invention that is set forth in the following claims.

Claims

CLAIMS:

1. For controlling an output signal, a circuit arrangement comprising: a transistor (108) having a gate coupled to a capacitor (106) and an output coupled to the output signal and the capacitor (106); a current source (102) coupled to the gate of the transistor (108), the current source (102) configured to selectively provide an amount of current in response to an input signal (101) and to vary the amount current provided in response to a feedback signal; and a feedback circuit (104) that provides the feedback signal to the current source (102) and that varies the feedback signal in response to a voltage at the gate of the transistor (108).

2. The circuit arrangement of claim 1 wherein, the current source (102) includes a semiconductor device producing an internal voltage and resistor network having a resistance value to which the internal voltage is applied.

3. The circuit arrangement of claim 2 wherein, the current source (102) varies the resistance value of the resistor network to vary the amount of current provided.

4. The circuit arrangement of claim 3 wherein, the varying of the resistance value of the resistor network is accomplished using a gate responsive to the feedback signal.

5. The circuit arrangement of claim 1 wherein, the amount of current provided by the current source (102) is significantly reduced in response to a voltage of the output signal being near a pull-up voltage for the output signal.

6. The circuit arrangement of claim 1 wherein, the output signal is part of an inter- integrated circuit bus.

7. The circuit arrangement of claim 2 wherein, the internal voltage is controlled using one of a threshold voltage and a voltage drop.

8. The circuit arrangement of claim 1 wherein, the transistor (108) is an n-channel metal-oxide-semiconductor field-effect transistor.

9. The circuit arrangement of claim 8 wherein, the output signal is connected to a pull-up voltage through a resistor.

10. A method for controlling an output signal, the method comprising: in response to an input signal (101), providing a first current amount to a gate of a transistor (108), the gate coupled to a capacitor (106), the transistor (108) having an output coupled to the output signal and the capacitor (106); in response to a voltage at the gate of the transistor (108) reaching a reference voltage, providing a second current amount.

11. The method of claim 10 wherein, the second current amount is greater than the first current amount.

12. The method of claim 10 further including the step of providing near zero current in response to the voltage at the gate of the transistor (108) reaching about a supply voltage level.

13. The method of claim 10 wherein, the current is provided using circuit having a resistor network and a voltage regulator.

14. The method of claim 13 wherein, the step of providing a second current includes changing an effective resistance value for the resistor network.

15. The method of claim 13 wherein, the voltage regulator uses one or more semiconductor threshold voltage drops to produce a voltage.

16. The method of claim 14 wherein, the step of changing the effective resistance value includes enabling a transistor device to effectively removed a resistor from the resistor network.

17. The method of claim 10 wherein, the output signal is used in an inter-integrated circuit bus.

18. For controlling an output signal, a circuit arrangement comprising: a transistor means (108) for driving an output signal; a capacitive means (106) for providing capacitive coupling between a gate of the transistor means and the output signal; a current source means (102) for providing an amount of current responsive to an input signal and to vary the amount current provided in response to a feedback signal; and a feedback circuit means (104) for providing the feedback signal to the current source means (102) in response to a voltage at the gate of the transistor means (108).