[go: up one dir, main page]

WO2007014320A3 - Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process - Google Patents

Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process Download PDF

Info

Publication number
WO2007014320A3
WO2007014320A3 PCT/US2006/029378 US2006029378W WO2007014320A3 WO 2007014320 A3 WO2007014320 A3 WO 2007014320A3 US 2006029378 W US2006029378 W US 2006029378W WO 2007014320 A3 WO2007014320 A3 WO 2007014320A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrates
substrate
plate
cleaving process
track member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/029378
Other languages
French (fr)
Other versions
WO2007014320A2 (en
WO2007014320A9 (en
Inventor
Francois J Henley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Genesis Corp
Original Assignee
Silicon Genesis Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/191,464 external-priority patent/US7674687B2/en
Application filed by Silicon Genesis Corp filed Critical Silicon Genesis Corp
Priority to JP2008524186A priority Critical patent/JP2009507363A/en
Publication of WO2007014320A2 publication Critical patent/WO2007014320A2/en
Publication of WO2007014320A9 publication Critical patent/WO2007014320A9/en
Anticipated expiration legal-status Critical
Publication of WO2007014320A3 publication Critical patent/WO2007014320A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H10P32/1204—
    • H10P95/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10P30/20—
    • H10P72/0471—
    • H10P72/30—
    • H10P90/1916—
    • H10W10/181—

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Plasma Technology (AREA)

Abstract

A method for manufacturing substrates using a continuous plasma immersion process is disclosed. A process chamber (215 having an inlet (207) and outlet (217) has a movable track member (219) contained therein. The moveable track member is used to transport the one or more substrates from the inlet, to the scanning area of chamber (215), and then to the outlet (217). The track member can be rollers, air bearings, belt members and/or a moveable beam member. The substrates are provided with a plurality of ti thereon which are subjected to the scanning implant process provided by device (213). A plurality of substrates with tiles can be sequentially processed by this method to improve throughput. An alternative to the substrates is a reusable transfer substrate member. This member has donor substrate regions which have a substrate thickness and substrate region wherein the regions do not have a definable cleave region.
PCT/US2006/029378 2005-07-27 2006-07-26 Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process Ceased WO2007014320A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008524186A JP2009507363A (en) 2005-07-27 2006-07-26 Method and structure for forming multiple tile portions on a plate using a controlled cleavage process

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/191,464 2005-07-27
US11/191,464 US7674687B2 (en) 2005-07-27 2005-07-27 Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US83328906P 2006-07-25 2006-07-25
US60/833,289 2006-07-25

Publications (3)

Publication Number Publication Date
WO2007014320A2 WO2007014320A2 (en) 2007-02-01
WO2007014320A9 WO2007014320A9 (en) 2007-09-07
WO2007014320A3 true WO2007014320A3 (en) 2009-05-07

Family

ID=37683988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/029378 Ceased WO2007014320A2 (en) 2005-07-27 2006-07-26 Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process

Country Status (4)

Country Link
JP (1) JP2009507363A (en)
KR (1) KR20080042095A (en)
TW (1) TW200746277A (en)
WO (1) WO2007014320A2 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281912B (en) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi substrate and manufacturing method thereof, and semiconductor device
EP1978554A3 (en) * 2007-04-06 2011-10-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate comprising implantation and separation steps
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
JP2009094488A (en) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd Method for manufacturing substrate with semiconductor film
TWI437696B (en) 2007-09-21 2014-05-11 半導體能源研究所股份有限公司 Semiconductor device and method of manufacturing same
JP5452900B2 (en) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 Method for manufacturing substrate with semiconductor film
JP5252867B2 (en) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor substrate
JP5325404B2 (en) * 2007-09-21 2013-10-23 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
JP5250228B2 (en) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP5506172B2 (en) * 2007-10-10 2014-05-28 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor substrate
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US8236668B2 (en) 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
TWI493609B (en) * 2007-10-23 2015-07-21 半導體能源研究所股份有限公司 Semiconductor substrate, display panel, and method of manufacturing display device
US8163628B2 (en) * 2007-11-01 2012-04-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
JP5548351B2 (en) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US20090139558A1 (en) * 2007-11-29 2009-06-04 Shunpei Yamazaki Photoelectric conversion device and manufacturing method thereof
US7947570B2 (en) 2008-01-16 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method and manufacturing apparatus of semiconductor substrate
JP5386193B2 (en) * 2008-02-26 2014-01-15 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
US20090223628A1 (en) * 2008-03-07 2009-09-10 Semiconductor Energy Laboratory Co., Ltd. Manufacturing apparatus of composite substrate and manufacturing method of composite substrate with use of the manufacturing apparatus
JP5548395B2 (en) 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
EP2401768A4 (en) * 2009-02-27 2013-07-17 Alta Devices Inc SUBSTRATES COVERED FOR EPITAXIAL DEPOSITION AND REMOVAL METHODS
US8008176B2 (en) * 2009-08-11 2011-08-30 Varian Semiconductor Equipment Associates, Inc. Masked ion implant with fast-slow scan
KR101213955B1 (en) 2010-09-20 2012-12-20 에스엔유 프리시젼 주식회사 Substrate processing apparatus
US8981519B2 (en) 2010-11-05 2015-03-17 Sharp Kabushiki Kaisha Semiconductor substrate, method of manufacturing semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescence apparatus, wireless communication apparatus, and light emitting apparatus
WO2013002227A1 (en) 2011-06-30 2013-01-03 シャープ株式会社 Method for producing semiconductor substrate, substrate for forming semiconductor substrate, multilayer substrate, semiconductor substrate, and electronic device
JP2015511989A (en) * 2011-12-23 2015-04-23 ソレクセル、インコーポレイテッド Productive semiconductor metallization and interconnect spraying
US9041147B2 (en) 2012-01-10 2015-05-26 Sharp Kabushiki Kaisha Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus
US9577134B2 (en) * 2013-12-09 2017-02-21 Sunpower Corporation Solar cell emitter region fabrication using self-aligned implant and cap
CN113788441B (en) * 2021-08-25 2023-03-24 山东永昇重工有限公司 Hanging basket and assembling method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863830A (en) * 1994-09-22 1999-01-26 Commissariat A L'energie Atomique Process for the production of a structure having a thin semiconductor film on a substrate
US20020029850A1 (en) * 1995-07-19 2002-03-14 Chung Chan System for the plasma treatment of large area substrates
US20080038908A1 (en) * 2006-07-25 2008-02-14 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61502298A (en) * 1984-08-20 1986-10-09 カルフアイアン，メグエア　ヴイ Solid-state generator of perpetual precession of electrons
US4981408A (en) * 1989-12-18 1991-01-01 Varian Associates, Inc. Dual track handling and processing system
US5486080A (en) * 1994-06-30 1996-01-23 Diamond Semiconductor Group, Inc. High speed movement of workpieces in vacuum processing
US20030045098A1 (en) * 2001-08-31 2003-03-06 Applied Materials, Inc. Method and apparatus for processing a wafer
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
US6818529B2 (en) * 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
US6800518B2 (en) * 2002-12-30 2004-10-05 International Business Machines Corporation Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering
SG115630A1 (en) * 2003-03-11 2005-10-28 Asml Netherlands Bv Temperature conditioned load lock, lithographic apparatus comprising such a load lock and method of manufacturing a substrate with such a load lock
US7126139B2 (en) * 2003-10-09 2006-10-24 The Regents Of The University Of California Device and method of positionally accurate implantation of individual particles in a substrate surface
US7019315B2 (en) * 2003-12-08 2006-03-28 Varian Semiconductor Equipment Associates, Inc. System and method for serial ion implanting productivity enhancements

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863830A (en) * 1994-09-22 1999-01-26 Commissariat A L'energie Atomique Process for the production of a structure having a thin semiconductor film on a substrate
US20020029850A1 (en) * 1995-07-19 2002-03-14 Chung Chan System for the plasma treatment of large area substrates
US20080038908A1 (en) * 2006-07-25 2008-02-14 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process

Also Published As

Publication number Publication date
TW200746277A (en) 2007-12-16
WO2007014320A2 (en) 2007-02-01
WO2007014320A9 (en) 2007-09-07
KR20080042095A (en) 2008-05-14
JP2009507363A (en) 2009-02-19

Similar Documents

Publication Publication Date Title
WO2007014320A3 (en) Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process
WO2008014339A3 (en) Method and system for continuous large-area scanning implantation process
WO2009117565A3 (en) Method and apparatus of a substrate etching system and process
WO2007117742A3 (en) Batch processing system and method for performing chemical oxide removal
WO2008058131A3 (en) Method and structure for thick layer transfer using a linear accelerator
WO2006101886A3 (en) A plasma enhanced atomic layer deposition system and method
WO2007021692A3 (en) Method and apparatus to control semiconductor film deposition characteristics
WO2011100109A3 (en) Gas distribution showerhead with coating material for semiconductor processing
WO2005104186A3 (en) Method and processing system for plasma-enhanced cleaning of system components
WO2009114120A3 (en) Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter
WO2002101854A3 (en) Coating edge control
WO2007019188A3 (en) Manufacture of photovoltaic devices
WO2005111268A3 (en) Apparatus including showerhead electrode and heater for plasma processing
NZ597658A (en) Apparatus and method for pharmaceutical production
EP1113087A3 (en) Film formation apparatus and method for forming a film
SG143230A1 (en) Multi-step dep-etch-dep high density plasma chemical vapor deposition processes for dielectric gapfills
WO2006062576A3 (en) Method and apparatus for improved baffle plate
WO2002082530A3 (en) In-situ thickness measurement for use in semiconductor processing
WO2007140425A3 (en) Process chamber for dielectric gapfill
WO2012145492A3 (en) Apparatus for deposition of materials on a substrate
WO2004068538A3 (en) Object-moving method, object-moving apparatus and production process using the method
EP1918971A3 (en) Method and apparatus for photomask plasma etching
TW200729304A (en) Methods for in-situ generation of reactive etch and growth specie in film formation processes
WO2007120776A3 (en) Plasma deposition apparatus and method for making solar cells
GB2423774B (en) Method of culturing neurons, neuron culture substrate, neurons, neuron system, and method for manufacturing neuron system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2008524186

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087004648

Country of ref document: KR

122 Ep: pct application non-entry in european phase

Ref document number: 06800446

Country of ref document: EP

Kind code of ref document: A2