WO2007009266A1

WO2007009266A1 - Asynchronous data recovery

Info

Publication number: WO2007009266A1
Application number: PCT/CA2006/001332
Authority: WO
Inventors: John W. Bogdan
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-07-20
Filing date: 2006-07-20
Publication date: 2007-01-25
Anticipated expiration: 2008-01-20

Abstract

The ADR invention recovers phases and amplitudes of data carrying pulses from an over-sampled noisy signal, and extracts data symbols by measuring pulses lengths in time intervals equal to expected symbol time. The ADR analyzes incoming waveform and provides instant compensation for line load or other interference, by utilizing plurality of different edge masks providing wide variety of instant compensations responding to past, present and future received signal conditions such as received wave form amplitude and/or steepness levels. Furthermore the ADR provides adaptive time domain compensation of cross-talk and other noise sources by introducing testing steps into the received waveform and observing their effect on a phase jitter in recovered data pulses, in order to optimize phase of an internal waveform applied back to the received waveform for compensating noise having an unknown displacement.

Description

Asynchronous Data Recovery

BACKGROUND OF THE INVENTION

1. Field of the invention

This invention is directed to providing low cost system on chip (SOC) design for asynchronous data recovery (ADR) from noisy signals.

The ADR invention defines digital means for adaptive time domain filtering of over-sampled waveforms consisting of variable lengths pulses carrying data rates ranging to 1/2 of technology's maximum clock frequency.

The ADR includes edge detecting filters (EDF) directed to signal and data recovery in wireless, optical , or wireline transmission systems and measurement systems.

The EDFs shall be particularly advantageous in system on chip (SOC) implementations of signal processing systems.

2. Background art

Mainstream prior art data recovery systems; require phase locking to the transmitter's clock, and implement frequency domain filters for noise reduction in the received waveform, and compensate line loads with a feedback signal connected from a receivers output to an input of the receiver.

However said phase locking eliminates immunity to high frequency phase noise cross-talk exceeding bandwidth of receivers PLL.

Said frequency domain filters are inefficient in responding to changing high frequency noise and often attenuate high frequency data, while prior art line load compensation offers only delayed responses involving feedback signals which may compromise accuracy and/or stability of line receivers.

In particular, such mainstream prior art uses frequency domain filters for recovering data from serially transmitted pulses. Since serially transmitted pulses must have widely variable lengths and frequencies, such frequency domain filters can not eliminate high frequency phase jitter and attenuate useful part of signal while filtering high frequency noise. Both deficiencies mentioned above are eliminated in the prior art presented in WO 2004/002052 by

Bogdan (the same inventor); wherein a received signal is densely over-sampled and phases and amplitudes of data carrying pulses and phases of their edges are recovered without causing any signal attenuation, and a number of data symbols contained in the pulse is deteπnined by measuring length of such pulse instead of relying on sampling pulse amplitude with a phase aligned clock targeting a middle of symbol time periods.

Another type of a mainstream prior art is represented by frequency domain filters dominating signal processing area. Such prior art frequency domain filters are inherently inefficient and inaccurate in detecting phase of data carrying signals; while accurate and reliable phase detection is becoming essential for efficient modern communication based on FM, PM, or NRZ/PAM over copper/fiber which use signal transitions between limited set of discrete levels and transitions phases as the means for data encoding.

Such deficiency of the mainstream frequency domain filters working as amplitude noise filters and spending processing resources ineffectively on recovering all intermediate signal amplitudes, has been eliminated in the prior art presented in CA 2,453,292, 07 July 2005, Bogdan (the same inventor); wherein the NFED solution is focusing entirely on improving recovery of signal transients relevant to transmitted data, while avoiding said spending resources on calculations of intermediate amplitudes which are determined by the transients recovered.

3. ADR contributions

This invention contributions over prior art comprise:

Enhancing the advantages of said WO 2004/002052 and CA 2,453,292 standing alone solutions by upgrading them into the Asynchronous Data Recovery (ADR) method and apparatus, wherein such upgrade enables by one order (>5x) better immunity to phase and amplitude noise than those achievable with the stand alone solutions.

Furthermore the ADR adds using plurality of preprogrammed already edge masks which can be instantly re-selected for accommodating very fast changes of line load or other noise or interference by providing instant predictive response to received unfϊltered data with time domain compensation of present line load and cross-talk noise, wherein this ADR invention; analyzes currently incoming waveform and provides instant compensation for combinations of noise with other factors, by utilizing plurality of different edge masks providing wide variety of compensations responding to past, present and future received signal conditions including waveform amplitude and/or steepness levels.

Still furthermore the ADR adds a unique ability to provide highly efficient adaptive time domain compensation of cross-talk and other major noise sources, wherein; a gradient of averaged phase jitter, of recovered data pulses, is calculated and analyzed while testing phase steps are introduced into an internal waveform further used for compensating noise components having a predictable shape, and based on such analysis a relation between said gradient and said phase steps is estimated and used to calculate optimum phase displacement of the internal waveform which is applied back to the received waveform in order to compensate said predictable noise components.

ADR invention responds to insatiable demand for higher throughput & connectivity by enabling 2x longer distances or 2x higher data rates than prior art on copper/optical links including 1OG Ethernet and high speed backplanes.

SUMMARY OF THE INVENTION

The ADR invention enables using over 10 times higher sampling rates than prior art, by contributing means for continuos processing of resulting very high samples rates with over 10 times higher throughput than prior art.

Therefore, ADR allows benefiting from all the fundamental advantages of dense oversampling and time domain processing for data rates over 10 times higher than those still manageable for prior art in time domain processing. While such higher data rates involve higher noise levels requiring fundamentally superior time domain filtering, prior art solutions are limited to using much lower sampling rates and frequency domain filters which are unreliable for low signal to noise ratios.

The ADR invention allows adaptive time domain filtering of high speed high noise signals by implementing instant predictive response to received unfiltered data which provides time domain compensation of present line load and cross-talk noise.

The ADR analyzes currently incoming waveform and provides instant compensation for combinations of noise with other factors. Such ADR utilizes plurality of different edge masks for providing wide variety of compensations responding to past, present and future wave-form conditions.

The ADR contributes a unique ability to provide highly efficient time domain compensation of cross-talk and other major noise sources. In accordance to the ADR invention a gradient of averaged phase jitter, of recovered data pulses, is calculated and analyzed while testing phase or amplitude steps are introduced into an internal waveform which can be used for compensating noise components such predicting shape.

Based on such analysis a relation between said gradient and said phase steps is estimated and used to calculate optimum phase or shape displacement of the internal waveform which is applied back to the received waveform in order to compensate such predicted noise components.

The ADR invention comprises an edge detecting filter (EDF) for time domain filtering of waveform pulses transmitting serial streams of data symbols with data rates reaching Vi of maximum clock frequency of IC technology. The EDF comprises: a means for continues waveform over-sampling with sampling frequencies several times higher than the maximum clock frequency; and a means for elimination of phase jitter from edges of the pulses and elimination of amplitude glitches from insides of the pulses as well; and a system for adaptive noise filtering based on analysis of captured unfiltered portions of the over-sampled waveform.

The removal of amplitude glitches from pulses insides enables significant increase of transmission distance, since such removal eliminates any need for a band limiting low-pass filter attenuating received signal by two times.

The unique ability of EDF to remove glitches from insides of received pulses without any attenuation of amplitude of the pulses, constitutes major contribution over prior art obvious for those skilled in the art.

The presented invention of Asynchronous Data Recovery (ADR) comprises a pulse lengths processor of over-sampled signal (PLPOS) which continuously over-samples an incoming signal, keeps comparing a set of captured samples including or surrounding any particular sample with a set of samples expected at a signal edge occurrence (further named edge mask), uses results of such comparisons for detecting edge occurrences at said particular samples, uses timing of such detected edges for defining lengths of pulses representing constant amplitude of the incoming signal, and uses said lengths of pulses for extracting data transmitted by the signal or for analysis of other signal properties.

The ADR further comprises a parallel processor of correlated edges of over-sampled signal (PPCE) which continuously over-samples an incoming signal by capturing samples occurring in time instances defined by outputs of a delay line of a sampling clock, performs parallel calculations of correlation integrals for multiple consecutive time instances by integrating deviations between a set of said captured samples surrounding any such time instance and a set of samples expected at an edge occurrence defined by an edge mask, uses such correlation integrals for detecting said edge occurrences at particular time instances, uses timing of such detected edges for defining lengths of pulses representing constant amplitude of a filtered signal, and uses said lengths of pulses for extracting data transmitted by the signal or for analysis of other signal properties.

As far as said high throughput is concerned; the closest prior art other than said WO 2004/002052 is represented by processing pipelines. However prior art pipelines can perform only simple separate logical operations, and are limited to processing separate sets of samples from specific limited intervals of processed waveform.

The ADR invention achieves much better performances than the prior art pipelines by combining listed below improvements. 1. The ADR enables performing arithmetical and complex logical operations in eveiy sequential stage of its synchronous pipeline which enables continuous processing of unlimited intervals of over 10 times oversampled waveform carrying data rates reaching 1/2 of maximum clock frequency.

2. Said continuous processing of infinite waveform intervals is enabled by a means for passing a result of a previous interval processing operation to another operation using such previous result as one of arguments for next interval processing. Such results passing can be provided between consecutive sequential stages or between consecutive stages located in parallel pipelines as well.

3. The invention includes splitting such sequential stages into multiple parallel phases performing multiple parallel operations, wherein a time overlap between neighbouring parallel stages equals to a phase single cycle. Such splitting allows multiplication of cycle processing times available in said parallel phases. Consequently said splitting allows accommodation of more complex arithmetical operations such as correlation integrals calculations. On the other hand merging such parallel phases saves hardware and/or enables combining all the data produced in the multiple parallel phases into a single data stream.

4. Said complex arithmetical and logical operations can be combined into any required sequence of micro-cycles with every micro-cycle performed by its dedicated sequential stage. Since any number of such highly diversified sequential stages and parallel phases can be connected into a synchronous sequential processor (SSP), almost over 10 times higher throughput for complex signal processing operations can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG.l shows Sequential Clocks Generation (SCG) and Clocks Selectors(CS); wherein these circuits define timing of the ADR system

FIG.2 shows Interleaved A/D Converters producing 16 Samples/Symbol.

FIG.3 shows Capturing samples of odd symbols in the Phase 1/WaveRegister.

FIG.4 shows Capturing samples of even symbols in the Phase2/WaveRegister.

FIG.5 shows Phases 11&12 Averaging Filters (11AR3&12AR3); wherein average of amplitude over a symbol period surrounding any particular sample belonging to the phases 11 and 12, is calculated in two processing micro-steps and stored in the Phasel l/AveragesReg.3 and Phase 12/AveragesReg.3.

FIG.6 shows Phasel 1 Differences & Transition- Area Processors, wherein; for every particular sample belonging to the Phasel 1 such' processors calculate amplitude difference between said averages of the previous symbol and the next symbol, and produce indicator G=I / 0 if the particular sample belongs / does not belong to a transition area where an edge of data carrying pulse can be expected.

FIG.7 shows Phase 11 / Preliminary Localization of Transitions, wherein; a maximum average difference in the particular transition area is identified in order to be used for identifying an edge mask closest to a set of samples surrounding a pulse edge expected in this area.

FIG.8 shows Ph.11 / Masks Selection for Correlation Processing. FIG.9 shows Ph.11 / Parallel Processing of Correlation Integrals. FIG.10 shows Phasel I / Edge Localization, wherein positioning of the edge and data symbol

(defined by edges final amplitude) following the edge are identified. FIG.l 1 shows Phasel 1 / Symbols Identification, wherein symbols detected in previous phases are retimed into next phases for as long as the next edge ending this data pulse is not detected. FIG.12 shows Phasel 1 / Symbols Attachments based on Pulses Lengths. FIG.12A shows Phasel 1 / Measurements of Phase Jitter, wherein; a fractional phase error, between actually encountered lengths of the data pulse and a closest integral number of sampling periods, is calculated in order to be further used for calculating said averaged phase jitter. FIG.13 shows Phasel / Attaching Symbols and Merging Phases 11&12. FIG.14 shows Attaching Symbols and Merging Phases 1&2.

GENERAL DESCRIPTION OF THE INVENTION

The first part of the ADR invention involves application of the edge detecting filter (EDF) described below.

The EDF enables: continues waveform over-sampling with sampling frequencies >10 times higher than the maximum frequency of data carrying serial pulses; elimination of phase jitter from edges of the pulses and elimination of amplitude glitches from insides of the pulses as well; a system for adaptive noise filtering based on analysis of captured unfiltered portions of the over-sampled waveform.

The EDF invention provides an implementation of programmable algorithms for noise filtering for a very wide range of low and high frequency wave-forms. The EDF enables >10 times faster sampling and processing than prior art digital filters.

The EDF configuration uses: a synchronous sequential processor (SSP) for capturing and real time processing of an incoming waveform (see the end of this section); a wave-from screening & capturing circuit (WFSC) (see the end of this section); a programmable control unit (PCU) for supporting adaptive noise filtering and edge detection algorithms;

The EDF produces a correlation integral, between a captured set of binary values surrounding a particular bit of a captured waveform and produces an edge mask comprising a programmed set of binary values. Such correlation integral serves as an indicator of proximity between the surrounded bit and an expected edge of the waveform. Therefore the correlation integral is also named edge proximity figure (EPF). Such EPFs are further used to define edge timing.

Producing the correlation integral and defining edge timing comprise:

• performing logical and/or arithmetic operation on any bit of the captured set and its counterpart from the edge mask;

• integrating results of said operations perfonned on all the bits of the captured set, in order to estimate the EPF for the surrounded bit;

• defining a waveform transition area by comparing the EPF with an edge threshold, wherein a set of bits having EPFs located on a predefined side of the threshold defines the wavefoπn transition area where an edge is expected.

• Finding the most extreme EPF by comparing all the EPFs belonging to the same waveform transition area, wherein such EPF identifies a bit position localizing a filtered edge.

The EDF further comprises: modulation of locations of detected rising and/or falling waveform edges; wherein an edge modulating factor (EMF) modifies edge thresholds which are subtracted from to or added to the

EPFs before such modified EPFs are used for finding edge locations; using an edge modulation control register (EMCR) programmed by the PCU₅ for defining function performing said modifications of edge thresholds.

The EDF still further comprises displacing detected edges by a preset number of bits, in order to compensate for inter-symbol interference ISI or other duty cycle distortions.

The EDF invention further includes:

• using the WFSC for programmable screening of the over-sampled unfiltered wave-form, and for capturing screened out wave-form intervals, and for communicating said captured intervals and other results to the PCU;

• programmable waveform analysis and adaptive noise filtering algorithms;

• edge mask registers for providing said edge masks used for detecting rising and/or falling waveform edges;

• edge threshold registers for providing said edge thresholds used for detecting rising and/or falling waveform edges;

• edge displacement registers for providing said edge displacement numbers used for shifting detected rising and/or falling edges by a programmable number of bits of waveform processing registers;

• filter control registers which control; said logical and/or arithmetic operations conducting the comparison of captured waveform bits with the edge mask, and said edge displacements in the processed waveforms;

• using the PCU for calculating and loading said edge mask registers and/or said edge threshold registers and/or said edge displacement registers and/or said filter control registers;

• using the PCU for controlling said calculations of the EMF by presetting the EMCR in accordance with adaptive noise filtering algorithms.

• using the PCU for controlling and using the WFSC operations for implementing adaptive filters by controlling noise filtering edge detection stages of the SSP.

More complete definition of the EDF invention is provided below.

The EDF invention comprises: a wave capturing circuit for capturing an incoming wave-form sampled by sub-clocks produced by the outputs of the delay line which the sampling clock is propagated through; a circuit performing logical or arithmetic operations on particular samples of the edge mask and their counterparts from the wave-form samples surrounding the consecutive analyzed sample of the captured wave-form; using the results of said operations for defining a filtered location of an edge of the waveform. Such EDF further comprises: a filter arithmometer for comparing the edge mask with the captured wave-form in order to introduce noise filtering corrections of the edges of the filtered wave-form; a filter mask register providing the edge mask which is compared with the captured wave-form of an input signal and/or filter control register which provides code for controlling operations of said filter arithmometer in order to provide said corrections of the filtered wave-form.

The EDF compares said edge mask samples of the expected edge pattern with samples from a consecutive processed region of the captured wave-form. Consequently the EDF comprises: accessing any said consecutive processed region of the captured wave-form and using such region as comprising samples corresponding to the edge mask samples; selection of a consecutive sample from the edge mask and simultaneous selection of a corresponding consecutive sample from the processed region of the captured wave-form; calculating a correlation component between such selected samples by performing an arithmetical or logical operation on said selected samples; calculating a digital correlation integral by adding said correlation components calculated for single samples of the edge mask.

The EDF includes calculating correlation integrals for said consecutive processed regions uniformly spread over all the captured wave-form, wherein the calculated correlation integrals are further analyzed and locations of their maximums or minimums are used to produce said filtered locations of said edges of the filtered wave-form;

Such EDF operations comprise: moving said processed region by a programmable number of samples positions of the captured wave-form; storing and comparison of said correlation integrals calculated for different processed regions, in order to identify said maximums or minimums and their locations; using said locations of said maximums or minimums for producing the filtered locations of the edges of the filtered wave-from.

In addition to the off-line analysis of unfϊltered samples, collected by the WFSC, and adaptive filtering provided by the PCU; the EDF offers unique ability to analyze currently incoming waveform and to provide instant predictive compensation to presently appearing combinations of noise with line-load and other factors. Such EDF utilizes plurality of different edge masks providing wide variety of compensations responding to past, present and future wave-form conditions. Such predictive EDF further comprises: an apparatus for continuous time domain analysis of a rate of amplitude change of the over-sampled waveform; a circuit for producing quantitative estimates of the change rates; a circuit for using said rates estimates for identifying transition areas of the waveform, wherein said transition areas define time intervals wherein pulse amplitude is switching between different levels; a circuit for using such rate estimate for instant selection of one of multiple edge masks which is most effective in filtering out noise from the transition area characterized by the rate estimate.

The predictive EDF further includes stabilizing said predictive response by using a pre-fϊltered waveform having improved noise immunity, for producing said rates estimates; wherein the EDF comprises: x using averaging filters to produce the pre-filtered waveform, which is used for the analysis producing said rates estimates; identifying transition areas by comparing rates estimates with a threshold of transition area (TTA); defining the transition areas as time intervals where said rate estimates exceed +/- TTA range; selecting the most extreme value of the rate estimates occurring in the transition area and using the such extreme value for choosing one of the edge masks; identifying an initial or final pulse amplitude for the present transition area and using it as additional factor in choosing the edge mask; and/or identifying pulse amplitudes surrounding past and/or future transition areas and using them as additional factors in choosing the edge mask; and/or selecting the most extreme value of the rate estimates occurring in the past and future transition areas and using the selected values as additional factors in choosing the edge mask, using an address encoder for edge masks memory (AEEMM) for transforming a set of the mask choosing factors, mentioned above, into an effective mask address.

The EDF further comprises using the PCU and the WFSC for slower off-line adaptive programming of the masks memory with most effective set of edge masks.

The EDF includes means for correcting pulse lengths distortions caused by variations of transmission line load resulting from varying past levels of transmitted signal wherein estimates of a present line load are produced during said processing of said pulse lengths and such line load estimates are further used for correcting a final pulse lengths; the PPCE further comprising: an apparatus for producing said line load estimate while current pulse lengths is processed following the detection of a leading edge of the pulse; an apparatus_for using such line load estimate for correcting positioning of the trailing detected edge of the current pulse in order to compensate said expected pulse length distortion caused by past variations of incoming signal levels.

The EDF further includes corrections of the current pulse length taking into account an impact of previous pulses lengths on said positioning of the trailing edge of the current pulse in addition to the impact of said current pulse length; the EDF further comprises: an apparatus for accumulating properly weighted said line load estimates of previously processed pulses of the signal; an apparatus for combining such accumulated load estimates with the line estimate produced for the current pulse of the signal; an apparatus for using such combined line load estimate for correcting positioning of the trailing detected edge of the current pulse in order to compensate said expected pulse lengths distortion caused by the past variations of incoming signal levels.

The EDF includes compensation of inter-symbol interference (ISI) or other predictable noise by adding a programmable displacement to said filtered location of the edge of the wave-form.

Therefore the EDF comprises: programmable amendment of the filtered location of the wave-form edge by presetting said programmable displacement with a new content; using such newly preset displacement for shifting the filtered location of the next detected edge.

The ADR includes compensation of periodical predictable noise with programmable modulations of said filtered locations of the wave-form edges by using an edge modulating factor (EMF) for a periodical diversification of said edge thresholds corresponding to different said regions of the wave-form; wherein the EDF comprises: modulation of the filtered locations of the wave-form edges by using the edge modulating factor

(EMF) for modulating said edge thresholds; subtracting such modulated thresholds from the correlation integrals calculated in said different wave-form regions or adding such modulated thresholds to the correlation integrals calculated in said different wave-form regions; using such reduced or increased correlation integrals for locating said maximums or minimums defining locations of filtered edges, whereby said EMF provides such modulation of the edge thresholds, that predictable noise introduced to consecutive wave-form samples by known external or internal sources, is compensated. The ADR further includes: using an edge modulation control register (EMCR) programmed by the PCU, for said modulation of the edge thresholds.

The ADR comprises: sequential processing stages configured into a sequential synchronous pipeline driven synchronously with said sampling clock. The ADR further comprises parallel processing phases implemented with said synchronous sequential pipelines; wherein: said parallel processing phases are driven by clocks having two or more times lower frequencies than said sampling clock; consecutive parallel phases are driven by clocks which are shifted in time by one or more periods of said sampling clock; The ADR comprises using multiple noise filtering sequential stages in eveiy parallel processing phase for extending said wave-form filtering beyond a boundary of a single phase.

Such ADR further includes an over-sampled capturing of consecutive wave-form phases in corresponding phases wave registers which are further rewritten to wave buffers with overlaps which are sufficient for providing all wave samples needed for a uniform filtering of any edge detection despite crossing boundaries of the wave buffers which are loaded and used during different said phases; wherein the ADR comprises: rewriting the entire wave register belonging to one phase into the wave buffer of the same phase and rewriting an end part of said wave register into a front part of the next phase wave buffer, while the remaining part of the next wave buffer is loaded from the wave register belonging to the next phase; whereby every wave buffer contains entire said wave-form regions needed for calculating said EPF's corresponding to the samples belonging to the phase covered by this buffer.

The ADR includes: merging of said parallel processing phases, wherein multiple said parallel processing phases are merged into a smaller number of parallel phases or into a single processing phase, when passing from one said sequential processing stage to the next sequential stage, splitting of said parallel processing phases, wherein one said processing phase is split into multiple parallel processing phases or multiple parallel processing phases are split into even more parallel phases, when passing from one said sequential processing stage to the next sequential stage.

The ADR comprises a pulse lengths processor of over-sampled signal (PLPOS) which continuously over-samples an incoming signal, keeps comparing a set of captured samples including or surrounding any particular sample with a set of samples expected at a signal edge occurrence (further named edge mask), uses results of such comparisons for detecting edge occurrences at said particular samples, uses timing of such detected edges for defining lengths of pulses representing constant amplitude of the incoming signal, and uses said lengths of pulses for extracting data transmitted by the signal or for analysis of other signal properties; wherein the PLPOS comprises: a circuit for generation of sampling clock instances providing time resolution which is multiple times higher than a minimum resolution allowing over-sampling of the incoming signal; a circuit for continuous sampling of incoming signal amplitude at said time instances and for capturing resulting continuously incoming samples in a wave-form register; a circuit for comparing said set of captured samples, including or surrounding any particular sample, with the edge mask; . a circuit for using results of said comparisons for detecting accurate timing of the signal edges; a circuit for using the timing of the detected edges for calculating the lengths of said pulses characterized by constant amplitudes of the incoming signal; a circuit for using said lengths and said amplitude of the pulses for extracting data from the incoming signal or for said analysis of other properties of the incoming signal.

The ADR invention further comprises parallel processing of correlated edges of over-sampled signal (PPCE) which continuously over-samples an incoming signal by capturing samples occurring in time instances defined by outputs of a delay line of a sampling clock, performs parallel calculations of correlation integrals for multiple consecutive time instances by integrating deviations between a set of said captured samples surrounding any such time instance and a set of samples expected at an edge occurrence defined by an edge mask, defines waveform transition area as time interval having said correlation integrals greater or smaller than an edge threshold, and identifies positioning of a filtered edge as equal to a position of most extreme correlation integral in the transition area; wherein the PPCE comprises: parallel correlation integral processors (CIPs) for producing said correlation integrals, wherein one said CIP dedicated to one said time instance produces correlation integral relating to that time instance by integrating all said deviations between the captured set of samples surrounding that time instance and the expected set defined by the edge mask wherein any such deviation is calculated as an estimate of a difference between a sample from said surrounding area and a corresponding element from the edge mask; parallel threshold comparators (PTCs) for comparing said correlation integrals with preprogrammed edge thresholds and for defining transition area as containing con-elation integrals located inside a transition range defined by said thresholds; an extreme value selector (EVS) for finding most extreme value of correlation integral within the transition range, wherein a time instance having the most extreme correlation integral defines position of a filtered edge of the waveform; a pulse lengths processor (PLP) for defining precise lengths of pulses representing constant amplitude of a filtered signal based on timing of the detected edges, and for extracting data transmitted by the signal or for analysis of other signal properties by processing said lengths of the pulses; whereby by using multiple said CIPs for producing multiple correlation integrals relating to said time instances and by using multiple said PTCs and the EVS for said edges detections, locations of filtered signal edges are identified and said edges locations enable the PLP to define the lengths of signal pulses and to perfoπn data extraction or other signal analysis functions.

The ADR includes the PLPOS defined above, further comprising means for correcting pulse lengths distortions caused by variations of transmission line load resulting from varying past levels of transmitted signal wherein estimates of a present line load are produced during said processing of said pulse lengths and such line load estimates are further used for correcting a final pulse lengths; the PLPOS further comprising: means for producing said line load estimate while current pulse lengths is processed following the detection of a leading edge of the pulse; means for using such line load estimate for correcting positioning of the trailing detected edge of the current pulse in order to compensate said expected pulse length distortion caused by past variations of incoming signal levels.

The PLPOS invention further includes corrections of the current pulse length take into account an impact of previous pulses lengths on said positioning of the trailing edge of the current pulse in addition to the impact of said current pulse length; the PLPOS further comprising: means for accumulating properly weighted said line load estimates of previously processed pulses of the signal; means for combining such accumulated load estimates with the line estimate produced for the current pulse of the signal; means for using such combined line load estimate for correcting positioning of the trailing detected edge of the current pulse in order to compensate said expected pulse lengths distortion caused by the past variations of incoming signal levels.

The PLPOS still further includes a line load compensation (LLC) for correcting pulse lengths distortions caused by variations of transmission line load resulting from vaiying past levels of transmitted signal, wherein the LLC produces estimates of a present line load and uses such line load estimates for selecting such said edge masks which are load dependent (further named load dependent edge masks LD-EMs) and are able to correct said pulse lengths distortions; the PLPOS further comprising: means for producing said line load estimates by processing previously captured samples of transmitted signal; means for applying variety of said LD-EMs wherein any particular LD-EM can correct positioning of detected edges in order to compensate distortions of incoming signal caused by line loads corresponding to that particular LD-EM; edge mask selector using said line load estimates for selecting said LD-EMs which correct positioning of detected edges in order to compensate said expected pulse lengths distortions caused by past variations of incoming signal levels.

The PLPOS invention further comprises: means for an analysis of error rates or phase jitter in data symbols recovered after using said compensation of incoming signal; means for using results of said analysis for improving said LD-EMs towards lowering bit error rates.

The ADR invention further includes circuit for Adaptive Phase Locking (APL) of an internal receiver's waveform, such as crosstalk compensating waveform or receiver's clock, to a component of a received waveform, such as transmission line cross-talk or digital data pulses, wherein both the internal waveform and the component of the received waveform have similar shapes, wherein averages of phase jitter of the data pulses are calculated while testing phase steps are introduced into the internal waveform phase and the APL uses changes of the jitter averages resulting from the tesing phase steps to define phase modifications of the internal waveform which minimize phase jitter of resulting digital data pulses representing data recovered from the received waveform, such APL comprises: a circuit for digital over-sampling of the received waveform, wherein sampling time instances divide any symbol interval of the received waveform into multiple sampling instances spaced equally in time; a circuit for capturing said over-sampled waveform; an internal waveform generator (IWG) for defining said internal waveform as a series of numbers defining amplitudes of the internal waveform corresponding to said sampling instances of the received waveform; a phase modifier circuit (PMC) modifying the internal waveform by introducing said testing phase steps into the internal wave form by shifting the entire waveform by a fixed number of said sampling instances; a data recovery circuit (DRC) using the internal waveform modified with the phase steps during a recovery of said digital data pulses form the received waveform, wherein the internal waveform is used for compensating a deterministic noise in the received waveform resulting from echo or cross-talk or clock deviations between transmitter and receiver; a jitter calculating circuit (JCC) calculating said changes of the average phase jitter of the recovered data pulses corresponding to said testing phase steps; an APL control circuit (APLCC) for providing said testing phase steps to the PMC and for analyzing said averaged jitter changes calculated by the JCC and for using results of said analysis for defining an optimum relation between phase/frequency of the internal waveform and the compensated component of the received waveform; wherein said definition of the optimum phase/frequency relation is introduced into said internal noise compensating waveform used for minimizing phase jitter of the recovered data pulses and for maximizing receiver's immunity to noise.

The ADR includes said PCU for analyzing results of said real time signal processing form the SSP and for controlling operations of the SSP; wherein the PCU comprises: means for reading results of captured signal processing from the SSP; means for programming the filter mask register and/or the filter control register and/or said presetting of the programmable displacement and/or the edge modulating factor, which are applied for achieving said filtering of the captured wave-forms.

The ADR includes a wave-form screening and capturing circuit (WFSC) for capturing pre-selected intervals of unfiltered over-sampled wave-form; wherein the WFSC comprises: using programmable screening masks and/or programmable control codes for verifying incoming wave-form captures for compliance with said programmable screening masks. buffering captured wave-form for which the pre-programmed compliance or non-compliance has been detected, or for counting a number of said detections; communicating said buffered wave-form and a detections counter to the PCU.

The PCU reads resulting captured signals from the WFSC and controls operations of the WFSC; wherein the PCU comprises: programming the screening masks and/or the control codes for performing said verification of captured wave-forms compliance or non-compliance with said screening patterns; reading verification results and/or reading captured wave-forms which correspond to the preprogrammed verification criteria.

The ADR includes using said PCU for adaptive noise filtering; wherein the PCU comprises: means for programmable waveform analysis; means for loading edge masks memory which provides said edge masks used for detecting rising and/or falling wave-form edges; or means for loading an edge thresholds memory or edge threshold registers which provide said edge thresholds used for detecting rising and/or falling waveform edges; or means for loading edge displacement registers which provide said edge displacements used for shifting detected rising and/or falling edges by a programmable number of samples positions of the captured wave-form; or means for loading filter control registers which control said logical and/or arithmetic operations conducting the comparison of captured wave-form samples with the edge mask, and said edge displacements in the processed wave-forms; or means for controlling said EMF by presetting the EMCR in accordance with adaptive noise filtering algorithms.

General definition of the SSP is provided below, The SSP includes real time capturing and processing of in-coming wave-form and a programmable computing unit (PCU) for controlling SSP operations and supporting adaptive signal analysis algorithms.

Said SSP comprises an over-sampling of incoming wave-form level by using a locally generated sampling clock and its sub-clocks generated by the outputs of serially connected gates which the sampling clock is propagated through. If an active edge of the wave-form is detected by capturing a change in a wave-form level, the position of the captured signal change represents an edge skew between the wave-form edge and an edge of the sampling clock.

Eveiy said edge skew amounts to a fraction of a sampling clock period.

The SSP invention comprises measuring time intervals between active wave form edges, as being composed of said edge skew of a front edge of the incoming waveform, an integer number of sampling clock periods between the front edge and an end edge, and said edge skew of the end edge of the wave-form.

The SSP passes incoming signal through multiple serially connected processing stages with every stage being fed by data from the previous stage which are clocked-in by a clock which is synchronous with the reference sampling clock. Since every consecutive stage is driven by a clock synchronous to the same reference sampling clock, all the stages are driven by clocks which are mutually synchronous but may have some constant phase displacements versus each other.

The synchronous sequential processor (SSP) multiplies processing speed by splitting complex signal processing operation into a sequence of singular micro-cycles, wherein: every consecutive micro-cycle of the complex operation is performed by a separate logical or arithmetical processing stage during a corresponding consecutive time slot synchronous with a reference clock providing a fundamental timing for a synthesized wave-form; serially connected sequential stages are connected to a programmable control unit (PCU), wherein the sequential stages are clocked by reference sub-clocks generated by a reference propagation circuit built with serially connected gates which the reference clock is propagated through; wherein the PCU controls operations of the sequential stages by synchronous reading of selected outputs of the sequential stages and by supplying SSP control registers with control codes which said sequential stages utilize during their operations, wherein said PCU reading of the selected outputs and said supplying of the control codes are synchronized with predefined reference sub- clocks assuring known PCU response times.

Furthermore this invention includes the SSP circuit upgraded into a parallel multiphase processor (PMP) by extending the time slot allowed for the micro-cycles of the synchronous sequential processor by a factor of P, wherein: 2-P stages are added to the original sequential stage and every one of the resulting 1-P parallel multiphase stages is clocked with a corresponding 1-P phase sub-clock, wherein such 1-P phase sub-clock begins during the corresponding to that phase 1-P cycle of the reference clock and has a cycle which is P times longer than the reference clock cycle; whereby consecutive 1-P parallel multiphase stages have processing cycles overlapping by 1 cycle of the reference clock wherein every 1-P parallel processing stage has P times longer cycle time equal to the cycle time of the corresponding 1-P phase sub-clock used for timing that stage.

The parallel multiphase processor further comprises: a parallel processing phase 2-P built with plurality of 2-P parallel multiphase stages which are connected serially and are driven by the phase sub-clocks belonging to the same 2-P phase.

The SSP invention further comprises a parallel multiphase processing of incoming signal by assigning consecutive parallel phases for the capturing of edge skews and/or processing of other incoming wave-form data with clocks which correspond to consecutive sampling clocks.

Consequently the SSP invention comprises using 1 to N parallel phases which are assigned for processing incoming signal data with clocks corresponding to sampling clock periods numbered from 1 to N, as it is further described below:

• circuits of phase 1 process edge skews or phase skews or other incoming signal data with a clock which corresponds to the sampling clock period number 1 ;

• circuits of phase2 process edge skews or phase skews or other incoming signal data with a clock which corresponds to the sampling clock period number 2;

• finally circuits of phase N process edge skews or phase skews or other incoming signal data with a clock which corresponds to the sampling clock period number N.

Said parallel multiphase processing allows N times longer capturing and/or processing times for said multiphase stages, compared with a single phase solution.

The SSP invention includes parallel stage processing of incoming signal by providing multiple processing stages which are driven by the same clock which is applied simultaneously to inputs of output registers of all the parallel stages.

The SSP further comprises a synchronous sequential processing of incoming signal by using multiple serially connected processing stages with every stage being fed by data from the previous stage which are clocked-in by a clock which is synchronous with the sampling clock.

Since every consecutive stage is driven by a clock which is synchronous to the same sampling clock, all the stages are driven by clocks which are mutually synchronous but may have some constant phase displacements versus each other.

The SSP further comprises:

• merging of processing phases which occurs if multiple parallel processing phases are merged into a smaller number of parallel phases or into a single processing phase, when passing from a one processing stage to a next processing stage;

• splitting of processing phases which occurs if one processing phase is split into multiple processing phases or multiple processing stages are split into even more processing stages, when passing from a one processing stage to a next processing stage.

The SSP invention includes a sequential clock generation (SCG) circuit which provides clock selectors for said sub-clocks which are mutually overlapping. Such selected sub-clocks are further used; to generate SSP clocks which drive said parallel phases and said sequential stages, and to generate phase selection signals for said merging and splitting of processing phases. The SSP invention includes time sharing of said parallel phases: which is based on assigning a task of processing of a newly began wave-form pulse to a next available parallel processing phase. The SSP comprises a sequential phase control (SPC) circuit, which uses results of a wave edge decoding and said SSP clocks, for performing said time sharing phase assignments and for further control of operations of an already assigned phase. The SSP comprises passing outputs of a one parallel phase to a next parallel phase, in order to use said passed outputs for processing conducted by a following stage of the next parallel phase. The outputs passing is performed: by re-timing output register bits of the one phase by clocking them into an output register of the next parallel phase simultaneously with processing results of the next parallel phase. The SSP further comprises all the possible combinations of the above defined: parallel multiphase processing, parallel stage processing, synchronous sequential processing, merging of processing phases, splitting of processing phases, and outputs passing. The SSP invention includes processing stage configurations using selectors, arithmometers, and output registers, which are arranged as it is defined below:

• input selectors select constant values or outputs of previous stages or outputs of parallel stages or an output of the same stage to provide arithmometer inputs, and arithmometer output is clocked-in to an output register by a clock which is synchronous to the sampling clock;

• multiple arithmometers are fed with constant values or outputs of previous stages or outputs of parallel stages or an output of the same stage, and an output selector selects an arithmometer output to be clocked-in to an output register by a clock synchronous to the sampling clock; • the above defined configuration as being supplemented by using an output of an output selector of a parallel processing stage for controlling output selector functions.

Proper arrangements of said parallel and sequential combinations and said stages configurations provide real time processing capabilities for very wide ranges of signal frequencies and enable a wide coverage of very diversified application areas.

General Description of the WFSC is provided below.

The wave-form screening and capturing circuits (WFSC) comprises:

• using programmable data masks and programmable control codes for verifying incoming wave-form captures for compliance or non-compliance with a pre-programmed screening patterns;

• buffering captured data for which the pre-programmed compliance or non-compliance have been detected;

• counting a number of the above mentioned detections;

• communicating both the buffered captured data and the number of detections, to an internal control unit and/or to an external unit;

• using programmable time slot selection circuits for selecting a time interval for which waveform captures shall be buffered and communicated to the PCU.

Said PCU comprises implementation of the functions listed below:

• programming of verification functions and patterns for checking captured wave-forms for compliance or non-compliance with the patterns;

• reading verification results and reading captured wave-forms which correspond to the preprogrammed verification criteria; '

• reading captured wave-forms which can be pre-selected by the PCU arbitrarily or based on other inputs from the SSP;

• programming of noise filtering functions and noise filtering masks for filtering captured waveforms;

• reading results of real-time wave-form processing from the SSP, processing the results and providing control codes and parameters for further real-time wave-form processing in the SSP, in accordance with adaptive signal processing algorithms;

• reading output data from the SSP, interpreting the data, and communicating the data to external units. The WFSC allows the PCU to screen signal quality of incoming wave form, by applying programmable screening functions using programmable data masks, as it is listed below:

• content of said wave buffers can be verified for compliance or non compliance with a mask provided by the PCU, based on verification functions and verification tolerances which are programmed by the PCU;

• if any wave buffer verification detects preset by PCU screening out criteria to be met, the corresponding content of a wave buffer is captured and made available for PCU for further analysis;

• in addition to the wave buffer capturing, a number of said screened out results will be counted and communicated to the PCU as well.

In addition to the above mentioned screening; the WFSC allows also the PCU to select arbitrarily a content of any of the wave buffers during any particular time slot; for being captured and made available for analysis by the PCU.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The preferred embodiment implements the above defined general components of the ADR in a configuration particularly useful for receivers of PAM (Pulse Amplitude Modulation) signals belonging to the very mainstream of the present Ethernet technology.

Said EDF comprises over-sampling the incoming waveform Vin with the 8 interleaved A/D converters producing 16 samples per symbol (see FIG.2.).

Resulting samples, of consecutive wave-form intervals corresponding to PAM data symbols, are captured in specifically dedicated consecutive wave registers, wherein odd intervals are written into the wave register IWR and even intervals are written into the wave register 2WR (see FIG.3 and FIG.4).

Therefore; incoming stream of samples is split into the two parallel processing phases (sometimes named as parallel synchronous pipelines), and such splitting is necessary in order to avoid an overriding of already captured data with next samples captured with continuously overlapping series of sub-clocks of a sampling clock. Furthermore, such splitting into 2 parallel phases doubles cycle time available in the sequential stages following the register IWR and in the stages following the 2WR as well. The first processing phase begins in the wave register IWR and the ^"second begins in the register 2WR.

A sequential clock generation circuit (see SCG in FIG.l) includes clock selectors further used for splitting a steady stream of mutually overlapping sub-clocks spaced by a gate delay only into sub-sets of sub-clocks active during their dedicated phases only and non-active during all other phases. Detailed generation of such selected sub-clocks is shown in FIG.3 and FIG.4. Such subsets are used for providing timing for their dedicated phases, as it is shown in the FIG.5-FIG.14.

The sampling clock period is selected to be equal to 1/4 of a symbol period of a data stream received in the incoming waveform.

While said A/D converters produce 16 samples / symbol, A/Ds outputs are captured: in the IWR during original 4 cycles of the sampling clock (see l/lClkO-l/4Clkl2 in FIG.3), and in the 2WR during the next 4 cycles (see 2/lClkO-2/4Clkl2 in FIG.4).

In order to provide longer micro-processing cycles; said phase 1 is further split into parallel phases 11 and 12, and said phase 2 is further split into phases 21 and 22. Clocks needed for driving the phases 11 and 12 are generated using the 11/12FF, and clocks for the phases 21 and 22 are selected using the 21/22FF (see FIG.5).

Said pre-filtering needed for preparing signal enabling reliable masks selections is implemented with amplitude averaging filters shown in FIG5. The averaging filter of phase 11, calculates arithmetic averages for all 16 samples long sequences of captured samples. Since the phase 11 buffer 11BUF2 and the phase21 buffer 21RB2 provide 2x16 consecutive samples, the averaging filter of phase 11 can only calculate averages for the 16 samples sequences centered around bits contained in the second half of the 11BUF2 and in the first half of the 21BUF2. Therefore resulting averages specified in the 11 AR3 are shifted ahead of the WRl by 8 samples. As processing cycles of the 1 1BUF2 and the 21BUF2 stages are four symbols long and the 21Bu£2 stage is delayed by one symbol; the averaging filter of the phase 11 has 3 symbols long cycle available for performing 16 averaging operations in parallel and for loading their results into the 11AR3. The averaging filters of the phases 21/12/22 are performed identically but every one of them is delayed in time by 1 symbol period compared to preceding them phases 11/21/12.

Said definition of transition areas for phase 11 is shown in FIG.6.

The phase 11 averages, available in the 1 AR3, are subtracted form the next symbol averages, available for 3 symbol periods in the next phases averaging register 12AR3, using 16 parallel difference arithmometers (DA). Resulting differences are loaded into the difference register 11DR4. Such differences represent said estimates of amplitude change rates per next sampling period.

Every one of the 16 D(k) differences is connected to one of the 16 parallel comparators checking if Modulus(D(k)) is greater than positive threshold for transition area TTA(k) preprogrammed by the PCU for the particular kth sampling instance. Results of said comparisons are loaded in the transition comparisons register 11TCR5.

Since phase 11 transition area may spread over to the previous phase, the 22TCR5 from the previous phase is re-timed into the 11TCRB5 (see FIG.6) in order to use both of them simultaneously for identifying whole transition areas with the selector of transition areas (STA). The STA identifies transition areas which need to be processed during phase 11 operations although they may extend into the previous phase 22. The 32 bit STA; activates bits of the transition area register 11TAR6 which identify locations of up to 2 continues transition areas, and resets all remaining bits.

Resulting active outputs of the 11TAR6 are used by the selector of extreme differences (SED) to define its search areas while identifying extreme differences. After locating the extremes the ^• SED encodes their locations into the LED(2:1) loaded into the extreme locations register 11ELR7 (see FIG.6). As there may be 2 transition areas, the two sets of pointers to the extreme differences enable accessing and using two sets of extreme differences and averaging amplitudes for best selection of edge masks providing instant compensation of line load and other noise causing factors. Edge masks selection is shown in FIG.8. This embodiment selects edge mask with set of pointers comprising: an amplitude average at the point having extreme difference detected for the future symbol period

(see the 11AB7 in FIG.7 and the 11AB4 in FIG.6 and the 11 AR3 in FIG.5, and see the

11ARB7 in FIG.7); a difference between said point's average and an average of a parallel point occurring one period later (see 11DB7 in FIG.7 and the 11DR4 in FIG.6, and see 11DRB7 in FIG.7)); an averages difference between the extreme point and a parallel point occurring one period earlier

(see the 11DRB7 in FIG.8 and the 11DRRB7 in FIG.7 and notice that the 11DRRB7 /

11DRB7 are phase22 equivalents of the 11DB7 / 11DRB7 shifted in time by one symbol period). Since the extreme's point may occur anywhere between the beginning of the present symbol and the end of the earlier symbol, said extreme's average may belong to the present symbol or to the earlier one. The selected extreme's average and differences represent the set of mask choosing factors which is provided to the address encoder for edge mask memory (AEEMM) which produces memory address loaded to the maskl/mask2 address registers (1M1AR8/1M2AR8). This embodiment is based on the assumptions that the TTA; prevents transition areas from being longer than 8 samples, and causes gaps, between said areas, to be longer than 2 samples.

Circuits calculating correlation integrals are shown in the FIG.9.

While said pre-filtering allowed stable immune to noise selection of edge masks, nevertheless it may cause changes to the original unfiltered signal which may compromise quality mask based noise filtering.

Therefore unfiltered wave-form samples are used for calculating said correlation integrals in the stage 9 (the unfiltered samples are carried through all the buffering stages from the 1B3 to 1B9 shown in FIG.6).

All needed samples are loaded in the buffers 11RB9 / 11B9 while the 21B9 from the phase 21 is used based on its availability during last 3 symbol periods. Furthermore both masks are loaded in the registers 1M1R9 and 1M2R9, and mask selector encoder uses mask 2 pointers SDR2 and EDP2 to encode mask selection signals which are loaded to the mask 2 selection register M2SR9. Said mask selection signals re-timed by M2SR9 are named Se32-Sel and are used for controlling application of the mask 2 to a second transition area defined by the mask 2 pointers.

For eveiy wave-form sample Sk, its correlation integral processor CIP performs basic operations explained below: Surrounding elements S^₊i of said element S_k, are defined using 1 ranging from -7 to +8. For every such S_k a deviation DSu from a corresponding mask element Mi is calculated as

Modulus of (S_k+1-Mi) . Consequently for every said waveform sample Sk , its correlation integral is calculated as equal to:

Such correlation integrals are loaded into the correlation integrals register 1 ICIRlO which passes the integrals to the Parallel Threshold Comparator (PTC). The PTC is also connected to the edge thresholds (EdgThr(ET32:ETl)) preprogrammed by the PCU.

Since this embodiment correlation integrals result from adding positive deviations between single samples and their mask counterparts, minimum values of such integrals indicate edge occurances.

Cozisequently subtracting the integrals 1 lCIR10(Int32:Intl) from their counterparts from the the EdgThr(ET32:ETl) is performed by the Parallel Integrals Modifier (PIM) in order to enable modifications of the integrals with said programmable edge thresholds.

Resulting modified integrals are loaded into the modified integrals register 1 IMIRl 1.

The modified integrals 11MIR(MI32:MI1) are used by the extreme values selector (shown as EVS in FIG.10) for identifying every edge location as a sampling instance having most extreme MI(k) value between all the integrals located in the same transition area defined by the transition areas buffer 1 ITABl 1. Encoded by the EVS locations of extreme integers LECl and LEC2, are loaded into the locations of extreme correlations register (1 ILECRl 2) together with corresponding next symbol amplitudes TINA and T2NA provided by the next amplitude buffers 11 T INAB and 11 T2NAB 11. Said next symbol amplitudes define pre-filtered values of received data symbols which follow their leading edges detected at said extreme integers.

The TINA and T2NA are inserted into the phased symbol register 1 IPSR 13 (see FIG.l 1); as received data symbols IS and 2S, together with their leading edges positions PlS and P2S. If no active edge is detected during a time slot corresponding to the phase 11; the last symbol (identified by the last detected edge) is carried into the phase 11 in the last symbol re-timing buffer 1 ILSRB 13 and will be inserted as phase 11 data symbol during the next processing stage shown in FIG.12.

The FIG.12 shows how pulses lengths are measured in sampling periods defined by the sub-clocks of the sampling clock, wherein the sampling clock period is very close to the symbol period defined by the transmitter's clock. Such pulse lengths measurements are used for determining ^ number of data symbols contained in every pulse contained between its limiting edges. These pulse lengths measurements and resulting attachments of next data symbols (see the ACOfDL and the ENAS and the 1 INASRl 4); are performed on symbols per phase basis. If no new edge is detected during present phases, every phase attaches one more symbol defined by the last active edge (carried over through the 1 ILSRB 13 or one of the

21LSRB13/12LSRB13/22LSRB13). Such attachments of long pulses data by adding one symbol per every phase which the long pulse is stretching over, represent and further explain the use of the pulse lengths processing for this inventions data recovery. Measurements of phase jitter are shown in the FIG.12A, wherein modulus of pulse length rounding error is calculated whenever an active edge is detected and is rounded to the a closest ideal position expected at pulse length equal to a multiple of the symbol period. Resulting modulus of phase jitter is stored in the pulse length rounding error register 11 PLRERl 4.

While consecutive phases 11/21/12/22 process corresponding to them transition areas and produce pulses liming edges, these 4 parallel phases are interleaved in time. Consequently they produce 4 interleaved data streams, which need to be integrated into a single stream before passing the recovered data to the outside world. Such data merging is implemented in two steps presented in FIG.13 and in FIG.14. The first step merges two consecutive phases 11&21 into a single phase 1 (see FIG.13) and merges the two other consecutive phases 12&22 into another single phase 2 (its drawing would be identical to the FIG.13). Any merging phase 11 or 21 may detect 1 or 2 edges in its transition areas and high noise levels may displace edges as well. In order to accommodate resulting uncertainties, a maximum number of 4 symbol • slots is provided in the attached symbols register IASRl 5. In order to define position which phase 2 symbols will be attached to during the second merging step between phase 1 and phase 2, the total number of symbols merged during the first step is calculated and loaded into the phase 1 number of attached symbols register INASRl 5. In addition to that; the phase 1 last edge register (1LASR15) indicates if any edge occurred during the phase 1 and/or defines position of the last active edge during the phase 1.

The second step of phase merging (see FIG.14) is conducted similarly as the first step.

During the first and the second steps of phase merging the pulse length rounding error calculated in their original phases 11/21/12/22 are added and the total of jitter errors is loaded to the pulse length rounding errors register PLRERl 6 shown in the FIG.14. Furthermore; during the first and the second merging steps the last edge symbol number registers

ILESNRl 5 and LESNRl 6 accumulate and store a number of a last symbol ended with an active edge occurrence (i.e. the last symbol in the same symbols stream packed in the same pulse). At the same time; the last edge registers ILERl 5 and LERl 6 define exact positions of last active edges terminating said last symbols having their numbers stored in the ILESNR 15 and LESNRl 6. After reading the LERl 6 and the LESNRl 6 the PCU uses them for high precision measurements of phase misalignment between the local sampling clock and the signal transmitter's clock carried in the received waveform. Such phase errors measurements allow the PCU to maintain frequency alignment between the sampling clock and the transmitter's clock using a digital frequency locked loop having a stable low bandwidth arrangement.

The final results are provided in the resulting number of attached symbols (NASRl 6) and the last edge register (LASR) and and the attached symbols register (ASRl 6) and in said PLRERl 6. Availability of said final results is communicated to the PCU with the Read_RQ Interrupt.

Claims

CLAIMSWhile the invention has been described with reference to particular example embodiments, further modifications and improvements which will occur to those skilled in the art, may be made within the purview of the appended claims, without departing from the scope of the invention in its broader aspect.Numerous modification and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.What is claimed is:

1. A method and an apparatus for asynchronous data recovery or analysis (ADRA) including an apparatus for a recovery of data carrying pulses from an over-sampled noisy signal by detecting phases and amplitudes of said pulses edges while amplitudes determined by a final amplitude of the previous edge are assumed for sampling instances occurring between the previous and the next edges, and a pulse lengths processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring lengths of the pulses; the ADRA comprising: a parallel processor of correlated edges of over-sampled signal (PPCE) for continuous over- sampling of an incoming signal by capturing samples occurring in time instances determined by a sampling clock, and for performing parallel calculations of correlation integrals for multiple consecutive time instances by integrating deviations between a set of said captured samples surrounding any such time instance and a set of samples defined by an edge mask as the set expected at an edge occurrence, and for analyzing such correlation integrals in order to detect said edge occurrences at particular time instances; the PLP for defining lengths of said pulses contained between the detected edges wherein pulses internal amplitudes remain constant between their edges, and for using such length of the pulses for extracting data transmitted by the signal or for analysis of other signal properties.

2. A method and a system for asynchronous data recovery with noise compensation (ADRNC) including a parallel processing system (PPS) for a recovery of data carrying pulses from an over- sampled noisy signal by detecting phases and amplitudes of said pulses edges while amplitudes determined by a final amplitude of the previous edge are assumed for sampling instances occurring between the previous and the next edges, and a noise compensating system (NCS) for compensation of currently occurring noise sources such as line load or crosstalk or inter-symbol interference, and a pulse lengths processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring lengths of the pulses; the ADRNC comprising: the parallel processing system of correlated edges of over-sampled signal (PPS) for continuous over-sampling of an incoming signal by capturing samples occurring in time instances determined by a sampling clock, and for performing parallel calculations of correlation integrals for multiple consecutive time instances by integrating deviations between a set of said captured samples surrounding any such time instance and a set of samples expected at an edge occurrence defined by an edge mask, and for analyzing such correlation integrals in order to detect said edge occurrences at particular time instances; the NCS for analyzing received signal waveform or other waveforms or noise sources such as data received or transmitted over the received signal channel or neighboring channels, and for estimating noise or interference contributions of such waveforms or such noise sources to the received signal waveform, and for modifying the edge masks applied and/or PPS operations in order to compensate for said noise or interference contributions; the PLP for defining lengths of said pulses contained between the detected edges wherein pulses internal amplitudes remain constant between their edges, and for using such length of the pulses for extracting data transmitted by the signal or for analysis of other signal properties.

3. A method and a system for asynchronous data recovery with adaptive noise compensation (ADRANC) including a parallel processing system (PPS) for a recovery of data carrying pulses from an over-sampled noisy signal by detecting phases and amplitudes of said pulses edges while amplitudes determined by a final amplitude of the previous edge are assumed for sampling instances occurring between the previous and the next edges, and an adaptive noise compensating system (ANCS) for compensation of currently occurring noise sources with an internal waveform constructed by using an adaptive testing procedure, and a pulse lengths processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring lengths of the pulses; the ADRANC comprising: the parallel processing system of correlated edges of over-sampled signal (PPS) for continuous over-sampling of an incoming signal by capturing samples occurring in time instances determined by a sampling clock, and for performing parallel calculations of correlation integrals for multiple consecutive time instances by integrating deviations between a set of said captured samples surrounding any such time instance and a set of samples expected at an edge occurrence defined by an edge mask, and for analyzing such correlation integrals in order to detect said edge occurrences at particular time instances; the ANCS for calculating and analyzing a gradient of averaged phase jitter of recovered data pulses while testing phase steps are introduced into the internal waveform, and for estimating a relation between said gradient and said phase steps in order to find an optimum phase displacement of the internal waveform, and for applying such internal waveform back to the received signal waveform in order to compensate said noise components; the PLP for defining lengths of said pulses contained between the detected edges wherein pulses internal amplitudes remain constant between their edges, and for using such length of the pulses for extracting data transmitted by the signal or for analysis of other signal properties.

4. A method and an apparatus for asynchronous data recovery (ADR), including an edge detecting filter (EDF) for recovering data carrying pulses from a noisy signal by detecting their edges occurrence times and edges amplitude limits wherein the EDF identifies sampling instances localizing such edges and uses a final amplitude of the previous edge for defining pulse amplitudes at sampling instances located between the previous and the next edges, and a pulse length processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring length of the pulses; the ADR comprising: the EDF for recoveiy of the data carrying pulses from the noisy received signal, by over-sampling the received signal, and by identifying sampling instances defining said edges occurrence times, and by recovering final amplitudes of the edges, and by recovering pulse amplitudes between such edges as equal to those determined by such final amplitude of the pulse leading edge; the PLP for recovering originally transmitted data from such recovered pulses, wherein a type of data symbols carried by such pulse is determined by said recovered pulse amplitude while a number of such data symbols contained within the pulse is estimated by measuring length of the pulse in time interval units equal to an expected symbol time.

5. A method and an apparatus for asynchronous data recovery (ADR) including an edge detecting filter (EDF) for recovering data carrying pulses from a noisy signal by detecting their edges occurrence times and edges amplitude limits wherein the EDF identifies sampling instances localizing such edges and assumes amplitudes defined by a final amplitude of the previous edge for sampling instances located between the previous and the next edges, and a pulse length processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring length of the pulses; the ADR comprising: the EDF for recovery of the data carrying pulses from the noisy received signal, by over-sampling the received signal, and by identifying sampling instances defining said edges occurrence times, and by recovering final amplitudes of the edges, and by recovering pulse amplitudes between such edge occurrences as equal to those determined by such final amplitude of the pulse leading edge; the PLP for recovering originally transmitted data from such recovered pulses, wherein a type of data symbols carried by such pulse is determined by said recovered pulse amplitude while a number of such data symbols contained within the pulse is estimated by measuring length of the pulse in time interval units equal to an expected symbol time; wherein the EDF derives steepness estimates of the received signal measured as amplitude change rate in time and uses such steepness estimates for recovering said edges occurrence times.

6. A method and an apparatus for asynchronous data recovery (ADR) including an edge detecting filter (EDF) for recovering data carrying pulses from a noisy signal by detecting their edges occurrence times and edges amplitude limits wherein the EDF identifies sampling instances localizing such edges and assumes amplitudes determined by a final amplitude of the previous edge for sampling instances located between the previous and the next edges, and a pulse length processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring length of the pulses; the ADR comprising: the EDF for recovery of the data carrying pulses from the noisy received signal, by over-sampling the received signal, and by identifying sampling instances defining said edges occurrence times, and by recovering final amplitudes of the edges, and by recovering pulse amplitudes between such edge occurrences as equal to those determined by such final amplitude of the pulse leading edge; the PLP for recovering originally transmitted data from such recovered pulses, wherein a type of data symbols carried by such pulse is determined by said recovered pulse amplitude while a number of such data symbols contained within the pulse is estimated by measuring length of the pulse in time interval units equal to an expected symbol time; wherein the EDF calculates a correlation integral by summarizing deviations or inner products between samples belonging to a set of samples surrounding an analyzed signal sample and corresponding samples belonging to an edge mask wherein the edge mask defines a set of samples expected within said surrounding set if said edge occurs at the analyzed sample; and wherein the EDF identifies said edge phase defining instance as that having most extreme value of the correlation integral indicating that such phase defining instance is the closest one to the edge expected, while said edge amplitude limits are defined by the amplitudes of the edge mask applied.

7. A method and an apparatus for asynchronous data recovery (ADR) including an edge detecting filter (EDF) for recovering data carrying pulses from a noisy signal by detecting their edges occurrence times and edges amplitude limits wherein the EDF identifies sampling instances localizing such edges and assumes amplitudes determined by a final amplitude of the previous edge for sampling instances located between the previous and the next edges, and a pulse length processor (PLP) for recovering data from the pulses by estimating number of data symbols contained in the pulses by measuring length of the pulses; the ADR comprising: the EDF for recovery of the data carrying pulses from the noisy received signal, by over-sampling the received signal, and by identifying sampling instances defining said edges occurrence times, and by recovering final amplitudes of the edges, and by recovering pulse amplitudes between such edge occurrences as equal to those determined by such final amplitude of the pulse leading edge; the PLP for recovering originally transmitted data from such recovered pulses, wherein a type of data symbols carried by such pulse is determined by said recovered pulse amplitude while a number of such data symbols contained within the pulse is estimated by measuring length of the pulse in time interval units equal to an expected symbol time; wherein the EDF derives steepness estimates of the received signal measured as amplitude change rate per time and uses such steepness estimates for selecting an edge mask representing a set of samples expected around a sampling instant which an edge occurs at, or the EDF estimates received signal amplitudes at the beginning and at the end of a pre-selected time interval surrounding currently analyzed said sampling instant and uses such initial and final amplitude estimates for selecting an edge mask representing a set of samples expected around a sampling instant which an edge occurs at; and wherein the EDF identifies said edge phase defining instance as that having said surrounding samples closest to the selected mask samples while said edge amplitude limits are defined by the amplitudes of the mask applied.