WO2007007589A1 - Field effect transistor and method for manufacturing same - Google Patents

Abstract

Disclosed is a group III nitride semiconductor field effect transistor having excellent operation stability which is able to be manufactured at high yield. Specifically disclosed is an HJFET (100) comprising a group III nitride semiconductor layer structure including a heterojunction between a GaN channel layer (112) and an AlGaN electron supply layer (113), a source electrode (101) and a drain electrode (103) formed separately from each other on the group III nitride semiconductor layer structure, and a gate electrode (102) arranged between the source electrode (101) and the drain electrode (103). An SiN film (121) is provided on the group III nitride semiconductor layer structure in a region between the gate electrode (102) and the drain electrode (103). At the interface between the SiN film (121) and the AlGaN electron supply layer (113), the impurity concentration in the AlGaN electron supply layer (113) is not more than 1E17 atoms/cm3.

Description

 Specification

 Field effect transistor and manufacturing method thereof

 Technical field

 [oooi] The present invention relates to a field effect transistor using a group m nitride semiconductor and a method of manufacturing the same.

 Background art

 [0002] GaN and other group III nitride semiconductors have a large band gap, a high breakdown electric field, and a large saturation drift velocity of electrons compared to GaAs semiconductors. Therefore, high-temperature operation, high-speed switching operation, and high-power operation It is expected to be a material that realizes excellent electronic devices in terms of

 [0003] In addition, since group III nitride semiconductors have piezoelectricity, they can utilize high-concentration two-dimensional carrier gas generated at the heterojunction due to spontaneous polarization and piezoelectric polarization force due to the heterojunction structure. It has the feature that it can operate by a mechanism different from that of a GaAs-based semiconductor field effect transistor driven by carriers generated by doping.

 [0004] In such a group III nitride semiconductor device, as carrier gas is generated at the heterojunction, a negative charge is induced on the surface of the semiconductor layer structure, which greatly affects various characteristics of the transistor. Therefore, the development of surface negative charge control technology is important. This point will be explained below.

[0005] It is known that in a layered structure of a group III nitride semiconductor including a heterojunction, a large charge is generated in the channel layer due to piezoelectric polarization or the like, while a negative charge is generated on the surface of the semiconductor layer such as AlGaN. (Non-patent document 1). These negative charges directly affect the drain current and have a strong effect on device performance. Specifically, when a large negative charge is generated on the surface, the maximum drain current during the alternating current operation is deteriorated as compared with direct current. This phenomenon is hereinafter referred to as current collapse. Current collabs are a peculiar phenomenon that is not so common in GaAs heterojunction devices and is not observed, and is notably observed in group III nitride semiconductor devices. [0006] Conventionally, current collabs have been reduced by forming a surface protective layer to solve these problems. In a structure without a protective film, sufficient drain current cannot be obtained when a high voltage is applied because of current collabs, and it is difficult to obtain the advantage of using a group III nitride semiconductor material. In addition, the effect of suppressing current collabs differs depending on the material using the protective film, and it is generally known that SiN is highly effective in suppressing current collabs. Hereinafter, an example of a conventional transistor having a protective film will be described.

 FIG. 28 is a cross-sectional view showing a configuration of a conventional hetero-junction field effect transistor (hereinafter referred to as HJFET). The HJFET shown in FIG. 28 is reported in Non-Patent Document 2, for example.

 In the HJFET 200 of FIG. 28, a buffer layer 211 made of A1N, a GaN channel layer 212 and an AlGaN electron supply layer 213 are stacked in this order on a sapphire substrate 209. On top of this, a source electrode 201 and a drain electrode 203 are formed, and these electrodes are in ohmic contact with the AlGaN electron supply layer 213. A gate electrode 202 is formed between the source electrode 201 and the drain electrode 203, and the gate electrode 202 is in Schottky contact with the AlGaN electron supply layer 213. In the uppermost layer, a SiN film 221 is formed as a surface protective film.

 Next, a method for manufacturing HJFET 200 will be described. First, on a substrate 209 having sapphire power, a semiconductor is grown by, for example, a molecular beam epitaxy (MBE) growth method or a metal organic vapor phase epitaxy (MOVPE) growth method. In this way, in order from the substrate side, the buffer layer 211 (film thickness 20 nm) made of undoped A1N, the undoped GaN channel layer 212 (film thickness 2 μm), and the AlGaN electron supply layer 213 (film) made of undoped AlGaN A semiconductor layer structure with a thickness of 25 nm) is obtained.

Next, a part of the epitaxial layer structure is etched away until the GaN channel layer 212 is exposed, thereby forming an element isolation mesa (not shown). Then, after forming a photoresist in a predetermined region of the AlGaN electron supply layer 213, a metal such as TiZAl is deposited on the AlGaN electron supply layer 213, and a source electrode 201 and a drain electrode are formed using a lift-off method or the like. 203 is formed. And by annealing it at 650 ° C, An ohmic junction is formed between these electrodes and the AlGaN electron supply layer 213.

[0011] Subsequently, after forming a photoresist in a predetermined region of the AlGaN electron supply layer 213, Ni (upper layer) ZAu (lower layer) is deposited on the A1 GaN electron supply layer 213 as a metal film for a gate electrode, for example. Then, by lift-off, the gate electrode 202 which is in Schottky junction with the AlGaN electron supply layer 213 is formed. Then, Sii ^ 22l03I thickness 50 nm) is formed by plasma CVD method or the like. With the above procedure, the HJFET 200 shown in FIG. 28 is obtained. Non-Patent Document 1: UK Mishra, P. Parikh, and Yi— Feng Wu, “AlGa N / GaN HEMTs —An overview of device operation and application s.” Proc. IEEE, vol. 90, No. 6, pp. 1022 —1031, 2002 Non-Patent Document 2: International 'Electron' Device 'Meeting' Digest (IEDM01—381-384), Ando (Y. Ando)

 Disclosure of the invention

 [0012] However, the inventors of the present invention have studied the HJFET obtained by the above-described manufacturing method, and even when a surface protective film is provided, the characteristics of the obtained transistor may vary, or sufficient drainage may occur. It became clear that the current could not be obtained.

 [0013] The present inventor has inferred such a cause as follows.

 First, the reason why sufficient drain current does not flow is that impurities introduced into the interface between the AlGaN electron supply layer 213 and the SiN film 221 during the manufacturing process form interface states, and carriers are trapped. Was inferred. When interface states are formed by impurities, current collapse occurs, which causes the drain current to decrease.

Here, the current collapse has a trade-off relationship with the gate breakdown voltage. The negative polarization charge generated on the AlGaN surface has a great influence on the transistor characteristics depending on the electrical properties of the protective film (passivation film) deposited on the AlGaN surface. In general, when a large negative fixed charge is present on the surface, a high gate breakdown voltage can be obtained, but current collaboration during AC operation tends to increase. On the other hand, when the negative charge amount on the surface is small, the gate breakdown voltage is low, but the current collab is small. Transistor operation is generally governed by this trade-off, but the AlGaN (upper layer) ZGaN (lower layer) heterostructure generates negative charges on the surface, for example, on the order of 1 E13 atoms Zcm ^2, so the quality of the surface passivation As a result, the above-described trade-off relationship appears very markedly. It is not uncommon for the pressure resistance value to change by an order of magnitude depending on the state of surface passivation. Such a large change is a phenomenon that cannot be seen in a Ga As transistor. Conversely, Group III nitride semiconductor transistors are devices that are extremely sensitive to surface conditions, and in order to stably obtain high performance with a high yield, it is necessary to improve the surface conditions. It is necessary to pay close attention to control.

 [0015] Secondly, the variation in transistor characteristics that still occurs even when the SiN film 221 is provided includes, for example, a variation in efficiency during the operation of the transistor. As a result of the examination by the present inventors, it has been inferred that the variation in the gate leakage current of the HJFET 200 is caused by the variation in the Schottky characteristics of the gate electrode 202 as the cause of the variation in efficiency during the operation of the transistor. Thus, when the cause of the variation in the Schottky characteristics of the HJFET 200 was further investigated, impurities introduced into the interface between the AlGaN electron supply layer 213 and the SiN film 221 also affected the Schottky characteristics. It was found. This point will be described below.

 [0016] During the manufacturing of the conventional HJFET 200, the surface of the AlGaN electron supply layer 213 is exposed. For this reason, a photoresist is formed on the surface of the AlGaN electron supply layer 213 in the manufacturing process. Also, when removing the resist, it is exposed several times to plasma damage due to plasma ashing. In addition, high-temperature annealing during ohmic electrode formation is performed with the surface of the AlGaN electron supply layer 213 exposed.

[0017] The concentration of impurities such as oxygen at the interface between the surface of the group III nitride semiconductor layer 213 of the HJFET 200 and the gate electrode 202 obtained through such a manufacturing process is determined by SIMS (secondary ion mass spectrometry). When measured, it was about lE18atomsZcm ^{3 to} lE19atomsZcm ³ . The impurity concentration increases as described above because the surface force of the AlGaN electron supply layer 213 is more damaged by plasma damage during the electrode formation process described above or by exposure to the atmosphere after high-temperature annealing. This is thought to be easy to be done. In order to clean the surface of the AlGaN electrode layer 213, etching with an acid or the like is effective for etching. Yes, metal is attacked and ohmic deterioration occurs. For this reason, It is difficult to sufficiently clean the surface state by ching.

[0018] Thus, in the HJFET 200, the surface state of the AlGaN electron supply layer is easily affected by the process. For this reason, the surface of the AlGaN electron supply layer 213 is in a state different from the initial clean state due to a change in crystallinity of the semiconductor. Examples of such states are:

 (i) a state in which the semiconductor crystal has changed due to plasma damage or high-temperature annealing, and

(ii) A state in which oxygen is mixed into the surface of the AlGaN electron supply layer by exposure to the atmosphere.

 Next, measurement results of the Schottky characteristics of the obtained HJFET 200 will be described. FIG. 25 (a) and FIG. 25 (b) are graphs comparing the characteristics of the HJFET 200 (FIG. 28) obtained by the conventional manufacturing method and the HJFET 100 (FIG. 1) of an example described later. Here, Schottky barrier height φ (eV) (Fig. 25 (a)) and idealization factor in HJFET obtained with 10 3-inch wafers.

 B

 Child n (Fig. 25 (b)) is shown. The idealization factor n is an index that indicates the degree of deviation of the Schottky barrier height φ force when an ideal Schottky junction is used.

 B

 This corresponds to the case where the Schottky junction is ideal, and the closer the n value is to 1, the better the Schottky property. From Fig. 25, in the HJFET200 obtained by the conventional manufacturing method, φ is lower than that of an ideal Schottky junction, and n is significantly different from 1.

 B

 [0020] From the above examination, since there are crystal defects on the surface in an actual device, the n value deviates from the ideal value n = l, and as a result, the apparent φ is reduced. The

 B

 This causes an increase in gate leakage current during AC operation, which hinders stable operation of the device. In addition, if there is some distribution of crystal defects, the Schottky characteristics will vary accordingly, degrading the reproducibility of the element characteristics. Therefore, in order to improve the stable operation of the device and the reproducibility of the characteristics, the n value should be close to 1 and the crystal state should be made uniform, that is, the crystallinity of the semiconductor surface forming the gate electrode. It is important to control this.

[0021] The present inventor has proceeded to study such viewpoint power, and by providing a surface protective film on the group III nitride semiconductor transistor and improving the cleanliness of the semiconductor surface, the current collab is reduced and the Schottky characteristic is excellent. It was found that a transistor can be realized. Main departure Akira was made based on these new findings.

 [0022] According to the present invention,

 A group III nitride semiconductor layer structure including a heterojunction;

 A source electrode and a drain electrode formed separately on the group III nitride semiconductor layer structure;

 A gate electrode disposed between the source electrode and the drain electrode;

 With

 In the region between the gate electrode and the drain electrode, an insulating film is provided on the group III nitride semiconductor layer structure,

There is provided a field effect transistor characterized in that an impurity concentration in the group VIII nitride semiconductor layer structure at the interface between the insulating film and the group VIII nitride semiconductor layer structure is lE17 atoms Zcm ³ or less.

In the field effect transistor of the present invention, an insulating film provided on a group III nitride semiconductor layer structure having a heterointerface in a region between the gate electrode and the drain electrode, and a group II group nitride semiconductor layer The impurity concentration at the interface with the structure is lE17atom _S Zcm ³ or less. For this reason, in the transistor of the present invention, formation of interface states due to impurities in the group III nitride semiconductor layer structure is suppressed, and current collab is effectively suppressed. In addition, the transistor of the present invention has excellent Schottky characteristics. It is presumed that the crystallinity of the group III nitride semiconductor layer structure is improved as the reason why the Schottky characteristics are excellent by setting the impurity concentration at the interface to 1 E17 atoms / cm ³ or less. In addition, the transistor of the present invention is excellent in operational stability and can be manufactured stably with a high yield.

 In the present invention, the impurity concentration can be measured, for example, by SIMS (secondary ion mass spectrometry).

 In the present invention, from the viewpoint of suppressing current collabs, the insulating film can be, for example, an insulating film containing nitrogen, preferably a SiN film having a nitrogen force with silicon.

 [0026] Further, according to the present invention,

 A method for producing the field effect transistor, comprising:

Forming a group III nitride semiconductor layer structure including a heterojunction in a deposition chamber; Forming the insulating film on the group m nitride semiconductor layer structure; selectively removing a predetermined region of the insulating film by etching to form an opening; and forming the opening on the group m nitride semiconductor layer structure And forming the gate electrode so as to fill the opening,

 A method of manufacturing a field effect transistor is provided.

According to the method of the present invention, the insulating film is formed before the gate electrode is manufactured. In the conventional method, as described above with reference to FIG. 28 in the background art section, the surface protective film is formed after the formation of the gate electrode. In the subsequent manufacturing process, a photoresist is not formed on the surface of the group II II nitride semiconductor layer, and the surface is not affected by plasma. Therefore, according to the manufacturing method of the present invention, it is possible to suppress the oxidation of the nitride semiconductor surface due to change with time. Therefore, a field effect transistor having a clean interface between the insulating film and the m-group nitride semiconductor layer structure can be stably manufactured. Therefore, according to the present invention, it is possible to suppress current collapse due to oxidation of the m-group nitride semiconductor layer. In addition, a field effect transistor with excellent uniformity of the Schottky interface can be stably manufactured. In addition, the crystal state of the surface of the group m nitride semiconductor layer in the region between the gate electrode and the drain electrode can be improved. In addition, the uniformity of the crystalline state can be improved.

 [0028] Further, according to the present invention,

 Forming a group III nitride semiconductor layer structure including a heterojunction in a film forming chamber; forming an insulating film on the group III nitride semiconductor layer structure;

 A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group m nitride semiconductor layer structure so as to embed the opening;

 Including

 A step of forming the insulating film without taking out the film forming chamber force after the step of forming the group m nitride semiconductor layer structure is performed. A manufacturing method is provided.

[0029] Further, according to the present invention, Forming a group III nitride semiconductor layer structure including a heterojunction in a film forming chamber; forming an insulating film on the group III nitride semiconductor layer structure;

 A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group m nitride semiconductor layer structure so as to embed the opening;

 After the step of forming the in-group nitride semiconductor layer structure and before the step of forming the insulating film,

 Cleaning the surface of the group m nitride semiconductor layer structure by wet etching using an acid;

 A method of manufacturing a field effect transistor is provided.

[0030] In the manufacturing method of the present invention, the insulating film is formed in a state where the surface of the group m nitride semiconductor layer structure is clean. In the conventional manufacturing method in which an insulating film is formed on the in-group nitride semiconductor layer structure to suppress current collabs, the insulating film is usually formed after the electrode is formed. The interface order was formed by impurities on the surface of the physical semiconductor layer structure. On the other hand, according to the manufacturing method of the present invention, a field effect transistor having a clean interface can be obtained by devising a process for forming an insulating film on the m-group nitride semiconductor layer structure. . For this reason, the current collaborative effect caused by the oxidation of the interface is suppressed, and a field effect transistor having excellent Schottky characteristics can be stably manufactured.

 In the present invention, after the step of forming the insulating film, a predetermined region of the insulating film is selectively removed by etching to be removed on the group III nitride semiconductor layer structure. Alternatively, the source electrode and the drain electrode may be formed so as to be embedded in the region. At this time, either the step of forming the source electrode and the drain electrode or the step of forming the gate electrode may be performed first.

 As described above, according to the present invention, it is possible to realize a group III nitride semiconductor field effect transistor that is excellent in operational stability and can be manufactured with a high yield.

 Brief Description of Drawings

[0033] The above objects and other objects, features and advantages will The present invention will be further clarified by embodiments and the following drawings attached thereto.

 FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to an example.

 FIG. 2 is a cross-sectional view showing a configuration of a field effect transistor according to an example.

 FIG. 3 is a cross-sectional view showing a configuration of a field effect transistor according to an example.

 FIG. 4 is a cross-sectional view showing a configuration of a field effect transistor according to an example.

 FIG. 5 is a cross-sectional view showing a configuration of a field effect transistor according to an example.

 FIG. 6 is a cross-sectional view showing a configuration of a field effect transistor according to an example.

7] FIG. 7 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG.

8] FIG. 8 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG.

9] FIG. 9 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 10] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 11] A sectional view showing a manufacturing process of the field effect transistor of FIG.

12] A sectional view showing a manufacturing process of the field effect transistor of FIG.

13] A sectional view showing a manufacturing process of the field effect transistor of FIG.

14] A sectional view showing a manufacturing process of the field effect transistor of FIG.

15] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 16] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 17] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 18] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 19] A sectional view showing a manufacturing process of the field effect transistor of FIG.

 20 is a cross-sectional view showing a manufacturing step of the field effect transistor of FIG. 4. FIG.

FIG. 21 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 22] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 23] A sectional view showing a manufacturing process of the field effect transistor of FIG.

FIG. 24] A sectional view showing a manufacturing process of the field effect transistor of FIG.

[25] FIG. 25 is a diagram comparing the method of manufacturing an example and a conventional field effect transistor. [26] FIG. 26 is a diagram for comparing the method of manufacturing an example and a conventional field effect transistor.

FIG. 27 is a cross-sectional view showing a configuration of a field effect transistor according to an example. FIG. 28 is a cross-sectional view showing a configuration of a conventional field effect transistor.

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, an embodiment of the present invention will be described by taking an HJFET having an AlGaN electron supply layer, a ZGaN channel layer, and a surface protective film (hereinafter also simply referred to as “protective film”) as an example of a group III nitride semiconductor structure. Will be described with reference to the drawings. In all the drawings, common constituent elements are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Further, in this specification, the laminated structure is expressed as “upper layer Z lower layer (substrate side) J”.

 FIG. 1 is a diagram showing a basic configuration of the field effect transistor of the present embodiment. This field effect transistor (HJFET100) is separated from the group III nitride semiconductor layer structure (GaN channel layer 112, AlGaN electron supply layer 113) including the heterojunction, and these group III nitride semiconductor layer structures. The source electrode 101 and the drain electrode 103 formed, and the gate electrode 102 disposed between the source electrode 101 and the drain electrode 103 are provided. Since the HJFET 100 has a heterojunction structure, it is possible to use a high-concentration two-dimensional carrier gas generated at the heterojunction with spontaneous polarization and piezoelectric polarization force.

 [0037] The group III nitride semiconductor layer structure includes a channel layer made of InGaN (0≤x≤1) and an electron supply layer made of AlGaN (0≤y≤1), and includes a heterointerface. Is the interface between InGaN and AlGaN. However, in the above formula, l -y so that X and y do not become zero at the same time.

 It is necessary to.

 The HJFET 100 has an insulating film (SiN film 121) as a protective film on the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113 in the region between the gate electrode 102 and the drain electrode 103.

 [0039] Like the SiN film 121, the protective film also has an insulating material strength. The SiN film 121 may be provided on the entire surface of the region between the gate electrode 102 and the drain electrode 103 or may be provided on a part of the region. By adopting a configuration in which the entire region between the gate electrode 102 and the drain electrode 103 is covered with the SiN film 121, the current collab can be more effectively suppressed.

The SiN film 121 is an insulating film containing nitrogen as at least one of the elements constituting the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113. Elements in protective film May move to the interface between the AlGaN electron supply layer 113 and the protective film, there is a concern that a level is formed as an impurity at the interface, but nitrogen in the SiN film 121 is common to N constituting the AlGaN electron supply layer 113 Therefore, it does not become an impurity with respect to the AlGaN electron supply layer 113, and an interface state can be prevented from being formed. For this reason, generation | occurrence | production of current collaboration can be suppressed more effectively. In addition, by using the SiN film 121 as the protective film, it is possible to use the same material as the AlGaN electron supply layer 113.

 [0041] When SiN is grown on the AlGaN epitaxial layer, which is the AlGaN electron supply layer 113, the crystallinity of the underlying layer is reflected in the initial stage of growth depending on the growth conditions so as to lattice match with the underlying AlGaN. So SiN grows so-called epitaxy. At this time, the SiN film 121 is a film including a region grown epitaxially on the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113. By using a film including an epitaxially grown region, the group III nitride semiconductor layer structure and the SiN film 121 can be manufactured in a continuous process. Further, the stability of the film quality of the obtained SiN film 121 can be improved.

 The SiN film 121 is a film that substantially does not contain oxygen as a constituent element. Since oxygen tends to form a level in a group III nitride semiconductor, the generation of current collabs can be more reliably suppressed by employing a structure that does not substantially contain oxygen. Note that “substantially free of oxygen” means that no oxygen is intentionally contained in the film, as long as current Collabs generation due to the formation of impurity levels of oxygen can be suppressed. Unintentionally included oxygen may be present. Moreover, it is preferable that the oxygen concentration is below the detection limit in SIMS.

 [0043] The thickness of the SiN film 121 is, for example, not less than 5 nm and not more than 200 nm, more specifically not less than 5 nm and not more than lOOnm. By setting the thickness to 5 nm or more, current collapse at the interface can be more reliably suppressed. The thickness of the SiN film 121 is, for example, 200 nm or less, preferably 150 nm or less, more preferably lOOnm or less. By doing this, current collaboratives can be suppressed and the gate breakdown voltage can be improved, and the trade-off problem between the two can be solved more effectively.

 Further, the SiN film 121 is a film grown on the surface of the clean AlGaN electron supply layer 113.

HJFET100! /, SiN film 121, GaN channel layer 112 and AlGaN electron supply Impurity concentration force LE17atomsZcm ³ below at the interface between the laminated structure of the layer 113, is favored properly is LE15atomsZcm ³ or less. By doing so, it is possible to suppress the formation of interface states in the AlGaN electron supply layer 113 and to suppress the generation of current collabs. In addition, Schottky characteristics can be improved. In this specification, the impurity concentration is the total concentration of carbon and oxygen contained in the interface. In this embodiment and the following examples, the impurity concentration can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0045] However, it is difficult to obtain the HJFET 100 satisfying the interface impurity concentration by the above-described conventional method. In the present embodiment, the SiN film 121 is used as a surface protective film that effectively suppresses the generation of current collabs, and the SiN film 121 is formed while the surface of the AlGaN electron supply layer 113 is clean. HJFET100 having the above impurity concentration can be obtained. As a method of forming the SiN film 121 while the surface of the AlGaN electron supply layer 113 is clean, for example,

 (i) After forming the AlGaN electron supply layer 113, a method of forming the SiN film 121 in the same deposition chamber without exposing to the atmosphere,

 (ii) a method of forming the SiN film 121 after etching the surface of the AlGaN electron supply layer 113 with an acid or the like,

Is mentioned. When an HJFET was fabricated by these methods, an HJFET having an impurity concentration of lE15 atoms Zcm ³ or less at the interface between the surface of the A1GaN electron supply layer 113 and the SiN film 121 and the gate electrode 102 was obtained by the method (i). In the method (ii), an HJFET having an impurity concentration of lE17 atoms Zcm ³ or less at the interface between the surface of the AlGaN electron supply layer 113 and the SiN film 121 and the gate electrode 102 was obtained. Note that these methods will be described in more detail in Examples described later.

In addition, according to the above method, since the SiN film 121 is formed after the AlGaN electron supply layer 113 is formed and before the electrode is formed, the source electrode 101 and the drain electrode 103 run on the SiN film 121. It has a structure. As a result, the concentration of the electric field at the gate electrode side end of the drain electrode 103 during high-voltage operation is alleviated, and the gate breakdown voltage is improved.

[0047] (Example) Hereinafter, an example of the present invention will be described with reference to the drawings, taking as an example the case where c-plane Sic is used as a growth substrate for a group m nitride semiconductor layer. In all the drawings, common constituent elements are denoted by the same reference numerals, and common description is omitted as appropriate in the following description.

 [0048] (Example 1)

 This example relates to an HJFET having the configuration shown in FIG. In this embodiment, the HJ FET 100 is formed on a substrate 110 such as SiC. A buffer layer 111 having a semiconductor layer force is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an eight-and-one electron supply layer 113 is formed. On the AlGaN electron supply layer 113, the source electrode 101 and the drain electrode 103 are in ohmic contact, and the surface of the AlGaN electron supply layer 113 is covered with the SiN film 121.

 7 to 9 are diagrams showing a method for manufacturing the HJFET 100 of this example.

 This manufacturing method includes the following steps.

 Step 101: A process of forming a III-nitride semiconductor layer structure including a heterojunction (laminated structure of AlGaN electron supply layer 113 and GaN channel layer 112), specifically, an epitaxial growth method on the substrate 110 Sequentially forming a GaN channel layer 112 and an AlGaN electron supply layer 113 by

 Step 103: forming a protective film (SiN film 121) while the surface of the AlGaN electron supply layer 113 is clean,

 Step 105: A predetermined region of the SiN film 121 is selectively removed by etching to form an opening, and the gate is embedded on the stacked structure of the AlGaN electron supply layer 113 and the GaN channel layer 112. Forming electrode 102; and

 Step 107: After the step of forming the SiN film 121, a predetermined region of the SiN film 121 is selectively removed by etching, and the source electrode 101 and the AlGaN electron supply layer 113 are embedded so as to embed the removed region. Forming the drain electrode 103 apart from each other;

Here, the force gate illustrated in the case of the procedure of forming the source electrode 101 and the drain electrode 103 in Step 107 after forming the gate electrode 102 in Step 105. As long as the SiN film 121 is formed before the formation of the first electrode 102, the source electrode 101, and the drain electrode 103, either Step 105 or Step 107 may be performed first. For example, it is possible to decide which step force to perform in consideration of the type of metal used for each electrode.

 [0051] The SiN film 121 in step 103 is formed at least between the formation region of the gate electrode 102 and the formation region of the drain electrode 103.

In this embodiment, after forming the group III nitride semiconductor layer structure by the epitaxial growth method in step 101, the step of subsequently forming the SiN film 121 in a clean atmosphere that is not taken out from the film forming chamber. 103 processes are performed. Specifically, the clean atmosphere is an atmosphere substantially free of oxygen. In this way, eight _&? ^ Do be exposed to the atmosphere the surface of the electron supply layer 113 is on the way, so further effectively an impurity concentration at the interface between the AlGaN electron supply layer 113 and the SiN film 1 21 Thus, the current collab can be more effectively suppressed.

 [0053] Note that, in the present specification, the film formation chamber is composed of a single chamber! Or may include a plurality of small chambers. In the case of using a film formation chamber including a plurality of chambers, after forming one AlGaN electron supply layer 113, the substrate 110 is transferred to another chamber without exposure to the atmosphere by releasing the vacuum, and the SiN film 121 is formed. You may go. Do not expose to the atmosphere by releasing the vacuum! Therefore, surface contamination of the AlGaN electron supply layer 113 can be effectively suppressed.

 Hereinafter, the manufacturing process of the HJFET 100 will be described more specifically.

 First, as shown in FIG. 7 (a), a semiconductor layer is grown on a substrate 110 having SiC force by using an epitaxial growth method, and the buffer layer 111 (thickness of the substrate 110 side force and also undoped A1N force is sequentially formed. 20 nm), an undoped GaN channel layer 112 (thickness 2 μm), and an AlGaN electron supply layer 113 (thickness 25 nm) with undoped Al GaN force are obtained (FIG. 7 (a)). As the epitaxy growth method, for example, a molecular beam epitaxy (MBE) growth method or a metal organic vapor phase epitaxy (MOVPE) growth method is used.

Then, a SiN film 121 (film thickness 60 nm) is formed on the AlGaN electron supply layer 113 (FIG. 7B). At this time, after the AlGaN electron supply layer 113 is formed, it is not exposed to the atmosphere in the same film forming apparatus. A SiN film 121 is formed. The SiN film 121 is formed by the same growth method as the growth method of the AlGaN electron supply layer 113 and the GaN channel layer 112.

 Subsequently, a part of the SiN film 121 is etched away until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively etched away to expose the AlGaN electron supply layer 113 (FIG. 8 (c)).

 [0057] Then, a source electrode 101 and a drain electrode 103 are formed on the AlGaN electron supply layer 113 by evaporating a metal such as TiZAl (FIG. 8 (d)), and annealing is performed at 650 ° C. Thus, the AlGaN electron supply layer 113 is ohmic-bonded.

 [0058] Next, a photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively removed by etching to provide an exposed portion of the AlGaN electron supply layer 113 (FIG. 9 (e)). On the exposed AlGaN electron supply layer 113, a gate metal of, for example, NiZAu is deposited to form a Schottky contact gate electrode 102 (FIG. 9 (f)). With the above procedure, the HJFET 100 shown in Fig. 1 is obtained.

 FIG. 25 and FIG. 26 are diagrams for comparing the manufacturing method of this example with the conventional manufacturing method.

 [0060] First, FIG. 25 (a) and FIG. 25 (b) show 10 3 inches each in the manufacturing method of the HJFET 100 of this embodiment and the manufacturing method of the conventional HJFET 200 (FIG. 28). Shows Schottky barrier height φ and idealization factor n in HJFET obtained in woofer

 B

 FIG.

 [0061] As can be seen from FIGS. 25 (a) and 25 (b), in the HJFET 100 of this example, an excellent Schottky property close to an ideal Schottky junction can be obtained, and the variation between wafers can be improved. It can be seen that cracks are suppressed and the uniformity is improved. This is presumably because the surface force of the AlGaN electron supply layer 113 in the region where the gate electrode 102 is formed is not exposed to the atmosphere or plasma until the gate electrode 102 is formed, and the surface of the AlGaN electron supply layer 113 is not contaminated.

[0062] FIG. 26 is a diagram showing the amount of current collabs when a device is prototyped on each of 10 3-inch wafers in the manufacturing method of this example and the conventional manufacturing method. In the field effect transistor 200 obtained by the conventional manufacturing method shown in FIG. 26, the surface of the AlGaN electron supply layer 213 provided between the gate electrode 202 and the drain electrode 203 undergoes various processes. It is difficult to control the negative charge induced on the surface, and even if a current film is suppressed by forming a protective film by the SiN film 221, there is a variation in the degree of current current reduction.

 In contrast, in the HJFET 100 of this example, it can be seen that the amount of current collapse is small and the variation is small. In this embodiment, after the AlGaN electron supply layer 113 is formed using the same growth apparatus as the semiconductor layer, the SiN film 121 is continuously grown without being exposed to the atmosphere or plasma. Therefore, the SiN film 121 is formed before the gate electrode 102 is formed, and the interface between the semiconductor and the SiN film 121 is formed with a uniform and high-quality interface that is not damaged by the process. From the above, the influence of negative surface charge becomes a big problem, especially as in the present invention! / In the Group III nitride semiconductor device, the current interface is reduced due to this uniform interface formation and low interface impurity concentration. And the effect of improving the uniformity of characteristics is remarkable.

[0065] Further, in the obtained HJFET, when the oxygen concentration in the AlGaN electron supply layer at the interface between the SiN film and the AlGaN electron supply layer was analyzed, in the case of the HJFET 100 of this example, it was 1E15 atoms / cm ³ or less. It was. When the thickness of the SiN film 121 was about 5 to 200 nm, the AlGaN electron supply layer 113 and the SiN film 121 having such an impurity concentration at the interface could be formed.

[0066] On the other hand, as a result of forming the SiN film 221 by the plasma CVD method after forming the electrodes for the HJFET 200 shown in FIG. 28, AlGaN at the interface between the AlGaN electron supply layer 213 and the SiN film 221 is formed. The oxygen concentration in the electron supply layer 213 was about IE 19 atoms Zcm ³ .

[0067] Further, in the manufacturing process of the HJFET 100, when the AlGaN electron supply layer 113 is formed by the epitaxial growth method and then exposed to the atmosphere before the SiN film 121 is formed, the SiN film 121 and the AlGaN electron supply layer 113 are formed. The oxygen concentration in the AlGaN electron supply layer 113 at the interface was about lE19 atoms Zcm ³ .

As described above, in the HJFET 100 of this example, after the AlGaN electron supply layer 113 is formed, the SiN film 121 is formed in the same film formation chamber without being exposed to the atmosphere. Therefore, the HJFET 100 has excellent Schottky properties. In addition, current collabs are suppressed, high output and high reliability Have a configuration. In addition, since the variation between wafers is suppressed, the HJFET 100 has a structure capable of stably manufacturing a structure as designed with a high yield. When an HJFET was fabricated by the method of this example, a transistor having an impurity concentration at the interface between the AlGaN electron supply layer 113 and the SiN film 121, here an oxygen concentration of lE15 atoms Zcm ³ or less, was obtained.

 [0069] In this example, since the SiN film 121 functioning as a protective film contains nitrogen, which is a constituent element of the AlGaN electron supply layer 113, which is a group III nitride semiconductor layer, after the formation of the AlGaN electron supply layer 113, The SiN film 121 can be formed in a continuous process without exposure to the atmosphere. Further, the stability of the film quality of the obtained SiN film 121 can be improved.

 In the present embodiment, the source electrode 101 and the gate electrode 102 have a structure that rides on the SiN film 121 that is a protective film, so that the drain electrode 103 is not damaged during high-voltage operation. Electric field concentration at the gate electrode side end can be alleviated. Therefore, the gate breakdown voltage is improved! /.

 [0071] (Example 2)

 FIG. 2 is a cross-sectional view showing the configuration of the HJFET of this example. The basic configuration of the HJFET 130 shown in FIG. 2 is the same as the HJFET 100 (FIG. 1) of the first embodiment. On the substrate 110, the buffer layer 111, the GaN channel layer 112, the AlGaN electron supply layer 113, and the SiN film 121 are on the substrate 110 side. In this order, the structure is such that the source electrode 101, the drain electrode 103, and the gate electrode 102 are provided on the AlGaN electron supply layer 113, and the cleanliness of the interface between the AlGaN electron supply layer 113 and the SiN film 121 is increased. The method of maintaining is different from Example 1.

 [0072] Such an HJFET 130 is manufactured by the following procedure.

10 to 13 are diagrams showing a method for manufacturing the HJFET in this example. In Example 1, after the step of forming the group III nitride semiconductor layer structure, the SiN film was formed without being exposed to the contaminated atmosphere (for example, air). However, the manufacturing method of this example is based on the group III nitride semiconductor. This is a case where the group III nitride semiconductor layer structure is exposed to a contaminated atmosphere after the step of forming the layer structure. In this embodiment, before the step of forming the SiN film 121 in order to remove impurities that form interface states on the surface of the group III nitride semiconductor layer structure, step 109: wet etching using an acid, Surface of III-nitride semiconductor layer structure Cleaning process,

 Is included.

 [0073] First, for example, molecular beam epitaxy (Molecular Beam) is formed on a substrate 110 made of SiC.

Semiconductors are grown by epitaxy (MBE) growth method or metal organic vapor phase epitaxy (MOVPE) growth method. Thus, in order from the substrate 110 side, an undoped A1N force buffer layer 111 (film thickness 20 nm), an undoped GaN channel layer 112 (film thickness 2 μm), and an undoped AlGaN AlGaN electron supply layer 113 (film) A semiconductor layer structure with a thickness of 25 nm) is obtained (Fig. 10 (a)).

 [0074] Next, when the surface of the AlGaN electron supply layer 113 is contaminated by the air or the like, the surface of the semiconductor layer is cleaned by wet etching on the AlGaN electron supply layer 113 with an acid or the like (FIG. 10 ( b)) SiN film 121 (60 nm) is formed by a plasma CVD method etc. in a clean atmosphere (Fig. ll (c)). Specifically, hydrofluoric acid or hydrochloric acid is used as the acid. For example, etching is performed at room temperature for about 30 seconds to 1 minute, followed by washing with water and drying.

[0075] Even if the AlGaN electron supply layer 113 was exposed to the atmosphere or the like by the cleaning process in Fig. 10 (b), the surface was cleaned, and in the completed HJFET 130, the AlGaN electron supply layer 113 The impurity concentration at the interface between the SiN film 121 and the SiN film 121 can be set to lE17 atoms Zcm ³ or less.

Subsequently, an element isolation mesa (not shown) is formed by etching away a part of the SiN film 121 and a part of the epitaxial layer structure until the GaN channel layer 112 is exposed. Then, a photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively etched away to expose the AlGaN electron supply layer 113 (FIG. 11 (d)). A source electrode 101 and a drain electrode 103 are formed on the electron supply layer 113 by evaporating a metal such as TiZAl (FIG. 12E). Then, annealing is performed at 650 ° C. to form ohmic contact with the AlGaN electron supply layer 113. A photoresist is formed in a predetermined region on the surface of the SiN film 12 1, and the exposed portion of the SiN film 121 is selectively etched away to provide an opening to expose the AlGaN electron supply layer 113 (FIG. 12 (f)) . On the exposed AlGaN electron supply layer 113, a gate metal such as NiZAu is deposited to form a Schottky contact gate electrode 102 (FIG. 13). As a result, the HJFET13 shown in Fig. 2 0 is obtained.

 In this example, before the electrode structure is formed, the semiconductor surface is cleaned by etching with an acid or the like (FIG. 10B). In addition, it can also be terminated so as to suppress subsequent oxidation of the surface by the cleaning treatment with acid. Even if the AlGaN electron supply layer 113 is slightly contaminated after the surface of the AlGaN electron supply layer 113 is etched with acid or the like and before the SiN film 121 is formed, the SiN film is formed by plasma CVD. When the film 121 is formed, contaminants can be removed by plasma irradiation.

 As described above, in this example, since the SiN film 121 is formed on the surface of the AlGaN electron supply layer 113, the influence of the negative surface charge is a serious problem. Current collab in the child is suppressed.

Further, in this example, the portion of the AlGaN electron supply layer 113 that was exposed to the atmosphere before the formation of the gate electrode 102 and was contaminated with the atmosphere was removed by etching. In addition, since the SiN film 121 is formed on the AlGaN electron supply layer 113 when the gate electrode 102 and the drain electrode 103 are formed, the surface of the AlGaN electron supply layer 113 is exposed to plasma at the time of electrode formation. There is nothing to do. Therefore, in the subsequent manufacturing process, a photoresist is formed on the AlGaN electron supply layer 113, and the gate electrode 102 having a nearly ideal Schottky property is obtained without the AlGaN electron supply layer 113 being attacked by plasma. In addition, since the cleaning process is performed, the crystal state of the surface of the AlGaN electron supply layer 113 in the region between the gate electrode 102 and the drain electrode 103 is good and uniform, and the surface state can be stabilized. It is. For this reason, it is possible to obtain a configuration that has excellent Schottky properties and can be stably manufactured at a high yield. When an HJFET was fabricated by the method of this example, a transistor having an impurity concentration at the interface between the AlGaN electron supply layer 113 and the SiN film 121, here an oxygen concentration of lE17 atoms Zcm ³ or less, was obtained.

 [0080] Also in this embodiment, as in the case of Embodiment 1, the source electrode 101 and the gate electrode 102 are structured on the SiN film 121, so that the drain electrode can be used during high-voltage operation. This makes it possible to produce a device with improved gate breakdown voltage due to relaxation of the electric field concentration at the end of the gate electrode.

[Example 3] FIG. 3 is a diagram showing a cross-sectional structure of the HJFET of this example.

 The basic configuration of the HJFET 132 shown in FIG. 3 is the same as that of the HJFET of Example 1 or Example 2, but a protective film is stacked on the first insulating film (SiN film 121) and the SiN film 121. It differs from the second insulating film (SiO film 122) in that the force is configured. Here, SiO film 122 is Si

 twenty two

 Although provided in direct contact with the N film 121, another insulating film may be provided as an intervening layer between the first insulating film and the second insulating film.

More specifically, the HJFET 132 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. A source electrode 101 and a drain electrode 103 are ohmic-bonded on the AlGaN electron supply layer 113, and the surface of the AlGaN electron supply layer 113 is covered with a SiN film 121. Covered with 122.

 2

 14 to 17 are diagrams showing a method for manufacturing the HJFET shown in FIG.

 First, a semiconductor is grown on the substrate 110 having SiC force by, for example, MBE growth method, metal organic vapor phase epitaxy MOVPE growth method, or the like. In this way, in order from the substrate 110 side, the buffer layer 111 (thickness 20 nm) made of undoped A1N, the undoped GaN channel layer 112 (thickness 2 μm), and the AlGaN electron supply layer 113 made of undoped AlGaN ( A semiconductor layer structure with a thickness of 25 nm) is obtained (Fig. 14 (a)).

 Next, as in Example 1, a SiN film 121 (60 nm) is subsequently formed on the AlGaN electron supply layer 113 by plasma CVD or the like without exposure to the atmosphere (FIG. 14 (b)). When the A IGaN electron supply layer 113 is exposed to the atmosphere, etching is performed with an acid or the like to clean the surface of the semiconductor layer, and the SiN film 121 is formed as in the second embodiment.

 Then, a SiO film 122 (100 nm) is formed on the SiN film 121 by an atmospheric pressure CVD method or the like (see FIG.

 2

15 (c)) ₀

 [0086] After that, a part of the SiN film 121 and the SiO film 122 and a part of the epitaxial layer structure were removed by Ga.

 2

 An element isolation mesa (not shown) is formed by etching until the N channel layer 112 is exposed. Then, a photoresist is formed in a predetermined region on the surface of the SiO film 122,

 2

The predetermined regions of the SiN film 121 and the SiO film 122 are exposed until the AlGaN electron supply layer 113 is exposed. Then, the source electrode 101 and the drain electrode 103 are formed on the AlGaN electron supply layer 113 by evaporating, for example, Ti ZA1 metal (FIG. 16 (e)). An ohmic bond is formed by annealing at 650 ° C.

[0087] Subsequently, a photoresist is formed in a predetermined region on the surface of the SiO film 122, and the SiN film 121 is formed.

 2

 And by selectively etching away a predetermined region of the SiO film 122, AlGaN

2

 An exposed opening of the electron supply layer 113 is provided (FIG. 16 (f)). On the exposed AlGaN electron supply layer 113, for example, a NiZAu gate metal is deposited to form a Schottky-junction gate electrode 102 (FIG. 17). As a result, the HJFET 132 shown in FIG. 3 is obtained.

 [0088] In this embodiment, however, do not expose to the atmosphere before forming the electrode structure! Or use a method of cleaning the surface of the AlGa N electron supply layer 113 with an acid or the like. Thus, the interface between the AlGaN electron supply layer 113 and the SiN film 121 is kept clean. For this reason, the same effect as in Example 1 or Example 2 can be obtained.

 Furthermore, in this example, since the SiN film 121 formed on the surface of the group III nitride semiconductor layer is covered with the SiO 2 film 122, the deterioration with time of the SiN film 121 is further reliably suppressed.

2

 can do. Therefore, the lifetime of element characteristics can be extended.

Note that the SiO film 122 may be formed using the same film forming apparatus as the SiN film 121, or may be different.

 2

 The film forming apparatus may be used. The planar shape of the SiO film 122 is the same as that of the SiN film 121.

 2

 The same or different configurations may be used. In addition, a field plate portion 105 may be formed in a region between the gate electrode 102 and the drain electrode 103 via a SiN film 121 above the AlGaN electron supply layer 113. This configuration will be described later in Example 4 and Example 5.

[0091] (Example 4)

 FIG. 4 is a cross-sectional view showing the configuration of the HJFET of this example.

 The basic configuration of the HJFET 134 shown in FIG. 4 is the same as that of the HJFET 100 of Example 1, except that the gate electrode 102 protrudes in a bowl shape on the drain electrode 103 side and is formed on the SiN film 121. Is different from HJFET100.

[0092] The HJFET 134 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. On this buffer layer 111, a GaN channel layer 112 Is formed. On the GaN channel layer 112, an eight-and-a-half electron supply layer 113 is formed. On the eight &? ^ Electron supply layer 113, the source electrode 101 and the drain electrode 103 are joined in ohmic contact. A gate electrode 102 is provided between these electrodes. The gate electrode 102 has a field plate portion 105 and is joined to the eight &? ^ Electron supply layer 113 in a Siykey key junction. The surface of the AlGaN electron supply layer 113 is covered with the SiN film 121.

 [0093] The length of the field plate portion 105 in the gate length direction is, for example, 0.3 µm or more, preferably 0. 0 or more. In this way, current collab can be more reliably suppressed. The field plate portion 105 is configured so as not to overlap the drain electrode 103, and preferably the length of the field plate portion 105 in the gate length direction is 70% or less of the distance between the gate electrode and the drain electrode. The greater the length of the extension of the field plate portion 105, the greater the effect of suppressing current collabs. The withstand voltage decreases. Note that the distance between the gate electrode 102 and the drain electrode 103 refers to the length from the drain electrode side end of the gate electrode 102 to the gate electrode side end of the drain electrode 103.

 18 to 20 are views showing a method for manufacturing the HJFET of FIG.

 First, a semiconductor is grown on a substrate 110 made of SiC by, for example, MBE growth method or MOCVD growth method. In this way, the buffer 110 side force in the order of the substrate 110 is also an undoped A1N buffer layer 111 (film thickness 20 nm), an undoped GaN channel layer 112 (film thickness 2 μm), and an undoped AlGaN force AlGaN electron supply layer 113 (film thickness) A semiconductor layer structure in which 25 nm) is stacked is obtained (Fig. 18 (a)).

 Next, similarly to Example 1, a SiN film 121 (60 nm) is subsequently formed on the AlGaN electron supply layer 113 by plasma CVD or the like without exposure to the atmosphere (FIG. 18B). When the A IGaN electron supply layer 113 is exposed to the atmosphere, etching is performed with an acid or the like to clean the surface of the semiconductor layer, and the SiN film 121 is formed as in the second embodiment.

Subsequently, part of the SiN film 121 and part of the epitaxial layer structure are etched away until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region of the SiN film 121, and the exposed portion of the SiN film 121 is removed. Etching is selectively removed until the AlGaN electron supply layer 113 is exposed (FIG. 19 (c)). A metal such as TiZAl is deposited on the exposed AlGaN electron supply layer 113 to form the source electrode 101 and the drain electrode 103 (Fig. 19 (d)), and annealing is performed at 650 ° C. The electrode and the AlGaN electron supply layer 113 are joined in ohmic contact. A photoresist is formed in a predetermined region of the SiN film 121, and an exposed portion of the SiN film 121 is selectively removed by etching to provide an opening to expose the AlGaN electron supply layer 113 (FIG. 20 (e)).

Then, for example, NiZAu is vapor-deposited on the exposed AlGaN electron supply layer 113 as a metal film to be the gate electrode 102 to form the Schottky contact gate electrode 102 (FIG. 20 (f)) ₀ or At the same time, a field plate portion 105 made of NiZAu is formed integrally with the gate electrode 102. As a result, the HJFET 134 shown in FIG. 4 is obtained.

 Note that although an example in which the gate electrode 102 and the field plate portion 105 are formed at the same time has been described in this embodiment, these may be performed in separate steps. It is also possible to form a resist having an opening at a predetermined position on the SiN film 121 and form the field plate portion 105 so as to fill the opening. In this case, the gap between the gate electrode 102 and the field plate portion 105 can be formed with a narrower gap.

 [0099] In this embodiment, however, exposure to the atmosphere is not performed before the formation of the electrode structure! / Alternatively, a method of cleaning the surface of the AlGa N electron supply layer 113 with an acid or the like should be employed. Thus, the interface between the AlGaN electron supply layer 113 and the SiN film 121 is kept clean. For this reason, the same effect as in Example 1 or Example 2 can be obtained.

Further, the HJFET 134 has a field plate portion 105. Therefore, even when a high reverse voltage is applied between the gate electrode 102 and the drain electrode 103, the electric field force applied to the drain electrode side end of the gate electrode 102 is mitigated by the action of the field plate portion 105. . Therefore, the electric field concentration at the drain electrode side end of the gate electrode 102 can be further reliably suppressed, and the gate breakdown voltage can be improved. Furthermore, since the surface potential can be modulated by the field plate portion 105 during a large signal operation, the response speed of the surface trap can be increased and the current collab can be suppressed. Therefore, according to the present invention, the balance of current collabs, gate breakdown voltage, and gain can be remarkably improved. In addition, even if the surface condition fluctuates due to variations in the manufacturing process, such good performance should be realized stably. Can do.

 [0101] In the above description, the force electric field control unit described as an example in which the same member member as the gate electrode 102 is configured and the field plate unit 105 functioning as an electric field control unit is provided is the gate electrode In the region between the gate electrode 102 and the drain electrode 103, the electric field is independent of the gate electrode 102 via the SiN film 121 above the group III nitride semiconductor layer structure in the region between the gate electrode 102 and the drain electrode 103. A configuration in which a control electrode is provided may be employed.

 FIG. 27 is a cross-sectional view showing the configuration of such an HJFET. In FIG. 27, instead of the gate electrode 102 having the field plate portion 105, a gate electrode 102 and an electric field control electrode 106 provided apart from the gate electrode 102 are provided.

 Note that the electric field control electrode 106 may be formed at the same time as the gate electrode 102 or may be formed in a separate process. In another process, a resist having an opening at a predetermined position is formed on the SiN film 121, and the electric field control electrode 106 can be formed so as to fill the opening. In this case, the gap between the gate electrode 102 and the electric field control electrode 106 can be formed with a narrower gap.

 [0104] In FIG. 27, the electric field control electrode 106 may apply different potentials to the electric field control electrode 106 and the gate electrode 102, which may be independently controllable to the gate electrode 102. it can. With such a structure, the field effect transistor can be driven under optimum conditions. Since the surface trap response can be suppressed by fixing the surface potential, the electric field control electrode 106 is set to the same potential as the gate electrode 102, and the current collab can be suppressed more effectively than when the surface potential is modulated. . In particular, the effect of being able to control the electric field control electrode 106 independently is remarkable in the group III nitride semiconductor device in which the influence of the negative surface charge is a serious problem.

 [0105] Further, when the electric potential of the electric field control electrode 106 is fixed as described above, the gate capacitance hardly changes even if the electric potential of the gate electrode 102 is changed, so that a decrease in gain can be significantly suppressed. I'll do it.

 [0106] (Example 5)

In the HJFET 134 of Example 4 having the field plate part 105, further implementation As in Example 3, the insulating film may have a laminated structure. FIG. 5 is a cross-sectional view showing the configuration of the HJFET of this example.

 The HJFET 136 shown in FIG. 5 is formed on a substrate 110 such as SiC.

 A buffer layer 111 having a semiconductor layer force is formed on the substrate 110. A GaN channel layer 112 force S is formed on the noffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. On this AlGaN electron supply layer 113, the source electrode 101 and the drain electrode 103 are ohmic-bonded. A gate electrode 102 is provided between these electrodes. The gate electrode 102 has a field plate portion 105 and is in Schottky junction with the AIGaN electron supply layer 113. The surface of the AlGaN electron supply layer 113 is covered with a SiN film 121, and a SiO film 122 is further provided thereon. F

 2

 The field plate portion 105 is provided on the SiO film 122 and the field plate portion 105.

 2

 The SiN film 121 and the SiO film 122 are provided immediately below.

 2

 21 to 24 are diagrams showing a method for manufacturing the HJFET 136. FIG.

 First, a semiconductor is grown on a substrate 110 made of SiC by, for example, MBE growth method or MOVPE growth method. In this way, the substrate 110 side force also has an undoped A1N force buffer layer 111 (film thickness 20 nm), an undoped GaN channel layer 112 (film thickness 2 m), and an undoped AlGaN force AlGaN electron supply layer 113 (film) A semiconductor layer structure with a thickness of 25 nm) is obtained (Fig. 21 (a)).

 Next, after the AlGaN electron supply layer 113 is formed, an SiN film 121 (60 nm) is formed on the AlGaN electron supply layer 113 without exposing it to the atmosphere by plasma CVD or the like (FIG. 21 (b )). When the AlGaN electron supply layer 113 is exposed to the atmosphere, the SiN film 121 is formed after etching with an acid or the like to clean the surface of the semiconductor layer.

 [0110] Subsequently, an SiO film 122 (10011111) is formed on the SiN film 121 by atmospheric pressure CVD or the like (

 2

 Figure 22 (c)).

 [0111] Then, a part of the SiN film 121 and the SiO film 122 and a part of the epitaxial layer structure are made Ga.

 2

 An element isolation mesa (not shown) is formed by etching until the N channel layer 112 is exposed. Then, a photoresist is formed in a predetermined region on the surface of the SiO film 122.

 2

AlGaN electron supply layer 113 is exposed in a predetermined region of SiN film 121 and SiO film 122 Until the source electrode 101 and the drain electrode 103 are formed by depositing a metal such as TiZAl on the AlGaN electron supply layer 113 (FIG. 23 (e)). ))) Annealing is performed at 650 ° C., and these electrodes and the AlGaN child supply layer 113 are joined in ohmic contact.

[0112] Next, a photoresist is formed in a predetermined region on the surface of the SiO film 122, and the SiN film 121 is formed.

 2

 And by selectively etching away a predetermined region of the SiO film 122, AlGa

 2

 An exposed opening of the N electron supply layer 113 is provided (FIG. 23 (f)).

 Next, on the exposed AlGaN electron supply layer 113, for example, NiZAu is vapor-deposited as a metal film to be the gate electrode 102 to form the gate electrode 102 that is Schottky-bonded to the AlGaN electron supply layer 113 ( (Figure 24). At the same time, a field plate portion 105 made of NiZAu is also formed. In this way, the HJFET 136 shown in FIG. 5 is obtained.

 [0114] In this embodiment, an example in which the gate electrode 102 and the field plate portion 105 are formed at the same time has been shown. The step of forming may be performed separately). In this case, the gap between the gate electrode 102 and the field plate portion 105 can be formed with a narrower gap.

 According to the present embodiment, in addition to the effects of the fourth embodiment, the following effects can be obtained. That is, in the HJFET 136, the SiN film 121 and the SiO film 122 are directly under the field plate portion 105.

 2 A protective film consisting of a laminated film is provided. Compared to the configuration in which the protective film is only the SiN film 121, the field plate portion 105 can

 2

 Increase in parasitic capacitance can be suppressed. In particular, the SiN film 121 is formed thin enough not to change the film quality over time (150 nm or less, more preferably lOOnm or less), and the SiO film 122 is thickly laminated, thereby further suppressing the increase in capacitance. It is possible

2

 The

 [0116] In this embodiment, the gate electrode 102 having the field plate portion 105 may be replaced with the gate electrode 102 and the electric field control electrode 106 provided apart from the gate electrode 102. .

[0117] The electric field control electrode 106 may be formed simultaneously with the gate electrode 102 or may be formed in a separate process. In a separate process, a resist with an opening at a predetermined position is removed from SiN. The electric field control electrode 106 may be formed on the film 121 so as to fill the opening. In this case, the gap between the gate electrode 102 and the electric field control electrode 106 can be formed with a narrower gap.

 [0118] In this example, the SiN film 121 formed on the surface of the group III nitride semiconductor layer is formed of SiO.sub.

 2 Since the structure is covered with the film 122, the deterioration with time of the SiN film 121 can be further reliably suppressed. Therefore, as in Example 3, the lifetime of the element characteristics can be extended.

Also in this example, as in Example 3, the structure is such that the source electrode 101 and the gate electrode 102 ride on the SiN film 121 and the SiO film 122. For this reason,

 2

 During the pressure operation, the electric field concentration at the gate side end of the drain electrode 103 can be relaxed, and the gate breakdown voltage can be improved.

[0120] In this example, the surface protective film has an SiO film 122 as an upper layer.

 2

 From the viewpoint of improving gain and reliability, it is more preferable to use a low dielectric constant film having a relative dielectric constant of 4 or less. Such low dielectric constant materials include SiOC (sometimes called SiOCH), BCB (benzocyclobutene), FSG (Flouro Silicate Glass: SiOF), HS (Hydrogen— ¾ilisesquioxane ^ MS (Methyl— ¾iisesquioxane) ^ machine polymer, or The material which made these porous is illustrated.

 [0121] Even when the protective film, more specifically, the insulating film that forms the upper layer of the surface protective film contains C (carbon) as a constituent element, the interface between the AlGaN electron supply layer 113 and the SiN film 121 is formed. The effects described above can be obtained by cleaning.

 [0122] (Example 6)

 This embodiment is an example of an HJFET that employs a wide recess structure.

FIG. 6 is a cross-sectional view showing the configuration of the HJFET of this example. In the HJFET 138 shown in FIG. 6, the contact layer composed of an undoped AlGaN layer is provided between the source electrode 101 and the AlGaN electron supply layer 113 and between the drain electrode 103 and the AlGaN electron supply layer 113. 114 intervenes. In the HJFET 138, a contact layer 114 is provided on the AlGaN electron supply layer 113 in the formation region of the source electrode 101 and the drain electrode 103. The contact layer 114 has an opening, and the AlGaN electron supply layer 113 is exposed from the opening. The bottom surface of the opening is a recess surface with respect to the upper surface of the contact layer 114. Con A source electrode 101 and a drain electrode 103 are provided in contact with the upper surface of the tact layer 114. A gate electrode 102 is provided in contact with the exposed portion of the AlGaN electron supply layer 113. The bottom force of the source electrode 101 and the drain electrode 103 is located above the bottom surface of the gate electrode 102 (on the side away from the substrate 110).

 [0123] The HJFET 138 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an eight-and-a-half electron supply layer 113 is formed. A contact layer 114 is formed on the AlGaN electron supply layer 113. The source electrode 101 and the drain electrode 103 are ohmic-bonded to the surface of the contact layer 114. The surface of the AlGaN electron supply layer 113 is covered with a SiN film 121! /.

 The HJFET 138 in FIG. 6 has a configuration in which a contact layer 114 is added to the HJFET 100 (FIG. 1) of the first embodiment. With this configuration, in addition to the effects described in the first embodiment, there is an effect of further reducing the contact resistance.

 [0125] Further, by adopting the wide recess structure, the electric field distribution at the end of the gate electrode 102 on the drain electrode side changes, so that an even better electric field relaxation effect can be obtained.

 [0126] Furthermore, in this example, as in Example 1, Example 2, and Example 4, the source electrode 101 and the gate electrode 102 are on the SiN film 121, so that the high voltage operation is possible. In this case, the electric field concentration at the gate electrode side end of the drain electrode 103 can be relaxed to improve the gate breakdown voltage.

 [0127] In this example, the protective film provided on the AlGaN electron supply layer 113 is a single layer. However, as in the case of Example 3 and Example 4 described above, two insulating films are provided. A layer structure can be formed, or the field plate portion 105 can be formed. For example, the field plate portion 105 has a two-layer structure composed of a SiN film 121 and a SiO film 122 as a protective film.

 2

 The rate part 105 may be provided on the SiO film 122. In this case as well, the same as in Example 3.

 2

 Thus, the SiO film 122 is preferably an insulating film having a lower dielectric constant than the SiN film 121.

 2

That's right. As such an insulating film, for example, when the first insulating film is SiN, a film containing no nitrogen can be used. In this way, it is possible to effectively suppress the change over time in the film quality of the insulating film in the region below the field plate portion 105 and the increase in capacitance. it can. Therefore, the reliability and high frequency characteristics of the HJFET 138 can be further improved. Further, the field plate portion 105 may extend to the top of the contact layer 114. By doing so, the electric field concentration at the drain side end of the gate electrode 102 can be more effectively dispersed and relaxed. If a recess structure is used, a multi-stage recess can be used.

In this embodiment, a gate recess structure in which a part of the drain electrode 103 is embedded in the AlGaN electron supply layer 113 can also be adopted.

Further, in the above description, the force has been described by taking the case where the contact layer 114 is composed of an undoped AlGaN layer as an example. In this embodiment, the contact layer 114 may be doped with a predetermined impurity. .

[0130] The present invention has been described based on the embodiments and examples. It is understood by those skilled in the art that these embodiments are exemplifications, and that various modifications are possible for each component and combination of each processing process, and that such modifications are also within the scope of the present invention. This is where it is.

 [0131] For example, in the above embodiment, the force described in the case where SiC is used as the material of the substrate 110, as well as other dissimilar substrate materials such as sapphire, and Group III nitride semiconductors such as GaN and AlGaN. A substrate or the like may be used.

 [0132] In the above embodiment, the case where the SiN film is provided as an insulating protective film containing at least one of the elements constituting the group-III nitride semiconductor layer structure has been described as an example. The material of the insulating film containing at least one of the elements constituting the nitride semiconductor layer structure is not limited to SiN, and other examples include nitrides such as BN. Even when such a film is used, the generation of current collabs can be suppressed.

 [0133] Further, the structure of the semiconductor layer below the gate electrode 102 is not limited to that illustrated, and various modes are possible. For example, a structure in which the AlGaN electron supply layer 113 is also provided in the lower part of the GaN channel layer 112 is also possible.

[0134] Further, an intermediate layer and a cap layer may be appropriately provided in this semiconductor layer structure. For example, a group II nitride semiconductor layer structure includes a channel layer made of InGaN (0≤x≤1), an electron supply layer with AlGaN (0≤y≤1) force, and a cap layer with GaN force. Laminate in order It can be set as the structure which has another structure. In this way, the effective Schottky height can be increased and a higher gate breakdown voltage can be realized. However, in the above formula, the case where x = y = 0 is excluded.

 In each of the above embodiments, a so-called gate recess structure in which a part of the lower portion of the gate electrode 102 is embedded in the AlGaN electron supply layer 113 can be employed. As a result, an excellent gate breakdown voltage can be obtained.

 Further, in each of the above embodiments, the distance between the gate electrode 102 and the drain electrode 103 can be made longer than that between the gate electrode 102 and the source electrode 101. This is a so-called offset structure, and the electric field concentration at the end on the drain electrode side of the gate electrode 102 can be more effectively dispersed and relaxed.

Claims

The scope of the claims  [1] Group m nitride semiconductor layer structure including heterojunction,  A source electrode and a drain electrode formed separately on the in-group nitride semiconductor layer structure;  A gate electrode disposed between the source electrode and the drain electrode;  With  In the region between the gate electrode and the drain electrode, an insulating film is provided on the in-group nitride semiconductor layer structure, A field effect transistor, wherein an impurity concentration in the in-group nitride semiconductor layer structure at the interface between the insulating film and the in-group nitride semiconductor layer structure is lE17 atoms Zcm ³ or less. [2] In the field effect transistor according to claim 1,  A field effect transistor, wherein the insulating film is an insulating film containing at least one of elements constituting the group III nitride semiconductor layer structure. [3] The field effect transistor according to claim 2,  A field effect transistor, wherein the element constituting the group III nitride semiconductor layer structure is nitrogen.  [4] The field effect transistor according to any one of claims 1 to 3,  The field effect transistor, wherein the insulating film is a film that substantially does not contain oxygen as a constituent element. [5] The field effect transistor according to any one of claims 1 to 4,  An electric field control electrode is provided on the region between the gate electrode and the drain electrode above the group III nitride semiconductor layer structure via the insulating film. Effect transistor. [6] The field effect transistor according to claim 5,  The field effect transistor, wherein the field control electrode can be controlled independently of the gate electrode. 7. The field effect transistor according to claim 1, wherein the gate electrode is used. A field-effect transistor comprising a field plate portion that extends in a bowl shape on the drain electrode side and is formed on the insulating film.  [8] The field effect transistor according to any one of claims 1 to 7,  A field effect transistor, wherein the insulating film has a thickness of 5 nm to lOO nm.  [9] The field effect transistor according to any one of claims 1 to 8,  2. The field effect transistor according to claim 1, wherein the first insulating film and a second insulating film laminated on the first insulating film are also configured with force. [10] The field effect transistor according to any one of claims 1 to 9,  A field effect transistor, wherein a contact layer is interposed between the source electrode and the group III nitride semiconductor layer structure and between the drain electrode and the group III nitride semiconductor layer structure. [11] The field effect transistor according to claim 10,  A field effect transistor, wherein the contact layer comprises an undoped AlGaN layer. 12. The field effect transistor according to claim 1, wherein an impurity concentration in the group III nitride semiconductor layer structure at an interface between the insulating film and the group III nitride semiconductor layer structure is lE15atomsZcm ^3. A field-effect transistor characterized by:  [13] The method of manufacturing a field effect transistor according to any one of claims 1 to 12, wherein the group III nitride semiconductor layer structure including a heterojunction is formed in a film formation chamber; Forming the insulating film on the physical semiconductor layer structure;  A step of selectively removing a predetermined region of the insulating film by etching to form an opening; and forming the gate electrode so as to embed the opening on the group III nitride semiconductor layer structure;  A method of manufacturing a field effect transistor comprising: [14] forming a group III nitride semiconductor layer structure including a heterojunction in the deposition chamber; Forming an insulating film on the group III nitride semiconductor layer structure; A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode so as to embed the opening on the group III nitride semiconductor layer structure;  Including  A step of forming the insulating film without taking out the film forming chamber force after the step of forming the group m nitride semiconductor layer structure is performed. Production method. [15] forming a group m nitride semiconductor layer structure including a heterojunction in the deposition chamber;  Forming an insulating film on the in-group nitride semiconductor layer structure;  A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group m nitride semiconductor layer structure so as to embed the opening;  After the step of forming the in-group nitride semiconductor layer structure and before the step of forming the insulating film,  Cleaning the surface of the group m nitride semiconductor layer structure by wet etching using an acid;  A method of manufacturing a field effect transistor comprising: [16] In the method of manufacturing a field effect transistor according to any one of claims 13 to 15, after the step of forming the insulating film, a predetermined region of the insulating film is selectively removed by etching, and the in A method for manufacturing a field effect transistor, comprising: forming a source electrode and a drain electrode separately on a group nitride semiconductor layer structure so as to embed a removed region.