WO2007000838A1 - Semiconductor device having lifetime control region - Google Patents

Abstract

In a semiconductor device having an insulated gate structure in which a channel is formed along the sidewall of a trench formed in a semiconductor substrate, a lifetime control region having a shorter carrier lifetime than the other regions is formed between the sidewalls of adjacent trenches. The lifetime control region is typically formed in a first semiconductor region between the opposing trenches, and is formed so as to have a shorter carrier lifetime than the remaining part of the first semiconductor region and the other semiconductor regions.

Description

 Specification

 Semiconductor device having lifetime control region

 Technical field

 The present invention relates to a semiconductor device such as an insulated gate field effect transistor in which a channel portion is formed on a sidewall of a trench structure.

 This application claims priority based on Japanese Patent Application No. 2005-190048 filed on June 29, 2005, the contents of which are incorporated herein by reference.

 Background art

 An insulated gate field effect transistor having a gate structure in which a conductive film having a polysilicon equivalent force is embedded in a trench having a gate insulating film formed on a side wall, that is, a so-called trench gate is described in Patent Document 1, for example. ing.

 As shown in FIG. 5, the insulated gate field effect transistor described in Patent Document 1 includes a high-concentration substrate 301, a low-concentration epitaxial growth layer 302 formed on the high-concentration substrate 301, and a low-concentration substrate. A semiconductor substrate 300 having a source diffusion region 304 and a channel diffusion region (base region) 306 formed in the epitaxial growth layer 302, and a source electrode 307 and a gate electrode formed on one main surface of the semiconductor substrate 300 308 and a drain electrode 309 formed on the other main surface of the semiconductor substrate 300.

 [0003] Trenches (grooves) 310 and 311 are provided on one main surface of the semiconductor substrate, and a silicon oxide film 313 that functions as a gate insulating film is formed on the sidewalls of the trenches 310 and 311. Yes. In addition, a conductor film (gate electrode) 312 made of, for example, polycrystalline silicon (polysilicon) is buried in the trenches 310 and 311 to form a trench gate. When a potential higher than the threshold voltage is applied to the gate electrode, the base region extends from the source diffusion region 304 toward the low-concentration epitaxial growth layer 302 along the sidewalls of the trenches 310 and 311, that is, along the gate insulating film 313. In 306, a channel extending in the longitudinal direction is generated. As a result, carriers (electrons) are injected from the source diffusion region 304 to the low-concentration epitaxial growth layer 302 through the channel, and a current flows in the vertical direction of the device.

Patent Document 1: Japanese Patent Laid-Open No. 11 177086 Disclosure of the invention

 Problems to be solved by the invention

 By the way, this type of semiconductor device is sometimes used as a diode element by utilizing a PN junction formed at the interface between the base region and the low-concentration epitaxial growth layer. FIG. 6 shows an equivalent circuit of the field effect transistor (MOSF ET400) of FIG.

 As shown in the figure, a PN junction diode 401 having an anode on the source electrode side and a force sword on the drain electrode side is integrally formed with the MOSFET 400 between the source electrode and the drain electrode.

 Here, in order to shorten the recovery time (reverse recovery time) of the diode 401 incorporated in the MOSFET 400, lifetime control such as electron beam irradiation or heavy metal diffusion may be performed. However, simply applying electron beam irradiation or heavy metal diffusion to the entire surface of the semiconductor substrate can reduce the liquefier time. On-resistance, that is, the operating resistance during device (MOSFET) operation is increased. There is a problem with [].

 Such a problem also occurs in a known insulated gate bipolar transistor (IGBT) or the like in which the high concentration substrate 301 is replaced with a semiconductor substrate of opposite conductivity type.

[0006] The present invention has been made in view of such circumstances, and can reduce the liqueory time (reverse recovery time) of the built-in diode without increasing the operating resistance during device operation. An object is to provide a semiconductor device.

 Means for solving the problem

In order to achieve the above object, the present invention provides a semiconductor device having an insulated gate structure in which a channel is formed along a side wall of a trench formed on a semiconductor substrate, and between the side walls of adjacent trenches. Provided is a semiconductor device characterized in that a lifetime control region is formed in which the lifetime of carriers is made smaller than the lifetime of carriers in other regions.

The present invention also includes first and second trenches formed on a semiconductor substrate including a first semiconductor region of a first conductivity type so as to face each other with the first semiconductor region interposed therebetween, A gate insulating film formed on side surfaces of the first and second trenches; A gate electrode formed inside the first and second trenches;

 A second semiconductor region of a second conductivity type formed between the first trench and the second trench and formed in contact with the first semiconductor region;

 A third semiconductor region of the first conductivity type that contacts the second semiconductor region, and the first semiconductor region between the first trench and the second trench facing each other. There is provided a semiconductor device characterized in that a lifetime control region in which the lifetime of a carrier is controlled is formed in the region.

[0009] Preferably, the carrier lifetime in the lifetime control region is the carrier lifetime in the first semiconductor region except for the lifetime control region, and in the second semiconductor region. The lifetime of the carrier and the lifetime of the carrier in the third semiconductor region are smaller than the deviation.

As a typical example, a PN junction diode is formed by the first semiconductor region and the second semiconductor region.

As another typical example, the lifetime control region is formed closer to the side of the third semiconductor region than the bottom surfaces of the first and second trenches.

As a preferred example, the lifetime control region is a region formed by implanting light ions, a region formed by irradiating an electron beam, or a region formed by diffusing heavy metal. .

 The invention's effect

 [0013] According to the present invention, in a semiconductor device having an insulated gate structure in which a channel is formed along the side wall of a trench formed on a semiconductor substrate, the lifetime of carriers is different between the side walls of adjacent trenches. Since a lifetime control region that is smaller than the carrier lifetime in the region is formed, the liqueory time (reverse recovery time) can be shortened without increasing the operating resistance during device operation.

 Brief Description of Drawings

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention.

 FIG. 2 is an explanatory view showing a state during element operation of the semiconductor device according to the embodiment of the present invention.

FIG. 3 shows a state when a diode built in the semiconductor device according to the embodiment of the invention operates Explanatory drawing which shows a state.

 FIG. 4 is a diagram showing a cross-sectional structure of a semiconductor device according to another embodiment of the present invention.

 FIG. 5 shows a cross-sectional structure of a semiconductor device having a conventional trench gate structure.

 6 is a circuit diagram showing an equivalent circuit of the conventional semiconductor device shown in FIG.

 Explanation of symbols

 [0015] 1 ... Semiconductor device, 100 ... Semiconductor substrate, 101 ... High-concentration substrate, 102 ... Low-concentration epitaxial growth layer, 103, 104 ... Trench, 105 ... Silicon oxide film, 106 ... Conductor film 107 ··· Base region 108 ··· Source diffusion region 110… Lifetime control region

 BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

 FIG. 1 shows a configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device shown in FIG. 1 is an insulated gate field effect transistor.

 A semiconductor device 1 according to an embodiment of the present invention is a semiconductor device having an insulated gate structure in which a channel is formed along a sidewall of a trench formed on a semiconductor substrate, and includes a carrier between sidewalls of adjacent trenches. This is characterized by the formation of a lifetime control region in which the lifetime of the carrier is smaller than the lifetime of carriers in other regions. The lifetime control region 110 formed by irradiating light ions is formed in the low concentration epitaxial growth layer 102 located between the base region 107 and the bottoms of the trenches 103 and 104, and is characterized in that ! /

In FIG. 1, a semiconductor device (insulated gate field effect transistor) according to an embodiment of the present invention includes a high-concentration substrate (for example, an n + -type semiconductor substrate) 101 and a low-concentration substrate 101 formed on the high-concentration substrate 101. Concentrated epitaxial growth layer (for example, n_ type epitaxial growth layer) 102, source diffusion region (for example, n + type diffusion region) 108 formed in low concentration epitaxial growth layer 102, and source diffusion region 108 are in contact with each other As described above, the semiconductor substrate 100 having the electrode layer 109 and the channel diffusion region, that is, the base region (for example, the p-type diffusion region) 107 formed on the upper surface, and one main surface of the semiconductor substrate 100 are formed. Source electrode 111 and gate electrode 112, and a drain electrode 113 formed on the other main surface of the semiconductor substrate 100. [0018] Similar to the conventional semiconductor device shown in FIG. 5, trenches 103 and 104 are provided on one main surface of the semiconductor substrate 100, and a gate insulating film is formed on the sidewalls of the trenches 103 and 104. A functional silicon oxide film 105 is formed.

 Inside the trenches 103 and 104, a conductor film (gate electrode) 106 made of, for example, polycrystalline silicon (polysilicon) is embedded to form a trench gate.

 [0019] As shown in the figure, the conductor film 106 includes an upper region of the low-concentration epitaxial growth layer 102, a channel diffusion region, that is, a base region 107, and a source diffusion region 108 through a silicon oxide film 105. In contact with the side of

 The lifetime control region 110 is formed in the upper region of the low-concentration epitaxial growth layer 102 facing the conductor film (gate electrode) 106, and is formed so as to cross between the adjacent trenches 103 and 104. .

 Here, the lifetime control region 110 refers to the carrier's carrier by irradiating light ions locally, irradiating electron beams locally, or diffusing heavy metals (lifetime killer) locally. An area where the lifetime is reduced compared to the lifetime of the carrier in other areas. In this embodiment, the lifetime control region 110 is formed by locally irradiating (introducing) light ions. The semiconductor substrate 100 is the semiconductor substrate of the present invention, the low-concentration epitaxial growth layer 102 is the first semiconductor region of the first conductivity type (ι type) of the present invention, and the conductor film (gate electrode) 106 is the present invention. The base region (for example, ρ-type diffusion region) 10 7 is the second conductivity type (ρ-type) second semiconductor region of the present invention, and the source diffusion region 108 is the first electrode of the present invention. It corresponds to a third semiconductor region of conductivity type (η + type).

 In the present embodiment, the upper surface of lifetime control region 110 is positioned on the other main surface side of semiconductor substrate 100 with respect to the lower surface of base region 107, and the upper surface of lifetime control region 110 and the base region The upper region of the low-concentration epitaxial growth layer 102 remains thinly between the lower surface of 107.

The lower surface of the lifetime control region 110 is located between the bottom surface of the trenches 103 and 104 and one main surface of the semiconductor substrate 100, and is an extension line between the lower surface of the lifetime control region 110 and the bottom surfaces of the trenches 103 and 104. The upper region of the low-concentration epitaxial growth layer 102 (that is, the region sandwiched between the trenches 103 and 104) remains thin. Note that the limetime control region 110 may be formed in the entire low concentration epitaxial growth layer 102 between the trenches 103 and 104.

However, the lifetime control region 110 is formed as a crystal defect region formed by light ion implantation. For this reason, the interface between the upper surface of the lifetime control region 110 and the low-concentration epitaxial growth layer 102 thereon is not clearly determined. Similarly, the interface between the lower surface of the lifetime control region 110 and the low-concentration epitaxial growth layer 102 under the lifetime control region 110 is not clearly determined. Therefore, for the sake of convenience, in this specification, the surface where the density of crystal defects on the interface side (recombination center density) is 1Z3 of the recombination center density on the center side of the lifetime control region 110 is referred to as the lifetime control region. The upper and lower surfaces are the same.

 In this way, by forming the lifetime control region 110 between the opposing trenches 103 and 104, while maintaining a relatively low on-resistance (operation resistance during device operation), the built-in diode Rikanoku Lee time (reverse recovery time) can be shortened.

 In other words, in the conventional semiconductor device having a trench gate structure shown in FIG. 5, when lifetime control is performed by irradiating light ions, the force-on resistance that decreases the lyano-leak time increases. However, in the transistor of this embodiment, the on-resistance remains relatively small. The reason for this is as follows.

 [0023] When the transistor is operating (on), the operating current (electron current) flows through the channel as shown in FIG. It is formed in the epitaxial growth layer 102 and the channel diffusion region (that is, the base region 107). For this reason, the electron current flows across only a part of the lifetime control region 110, and the total capture amount of electrons in the lifetime control region 110 is relatively small because the electron capture cross section is small. For this reason, the on-resistance is kept relatively low.

On the other hand, when the built-in diode is operated, that is, when a voltage for increasing the potential on the source electrode 111 side is applied between the source electrode 111 and the drain electrode 113, as shown in FIG. Electron current flows across the entire surface of the PN junction, in other words, across the entire lifetime control region 110. For this reason, the total amount of carriers captured in the lifetime control region 110 where the capture cross sections of electrons and holes are large is relatively large. For this reason, Ricano Time (Reverse recovery time) can be shortened.

 As a result, the light ion dose in the lifetime control region 110, in other words, the crystal defect density

 By controlling the amount of (recombination center density), a desired liqueury time can be obtained.

 In other words, if the light ion irradiation dose is increased to increase the recombination center density of the carriers, the diode liquefaction time can be made relatively short. On the other hand, if the amount of light ion irradiation is reduced to reduce the recombination center density of carriers, the diode recombination time can be made relatively long. As described above, even if the diode recovery time is controlled in this way (even if the recovery time is relatively short), the forward voltage of the transistor remains relatively low.

[0026] Note that the shape of the trench when viewed from one main surface of the semiconductor substrate 100 can be appropriately selected from various known shapes. For example, a lattice shape, a stripe shape, or an island shape can be used.

 Further, in order to obtain a low forward voltage satisfactorily, the force that positions the lower surface of the lifetime control region 110 on the extension line of the bottom surface of the trenches 103 and 104 or the trenches 103 and 104 as in the present embodiment. It is desirable to locate it between the extension line of the bottom surface and one main surface of the semiconductor substrate.

 However, depending on the required forward voltage, the lower surface of the lifetime control region 110 may be placed on the other main surface (lower surface) of the semiconductor substrate 100 rather than on the extended line of the bottom surfaces of the trenches 103 and 104. It ’s easy to put it in

 However, even in this case, the lifetime control region 110 force S is formed on the other main surface (lower surface) side of the semiconductor substrate 100 rather than on the extension line of the bottom surface of the trenches 103 and 104 so that the effect of the present invention can be obtained. When the lifetime control region 110 is formed closer to the main surface (upper surface) of one side of the semiconductor substrate 110 than the extended line of the bottom surface of the trenches 103 and 104 It is better to make it smaller than the total amount of recombination centers in the lifetime control region 110 (preferably 1Z3 or less).

Next, FIG. 4 shows a configuration of a semiconductor device according to another embodiment of the present invention. In this embodiment, the present invention is applied to an IGBT (Insulated Gate Bipolar Transistor). Deba The structure of the chair is different from the structure of the semiconductor device in FIG. 1 in that the second conductive material is formed on the lower surface side of the semiconductor substrate 200 instead of the high concentration substrate (n + type semiconductor substrate) 101 in FIG. Type (p + type) semiconductor regions 201A and first conductivity type (n + type) semiconductor regions 201B are alternately formed, and an IGBT is formed above the two second conductivity type (p + type) semiconductor regions 201A. This is because a diode is formed above the first conductivity type (n + type) semiconductor region 201B, and the other configurations are the same.

 In FIG. 4, in the semiconductor device (IGBT) according to the present embodiment, the second conductivity type (p + type) semiconductor region 201A and the first conductivity type (n + type) are formed on the lower surface side of the semiconductor substrate 200. The semiconductor regions 201B are alternately formed so that one semiconductor region 201B is sandwiched between the two semiconductor regions 201A, and a low-concentration epitaxial growth layer (for example, an n_-type epitaxial growth layer) is formed on these upper surfaces. ) 202 is formed. Further, an emitter diffusion region (for example, n + type diffusion region) 208 and a channel diffusion region, that is, a base region (for example, p type diffusion region) 207 are formed in the low concentration epitaxial growth layer 202. .

 As in the conventional semiconductor device shown in FIG. 5, trenches 203 and 204 are provided on one main surface of semiconductor substrate 200, and gate insulating films are formed on the sidewalls of trenches 203 and 204. A functional silicon oxide film 205 is formed.

 Inside the trenches 203 and 204, a conductor film (gate electrode) 206 made of, for example, polycrystalline silicon (polysilicon) is embedded to form a trench gate.

 [0031] As shown in the figure, the conductor film 206 includes an upper region of the low-concentration epitaxial growth layer 202, a channel diffusion region, that is, a base region 207, and an emitter diffusion region via a silicon oxide film 205. In contact with the side of 208.

 The lifetime control region 210 is formed in an upper region of the low-concentration epitaxial growth layer 202 facing the conductor film (gate electrode) 206, and is formed so as to cross between the adjacent trenches 203 and 204. .

Here, the lifetime control region 210 is the same as the lifetime control region 110 described above, such as local irradiation with light ions, local irradiation with electron beams, or local heavy metal (life). Time killer) An area where the carrier's lifetime has been reduced compared to the carrier's lifetime in other areas, such as by spreading. In this embodiment, locally light The lifetime control region 210 was formed by irradiating (introducing) ON.

In the present embodiment, as in the embodiments shown in FIGS. 1 to 3, the upper surface of the lifetime control region 210 is closer to the other main surface side of the semiconductor substrate 200 than the lower surface of the base region 207. The upper region of the low-concentration epitaxial growth layer 202 (that is, the region sandwiched between the trenches 203 and 204) remains thinly between the upper surface of the lifetime control region 210 and the lower surface of the base region 207. ing.

 The lower surface of the lifetime control region 210 is located between the bottom surface of the trenches 203 and 204 and one main surface of the semiconductor substrate 200, and is an extension line between the lower surface of the lifetime control region 210 and the bottom surface of the trenches 203 and 204. In between, the upper region of the low concentration epitaxial growth layer 202 remains thin.

 In the case of this embodiment, the same effect as that of the embodiment shown in FIGS. 1 to 3 can be obtained. Industrial applicability

In a semiconductor device having an insulated gate structure, a lifetime control region in which the lifetime of carriers is made smaller than the lifetime of carriers in other regions is formed between sidewalls of adjacent trenches. The recovery time (reverse recovery time) without increasing the operating resistance during operation can be shortened.

Claims

The scope of the claims  [1] In a semiconductor device having an insulating gate structure in which a channel is formed along a sidewall of a trench formed on a semiconductor substrate,  A semiconductor device, characterized in that a lifetime control region in which a carrier lifetime is made smaller than a carrier lifetime in another region is formed between side walls of adjacent trenches.  [2] First and second trenches formed on a semiconductor substrate including a first semiconductor region of a first conductivity type so as to face each other through the first semiconductor region;  A gate insulating film formed on side surfaces of the first and second trenches;  A gate electrode formed inside the first and second trenches;  A second semiconductor region of a second conductivity type formed between the first trench and the second trench and formed in contact with the first semiconductor region;  A third semiconductor region of the first conductivity type that contacts the second semiconductor region, and the first semiconductor region between the first trench and the second trench facing each other. A semiconductor device characterized in that a lifetime control region in which the lifetime of a carrier is controlled is formed in the region. [3] The carrier lifetime in the lifetime control region includes the carrier lifetime in the first semiconductor region except for the lifetime control region and the carrier lifetime in the second semiconductor region. 3. The semiconductor device according to claim 2, wherein the semiconductor device is smaller than both a time and a carrier life time in the third semiconductor region. 4. The semiconductor device according to claim 2, wherein a PN junction diode is formed by the first semiconductor region and the second semiconductor region. [5] The semiconductor device according to [2], wherein the lifetime control region is formed closer to the third semiconductor region than the bottom surfaces of the first and second trenches. .  6. The semiconductor device according to claim 1, wherein the lifetime control region is a region formed by implanting light ions. [7] The lifetime control region is a region formed by irradiating an electron beam. The semiconductor device according to claim 1 or 2.  3. The semiconductor device according to claim 1, wherein the lifetime control region is a region formed by diffusing heavy metal.