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WO2007043010A1 - Memoire non volatile a retention de donnees amelioree - Google Patents

Memoire non volatile a retention de donnees amelioree Download PDF

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Publication number
WO2007043010A1
WO2007043010A1 PCT/IB2006/053724 IB2006053724W WO2007043010A1 WO 2007043010 A1 WO2007043010 A1 WO 2007043010A1 IB 2006053724 W IB2006053724 W IB 2006053724W WO 2007043010 A1 WO2007043010 A1 WO 2007043010A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
memory device
insulating layer
volatile memory
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2006/053724
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English (en)
Inventor
Robertus T. F. Van Schaijk
Nader Akil
Michiel Slotboom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
NXP BV
Original Assignee
NXP BV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV, Koninklijke Philips Electronics NV filed Critical NXP BV
Priority to JP2008535168A priority Critical patent/JP2009512211A/ja
Priority to EP06809563A priority patent/EP1946384A1/fr
Publication of WO2007043010A1 publication Critical patent/WO2007043010A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Definitions

  • Non- volatile memory device with improved data retention
  • the present invention relates to a non-volatile memory device. Moreover, the present invention relates to a method of manufacturing such a non-volatile memory device. Also, the present invention relates to a semiconductor device comprising at least one such non- volatile memory device.
  • a charge storing layer stack that consists of a charge trapping layer which is located between a first or bottom layer and a second or top insulating layer.
  • a charge storage layer stack comprises a bottom silicon dioxide layer, a charge trapping silicon nitride layer and a top silicon dioxide layer, also known as an ONO stack.
  • Semiconductor memory devices based on such an ONO stack as the charge storage layer are often referred to as SONOS (Semiconductor Oxide-Nitride-Oxide Semiconductor) memory devices.
  • charge can be stored in the silicon nitride layer by a mechanism of direct tunneling of electrons (Fowler-Nordheim) through the bottom silicon dioxide layer (tunnel-oxide layer) from the current carrying channel to the silicon nitride layer.
  • the charge trapping properties of the silicon nitride layer allow for downscaling the thickness of the tunnel-oxide layer, which may result in lower program/erase voltages.
  • nMOS SONOS memory devices (based on an n-type channel) suffer from read disturb and low quality of data retention.
  • Read disturb is closely linked to the so-called erase saturation effect. Erasure of charge (electrons) in the charge trapping layer is done by tunneling of holes through the bottom insulating layer and recombination of the tunneled holes with the electrons in the charge trapping layer. Due to the erase saturation effect, a parasitic electron current from the top insulating layer is generated, and relatively large currents flow through the bottom and top insulating layer, which can cause the bottom and top insulating layers to deteriorate. Over the lifetime of the memory device, erase actions create defects (so-called deep traps) that accumulate in the insulating layers.
  • the level of the threshold voltage which defines the memory state, or bit value, of the memory device (being either '0' or ' 1 ', depending on the actual voltage of the memory device being below or above the threshold voltage), tends to increase gradually over the lifetime of the device.
  • the erase- induced change of the threshold voltage has an harmful effect on read actions of the memory device.
  • SONOS memories Another issue with SONOS memories concerns the quality of data retention. To retain charge in the charge storage layer, the energy barrier of the insulating layer should be sufficiently high to retain charge in the charge trapping layer for longer periods.
  • the thickness of the bottom layer is strongly restricted to about 2 nm for reasons of usable program/erase actions. Due to the small thickness of the bottom insulating layer, retention of charge is not optimal. Thus, to improve said retention, it would be desirable, during the design phase, to define a relatively thicker bottom silicon dioxide layer, but the charge transport to/from the charge trapping layer should still rely on the mechanism of direct tunneling.
  • the present invention relates to a non- volatile memory device on a semiconductor substrate, comprising a semiconductor base layer and at least a programmable memory transistor, the programmable memory transistor comprising a charge storage layer stack and a control gate; the semiconductor base layer comprising source and drain regions and a current carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current carrying channel region through the first insulating layer, wherein the first insulating layer comprises a high-K material which has a relatively smaller energy level difference between a barrier height for electrons and a barrier height for holes in comparison to the
  • the present invention allows the use of a relatively thicker bottom insulating layer, which improves the capability of retention of charge in the charge trapping layer.
  • the capability of erasing the charge stored in the charge trapping layer by the mechanism of holes tunneling through the thicker bottom insulating layer may be maintained, since the energy level of the barrier height for tunneling of holes is reduced. This allows the use of a lower read voltage, and hence a reduction of the read disturb effect.
  • the present invention relates to a method of manufacturing a non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer and at least a programmable memory transistor as described above, wherein the method comprises: depositing as the first insulating layer (9) a high-K material which has a relatively improved symmetry of a barrier height for electrons and a barrier height for holes in comparison to the barrier heights for electrons and holes in silicon dioxide.
  • the present invention relates to a memory array comprising at least one non- volatile memory device as described above.
  • the present invention relates to a semiconductor device comprising at least one non- volatile memory device as described above
  • Figure 1 shows schematically an embodiment of a non- volatile memory device which comprises a charge storage layer stack
  • Figure 2 schematically shows an energy barrier diagram for a SONOS memory device of the prior art
  • Figure 3 schematically shows an energy barrier diagram for a SONOS memory device of the present invention
  • Figure 4 shows a normalized threshold voltage window as a function of retention time
  • Figure 5 shows the endurance of an enhancement-type transistor SONOS memory device.
  • Figure 1 shows schematically an embodiment of a non- volatile memory device which comprises a charge storage layer stack.
  • the embodiment of the non- volatile memory device is a planar two -transistor structure 1 on a semiconductor substrate 2.
  • the transistor structure 1 comprises an access transistor Tl and a programmable memory transistor T2
  • the access transistor Tl comprises a first source/drain region 3a, a second source/drain region 3b, an access gate AG 4 and spacers 5.
  • the access gate AG 4 is defined to overlap a channel region Cl between the first and second source/drain regions 3a, 3b.
  • the spacers 5 are defined to cover the sidewalls of the access gate material 4. It is noted that in relation to the present invention, the access transistor, its detailed features, and its configuration with respect to the programmable memory transistor T2 are shown only as a non-limiting example, are not relevant to the present invention and will not be described further.
  • the programmable memory transistor T2 comprises a control gate CG, the second source/drain region 3b and a third source/drain region 3c.
  • the control gate CG is defined to overlap a second channel region C2 between the second source/drain region 3b and the third source/drain region 3c.
  • the control gate CG comprises a charge storage layer stack CT and a gate material 6. Further, the control gate CG may comprise a contact layer 7 on top of the gate material 6. Spacers 8 cover the sidewalls of the control gate CG.
  • the gate material 6 may, for example, be (doped) poly-Si.
  • the contact layer 7 may, for example, be (doped) poly-Si, a suicide compound or a metal.
  • the charge storage layer stack CT comprises a bottom insulating layer 9, a charge trapping layer 10 and a top insulating layer 11.
  • the charge storage layer CT comprises a silicon dioxide layer as bottom insulating layer 9, a silicon nitride layer as charge trapping layer 10 and a silicon dioxide layer as top insulating layer 11, also known as ONO stack.
  • ONO stack semiconductor memory devices based on such an ONO stack are known as SONOS non- volatile memory devices.
  • Figure 2 schematically shows an energy barrier diagram for a SONOS memory device of the prior art.
  • the position of the second channel region C2 and each layer 9, 10, 11 in the charge storage layer stack CT is indicated as a vertical bar.
  • an energy level is schematically depicted.
  • a conduction band level bl and a valence band level b2 are shown.
  • the height of each bar indicates the relative energy level of the corresponding layer in the stack 9, 10, 11, the width of each bar indicates the thickness of the respective layer.
  • the upward arrow indicates the barrier height for electrons (relative to bl), the downward arrow indicates the barrier height for holes (relative to b2).
  • the barrier height is about 3.1 eV.
  • the barrier height is between 4 and 5 eV, typically about 4.8 eV. Since the top insulating layer also comprises a silicon dioxide layer 11, the barrier height is basically the same as for the bottom silicon dioxide layer 9.
  • the energy level of the (silicon nitride) charge trapping layer 10 is to be somewhat lower than the energy level of the bottom insulating layer 9 and top insulating layer 11, respectively, to avoid (spontaneous) leakage from the charge trapping layer 11.
  • the thickness of the bottom silicon dioxide layer 9 is a compromise between the programming and erasure performance by electrons and holes, respectively, with a non-optimal charge retention.
  • An improvement of the reliability of the SONOS memory device of the prior art i.e. a better retention
  • the bottom silicon dioxide layer 9 typically has a thickness of 2.0 nm.
  • the oxide thickness For improvement of the data retention an increase of the oxide thickness to 3.0 nm would be desirable.
  • this would relatively strongly affect erase actions by tunneling of holes, while programming by tunneling of electrons would only be slightly affected due to the asymmetry of the barrier height levels for electrons and holes.
  • Figure 3 schematically shows an energy barrier diagram for a SONOS memory device of the present invention.
  • At least the bottom silicon dioxide layer is replaced by high-K materials, which will be described below in more detail.
  • the high-K materials for at least the bottom layer are selected to have a relatively improved symmetry of the barrier height for electrons and for holes in comparison to the barrier heights for electrons and holes in silicon dioxide, or, in other words, they are selected to obtain a barrier height for electron tunneling and a barrier height for hole tunneling which differ less than the barrier heights for electrons and holes in silicon dioxide, say about 30% or less.
  • the improved barrier height symmetry data retention is advantageously improved by allowing a relative increase of the thickness of the bottom high-K layer, while at the same time erasure of charge remains possible due to the relatively lower barrier height for holes.
  • the high-K material of choice may not exhibit a barrier height for electrons that is too low in order to avoid leakage of charge from the charge trapping layer 11.
  • high-K materials may be selected to have a relatively wide composition range, which would allow a variation and/or tuning of the relevant (e.g., physical, chemical, or electronic) properties of the high-K material as a function of the composition.
  • the bottom insulating layer 9 of the charge storage layer stack contains Hafnium silicate.
  • the Hafnium silicate compound may have either a stoichiometric (HfSiO 4 ) or a non- stoichiometric composition (denoted as: HfSiO). For reason of clarity, in the following both compositions will be denoted by the stoichiometric compound.
  • the magnitude of the barrier height for electrons or holes of this HfSiO compound can be varied and tuned by the silicon content of the HfSiO compound.
  • the high-K material is nitrided Hafnium silicate HfSiO 4 (N), which, through decoration of defects in the high-K material by nitrogen, may provide an improved quality (i.e., physical/chemical stability) of the bottom insulating layer 9.
  • the nitridation of the HfSiO 4 layer advantageously reduces the barrier height for hole tunneling even further and brings it closer to the barrier height level for electron tunneling, making the barrier heights for electrons and holes even more symmetric.
  • the nitrided Hafnium silicate compound may have either a stoichiometric or a non- stoichiometric composition. Below, both compositions will be denoted by the stoichiometric compound.
  • the barrier height for electrons in Hf ⁇ x Si x O 2 is between about 2.5 and about 3.1 eV
  • the barrier height for holes is between about 3.0 and about 3.6 eV.
  • Hf ⁇ x Si x O 2 denotes a stoichiometric compound with variable Si content; in the present invention this compound with variable Si content may also be non- stoichio metric).
  • the barrier height for electrons With a lower Si content of the (nitrided) Hafnium silicate compound, the barrier height for electrons will become lower, and the barrier height for holes will become higher.
  • the K-value of this Hf ⁇ x Si x O 2 layer (with a silicon content of x ⁇ 0.77) will be about K ⁇ 6. (Silicon dioxide: K ⁇ 4.) It is noted that to ensure that, during use, the electrical potential is localized mainly across the bottom (nitrided) Hafnium silicate insulating layer, the top insulating layer 11 may have a similar or larger K-value.
  • the top insulating layer 11 may consist of a high-K material with a larger K-value than the K-value of the bottom insulating layer 9.
  • the top high-K material is Hf ⁇ x Si x O 2 with a Si content of x ⁇ 0.47.
  • the K-value of this compound is about K ⁇ 12.
  • the top high-K material may be nitrided.
  • a SONOS memory device comprising a charge storage layer stack with high-K insulating layers may comprise a bottom Hfi_ x Si x ⁇ 2 (N) layer 9, with the silicon content between x ⁇ 0.60 and x ⁇ 0.90 and a thickness between about 2 and about 6 nm, and a charge trapping silicon nitride layer 10 with a thickness of about 4 to about 10 nm.
  • the top insulating layer 11 may be a Hfi_ x Si x ⁇ 2 (N) layer with the same or a higher K-value and a larger thickness than the bottom high-K layer.
  • the larger VT window can be used to increase the thickness of the bottom insulating Hfi_ x Si x O 2 (N) layer and improve the retention of the charge trapping layer.
  • Figure 4 shows a normalized threshold voltage window as a function of retention time.
  • a SONOS memory device with a 2.2 nm silicon dioxide bottom layer 9 is compared with a SONOS memory device with a 4.0 nm (nitrided) Hfo. 2 3Sio. 77 0 4 .
  • the retention time is plotted.
  • the normalized voltage threshold window ⁇ VT is plotted.
  • the VT window is normalized with respect to the initial VT window value.
  • ⁇ VT is plotted as a dashed curve.
  • ⁇ VT for the Hafnium Silicate based SONOS memory device is plotted as a solid curve.
  • the extrapolation for both curves to a retention time of 10 years is plotted as a dash-dotted line.
  • ⁇ VT decreases gradually for each type of SONOS memory device.
  • the extrapolated retention towards ten years gives a resulting window of 45% for a silicon dioxide layer 9 and 75% for a Hfo. 2 3Sio.77 ⁇ 2 layer 9.
  • Figure 5 shows the endurance of an enhancement-type transistor SONOS memory device.
  • FIG 5 an endurance measurement for a SONOS memory device with a 4.0 nm Hfo. 2 3Sio.77 ⁇ 2 bottom dielectric layer 9 is shown.
  • the SONOS memory device is an enhancement-type transistor, i.e., at a gate voltage of zero Volt, the drain current of the device is nil; the device is in an off-state.
  • the threshold voltage for programming Vtp and the threshold voltage for erasure Vte are depicted as a function of the number of program/erase cycles PE.
  • the magnitude of the programming voltage Vp is 12V for 0.5 ms.
  • the magnitude of the erasure voltage Ve is -13V for 0.5 ms.
  • the threshold voltage for programming Vtp is ⁇ 5V and the threshold voltage for erasure Vte is -2.5V, which requires the use of a high read voltage of about 3.5V.
  • a boosting circuit may be applied to obtain the read voltage of about 3.5V. Particularly for low power applications, this would be a disadvantage.
  • the threshold voltage for programming Vtp and the threshold voltage for erasure Vte gradually increase with the number of program/erase cycles, due to the described erase saturation effect.
  • the VT window changes gradually from about 2.5V to about 1.8V (-72%).
  • an enhancement-type SONOS memory device with a 4.0 nm Hfo.23Sio.77O2 bottom insulating layer 9 shows a significantly improved retention.
  • the read disturb (erase saturation) although improved, may remain an issue.
  • both the threshold voltage for programming Vtp and the threshold voltage for erasure Vte are lower in a depletion type transistor, thus the upper and lower boundaries of the VT window would each shift to a lower value.
  • the read voltage can be reduced significantly.
  • the read voltage can be zero Volt.
  • a read voltage of about IV could be used, which would cause virtually no read disturb.
  • no boosting circuitry would be needed to generate this voltage in devices of the 65 nm generation and smaller.
  • omitting boosting circuitry may enhance energy saving in such applications significantly.
  • the application of a high-K bottom dielectric layer 9 would result in a lower mobility of carriers due to a less complete passivation of interface traps between the bottom dielectric layer 9 and the semiconductor channel region C2.
  • a depletion- type SONOS memory device comprises a buried channel region C2, in which scattering of carriers on interface states at the interface of the bottom dielectric 9 and the semiconductor substrate 2 is strongly reduced.
  • the mobility of a depletion type SONOS memory device may be increased in comparison to the mobility of an enhancement-type SONOS memory device.
  • depletion-type SONOS memory devices it may be observed that the maximum transconductance is higher than for the enhancement-type device due to a higher mobility in the depletion-type SONOS memory device.
  • the SONOS memory device according to the present invention may be embodied by a programmable memory transistor T2 which is created as a depletion-type transistor.
  • the charge storage layer stack CT may be manufactured by way of the following method, which is to be regarded as a non- limiting example of manufacturing such a non- volatile memory device.
  • a semiconductor substrate 2 is provided. On the semiconductor substrate 2 active areas (comprising C2) are defined. Note that the characteristics of the active regions C2 and the substrate 2 are such that the programmable memory transistor T2 may be a depletion-type transistor.
  • the deposition technique may be, for example, MOCVD (metal-organic chemical vapor deposition) or ALD (atomic layer deposition).
  • MOCVD metal-organic chemical vapor deposition
  • ALD atomic layer deposition
  • the composition of the Hfi_ x Si x 0 2 (N) is controllable to allow a silicon content x between about 0.6 and about 0.9.
  • the thickness may be between about 2 and about 6 nm.
  • an annealing step may be carried out while at the same time nitrogen is provided to the high-K layer Hfi_ x Si x 0 2 to form a nitrided high-K layer Hfi_ x Si x 0 2 (N).
  • Nitrogen can be supplied by any conceivable precursor (for example, by supply of NH3).
  • the annealing temperature may be between about 600 and about 900 °C.
  • the charge trapping layer 10 which typically comprises silicon nitride, is deposited by any suitable method known in the art, for example by a CVD process or a PVD process.
  • the thickness of the charge trapping layer 10 is between about 4 and about 10 nm.
  • another charge trapping layer material may be applied here, e.g. a layer of silicon nano-crystals or a high-K material layer.
  • the top insulating layer 11 is deposited.
  • This top layer 11 consists of a further high-K material, for example also HfU x Si x O 2 (N).
  • the thickness is at least equal to, or larger than, the thickness of the bottom high-K layer 9, depending on the K- value of the top dielectric layer 11 in comparison to the K- value of the bottom high-K dielectric layer 9.
  • HfU x Si x O 2 (N) the layer is deposited in a similar fashion as the bottom HfU x Si x O 2 (N) dielectric layer 9.
  • control gate materials 6 is deposited by a method known in the art.
  • the control gate material 6 may comprise an intermetallic compound like a metal-silicide comprising for example Titanium, Tantalum or Cobalt as a metal, or a metal compound such as TiN or TaN.
  • a blanket metal layer may be provided as contact layer 7.
  • the blanket layers are patterned by suitable lithographic processing to form the bodies of the programmable memory transistor T2. Additionally, spacers 8 are formed on the sidewalls of the body of the programmable memory transistor T2.
  • source/drain regions may be formed, and during back-end processing, a passivation layer may be deposited to cover the transistor structure 1 , contacts to source/drain regions and to access and control gates may be created, and interconnect wiring may be provided by some metallisation process(es).

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention porte sur une mémoire non volatile d'un substrat semi-conducteur comprenant une base, et un transistor à mémoire programmable comprenant un paquet de mémoires, une grille de commande, des régions source et drain et un canal entre la source et le drain. Le paquet de mémoires comprend une première couche isolante (9), une couche de piégeage (10) et une seconde couche isolante (11). La première couche est positionnée au-dessus du canal, la couche de piégeage au-dessus de la première couche et la seconde couche au-dessus de la couche de piégeage. Ensuite, la grille de commande est disposée au-dessus du paquet de mémoires. Le paquet de mémoires est disposé de façon à piéger une charge dans la couche de piégeage par pénétration par effet tunnel des supports de charge depuis le canal par la première couche qui comprend un matériau de haute qualité. Ce matériau de haute qualité a une différence relativement plus petite entre l'énergie de hauteur de barrière des électrons et l'énergie de hauteur de barrière des trous en comparaison avec la différence entre les énergies de hauteur de barrière des électrons et des trous dans le dioxyde de silicium.
PCT/IB2006/053724 2005-10-14 2006-10-10 Memoire non volatile a retention de donnees amelioree Ceased WO2007043010A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008535168A JP2009512211A (ja) 2005-10-14 2006-10-10 改良されたデータ保持能力を有する不揮発性メモリデバイス
EP06809563A EP1946384A1 (fr) 2005-10-14 2006-10-10 Memoire non volatile a retention de donnees amelioree

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05109588 2005-10-14
EP05109588.3 2005-10-14

Publications (1)

Publication Number Publication Date
WO2007043010A1 true WO2007043010A1 (fr) 2007-04-19

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PCT/IB2006/053724 Ceased WO2007043010A1 (fr) 2005-10-14 2006-10-10 Memoire non volatile a retention de donnees amelioree

Country Status (5)

Country Link
EP (1) EP1946384A1 (fr)
JP (1) JP2009512211A (fr)
CN (1) CN101288181A (fr)
TW (1) TW200735360A (fr)
WO (1) WO2007043010A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102169891A (zh) * 2011-01-12 2011-08-31 北京大学 一种基于多能级杂质改变半导体掺杂特性的半导体存储器
CN102543214A (zh) * 2010-12-17 2012-07-04 上海华虹Nec电子有限公司 Sonos存储器工艺中在线监控ono膜质量的方法
US8994096B2 (en) 2008-10-23 2015-03-31 Nxp B.V. Multi-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor

Citations (1)

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US20030047755A1 (en) * 2001-06-28 2003-03-13 Chang-Hyun Lee Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers and methods

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US20030047755A1 (en) * 2001-06-28 2003-03-13 Chang-Hyun Lee Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers and methods

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SAITOH ET AL.: "1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-node MISFETs", JAPANESE JOURNAL OF APPLIED PHYSICS, PART 1 (REGULAR PAPERS, SHORT NOTES & REVIEW PAPERS) JAPAN SOC. APPL. PHYS JAPAN, vol. 44, no. 4B, 21 April 2005 (2005-04-21), pages 2330 - 2335, XP002369789, ISSN: 0021-4922 *
WANG X ET AL: "A NOVEL MONOS-TYPE NOVOLATILE MEMORY USING HIGH-KAPPA DIELECTRICS FOR IMPROVED DATA RETENTION AND PROGRAMMING SPEED", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 51, no. 4, April 2004 (2004-04-01), pages 597 - 602, XP001190300, ISSN: 0018-9383 *
WILK G D ET AL: "Hafnium and zirconium silicates for advanced gate dielectrics", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 87, no. 1, 1 January 2000 (2000-01-01), pages 484 - 492, XP012049027, ISSN: 0021-8979 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994096B2 (en) 2008-10-23 2015-03-31 Nxp B.V. Multi-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor
CN102543214A (zh) * 2010-12-17 2012-07-04 上海华虹Nec电子有限公司 Sonos存储器工艺中在线监控ono膜质量的方法
CN102169891A (zh) * 2011-01-12 2011-08-31 北京大学 一种基于多能级杂质改变半导体掺杂特性的半导体存储器

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EP1946384A1 (fr) 2008-07-23
CN101288181A (zh) 2008-10-15
JP2009512211A (ja) 2009-03-19
TW200735360A (en) 2007-09-16

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