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WO2006123580A1 - Dispositif semi-conducteur a base de nitrure et son procede de fabrication - Google Patents

Dispositif semi-conducteur a base de nitrure et son procede de fabrication Download PDF

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Publication number
WO2006123580A1
WO2006123580A1 PCT/JP2006/309550 JP2006309550W WO2006123580A1 WO 2006123580 A1 WO2006123580 A1 WO 2006123580A1 JP 2006309550 W JP2006309550 W JP 2006309550W WO 2006123580 A1 WO2006123580 A1 WO 2006123580A1
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Prior art keywords
back surface
semiconductor substrate
region
nitride semiconductor
semiconductor device
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English (en)
Japanese (ja)
Inventor
Yoshiaki Hasegawa
Akihiko Ishibashi
Toshiya Yokogawa
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to US11/570,147 priority Critical patent/US7606276B2/en
Priority to JP2006536906A priority patent/JP4842827B2/ja
Publication of WO2006123580A1 publication Critical patent/WO2006123580A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04254—Electrodes, e.g. characterised by the structure characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0207—Substrates having a special shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material

Definitions

  • the present invention relates to a nitride semiconductor device and a method for manufacturing the same.
  • III-V nitride semiconductor materials such as gallium nitride (GaN) (Al Ga in N (0
  • ⁇ x ⁇ l, 0 ⁇ y ⁇ l) is a key device for achieving ultra-high-density recording with optical disc devices, and is currently reaching a practical level. is there.
  • Increasing the output of a blue-violet semiconductor laser is an indispensable technology not only for enabling high-speed writing of optical discs but also for developing new technical fields such as application to laser displays.
  • GaN substrate has been considered promising as a substrate necessary for manufacturing a nitride semiconductor device.
  • the GaN substrate is superior in crystal lattice matching and heat dissipation compared to the sapphire substrate that has been used in the past.
  • Another advantage is that the GaN substrate is conductive while the sapphire substrate is insulative.
  • electrodes are also formed on the back side of the GaN substrate and current flows in the direction across the GaN substrate. If an electrode is formed on the back surface of a conductive GaN substrate, it becomes possible to reduce the size (chip area) of each semiconductor device, and if the chip area is reduced, it can be fabricated from a single wafer. Since the total number of chips increases, manufacturing costs can be reduced.
  • Patent Documents 1 to 3 A semiconductor laser in which an n-side electrode is formed on the back surface of a GaN substrate is disclosed in Patent Documents 1 to 3, for example.
  • Patent Document 1 Japanese Patent Laid-Open No. 2002-16312
  • Patent Document 2 JP 2004-71657 A
  • Patent Document 3 JP 2004-6718
  • the conventional method is insufficient in improving the contact resistance, and for the reason described in detail later, if a technology for forming irregularities on the back surface of the substrate is adopted at the mass production level, It was also found that there is a problem that it is difficult to manufacture a laser device with a high yield.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nitride semiconductor device that can be manufactured with high yield while improving the electrical contact characteristics on the back side of the substrate, and its It is to provide a manufacturing method.
  • the nitride semiconductor device of the present invention includes a nitride-based semiconductor substrate containing an n-type impurity, a semiconductor multilayer structure formed on the main surface of the semiconductor substrate and including a p-type region and an n-type region,
  • a nitride semiconductor device comprising: a p-side electrode that contacts a part of the p-type region included in the semiconductor multilayer structure; and an n-side electrode provided on a back surface of the semiconductor substrate, the semiconductor substrate
  • the back surface includes a flat region and a rough surface region, and the n-side electrode covers at least a part of the rough surface region.
  • the flat region on the back surface of the semiconductor substrate has a band shape having a width of 20 m or more, and is located around the rough surface region. ing.
  • the contour of the contact region between the back surface of the semiconductor substrate and the n-side electrode is aligned with the boundary between the flat region and the rough surface region.
  • the rough surface region on the back surface of the semiconductor substrate is a polished surface or a clean surface.
  • the main surface of the semiconductor substrate is a + C polar surface.
  • the flat region on the back surface of the semiconductor substrate is a C polarity surface.
  • the rough surface region on the back surface of the semiconductor substrate has a plurality of concave portions or convex portions formed by etching.
  • a plurality of facets having different plane orientations are formed in the rough surface region on the back surface of the semiconductor substrate.
  • the uneven step of the rough surface region on the back surface of the semiconductor substrate is in a range of lOnm or more and the uneven step of the flat region is 10 ⁇ m or less. .
  • the n-side electrode covers the entire rough surface region on the back surface of the semiconductor substrate.
  • the flat region on the back surface of the semiconductor substrate is disposed so as to contact the cleavage position.
  • the n-side electrode is made of Ti, Al, Pt, Au, Mo, Sn, In, Ni,
  • It has a layer formed of at least one metal or alloy selected from the group consisting of Cr, Nb, Ba, Ag, Rh, Ir, Ru, and Hf.
  • the n-side electrode has a contact resistivity of 5 ⁇ 10 ′′ 4 ⁇ -cm 2 or less.
  • the method for manufacturing a nitride semiconductor device of the present invention includes a step of preparing a nitride semiconductor substrate containing an n-type impurity, and a semiconductor multilayer structure including a p-type region and an n-type region. Forming on the main surface of the substrate; forming a P-side electrode in the p-type region included in the semiconductor multilayer structure; forming an n-side electrode on the back surface of the semiconductor substrate including a nitrogen surface; A method of manufacturing a nitride semiconductor device, comprising: forming a flat region and a rough surface region on the back surface before forming an n-side electrode on the back surface of the semiconductor substrate; and forming the n-side electrode. And cleaving the semiconductor substrate so that a cleavage plane passes through the flat region.
  • a step of reducing the carbon concentration on the back surface is performed.
  • the step of reducing the carbon concentration includes a step of forming an insulating film on the back surface of the semiconductor substrate and a step of removing the insulating film.
  • the step of reducing the carbon concentration is performed in the semiconductor substrate.
  • the method includes a step of depositing an oxide silicon film on the back surface and a step of removing the acid silicon film.
  • the step of forming the rough surface region includes a mask having an opening that exposes a portion of the back surface of the semiconductor substrate where the rough surface region is to be formed. Forming a layer on the back surface of the semiconductor substrate; and performing an etching process on a portion of the back surface of the semiconductor substrate where the rough surface region is to be formed.
  • the step of forming the n-side electrode includes a step of depositing a metal electrode layer on the back surface of the semiconductor substrate so as to cover the mask layer, and a step of forming the metal electrode layer.
  • the effective area of the contact interface is increased by the rough surface area at the interface between the back surface of the nitride-based semiconductor substrate and the n-side electrode, and the carbon concentration at the contact interface is reduced. This also improves the contact characteristics of the n-side electrode. Furthermore, since the cleavage is facilitated, a semiconductor laser device can be manufactured with a high yield.
  • FIG. 1 is a perspective view schematically showing a GaN crystal structure in a GaN substrate.
  • FIG. 2 is a cross-sectional view showing a first embodiment of a nitride semiconductor device according to the present invention.
  • FIG. 3 (a) is a plan view showing a part on the upper surface side of the nitride semiconductor substrate in Embodiment 1
  • FIG. 3 (b) is a plan view showing the back surface side of the nitride semiconductor substrate.
  • FIG. 4 is a cross-sectional view showing the main part of the nitride semiconductor device before cleavage in Embodiment 1.
  • FIG. 5 (a) and (b) are perspective views schematically showing primary cleavage.
  • FIG. 6 is a cross-sectional view showing another embodiment of the nitride semiconductor device according to the present invention.
  • FIG. 7 is a cross-sectional view showing still another embodiment of a nitride semiconductor device according to the present invention. Explanation of symbols
  • the inventor of the present application has attributed the cause of the high electrical external resistance of the n-side electrode formed on the bottom surface of the nitride semiconductor substrate to carbon (C) existing on the back surface of the nitride semiconductor substrate.
  • C carbon
  • the present inventors have found out that it is effective to reduce the contact resistance by reducing the carbon concentration at the interface between the back surface of the nitride semiconductor substrate and the n-side electrode. .
  • the GaN crystal is composed of Ga atoms and N nuclear power, and has a hexagonal crystal structure.
  • the surface (top surface) of the GaN substrate on which epitaxial growth of various semiconductor layers is performed is a surface (Ga surface or + C polar surface) in which Ga atoms are arranged in layers.
  • the back side of the GaN substrate is a surface (nitrogen surface or Is —C polarity plane).
  • the nitrogen surface (hereinafter referred to as the “N surface”) has a property that always appears on the back surface of the GaN substrate even when the GaN substrate is polished from the back surface side and the substrate thickness is reduced to an arbitrary thickness. ing. Note that even in a general nitride semiconductor substrate in which Ga atoms of the GaN substrate are substituted with A1 atoms or In atoms at some sites, the back surface of the substrate is the N plane as described above.
  • the N surface of a nitride semiconductor substrate such as a GaN substrate adsorbs carbon and immediately forms an electrode on the N surface, and then the carbon stabilizes at the interface between the N surface and the electrode.
  • This carbon exists stably at the interface where it does not diffuse to the surroundings even by heat treatment after electrode formation, and functions as an electrical barrier at the contact interface. If the carbon existing on the backside of the substrate can be properly eliminated before the n-side electrode is formed, the electrical barrier existing at the contact interface can be reduced, and the contact characteristics of the n-side electrode can be significantly improved.
  • the GaN substrate has a hexagonal crystal structure
  • the process of separating the individual semiconductor chips (having a substantially rectangular parallelepiped shape! / Spinning) by “cleavage” of the GaN substrate is performed with a high yield. It is very difficult to do.
  • a plurality of “concave arrangements hereinafter referred to as“ cleavage guides ”)” are formed on the cleave line on the upper surface side of the GaN substrate, and “cleave guides” are formed from the back side of the substrate. It is effective to adopt a method of primary cleavage along
  • the GaN substrate Since the GaN substrate has translucency, the position of the “cleavage guide” formed on the upper surface side of the substrate is originally observed by the force on the back surface side of the substrate, and primary cleavage is performed along the cleavage guide. Is possible. However, if unevenness is formed on the entire back surface of the GaN substrate, irregular reflection occurs on the back surface of the substrate, making it impossible to observe the cleavage guide from the back surface of the substrate. For this reason, when unevenness is formed on the back surface of the GaN substrate according to the conventional technology, the cleavage process cannot be performed with a high yield.
  • unevenness is formed only on a specific region, so that the back surface of the substrate is roughened with a flat region (window region). It is divided into surface areas.
  • the n-side electrode is formed so as to cover at least a part of the rough surface region.
  • the “flat region” in this specification is a relatively smooth surface as compared to the “rough surface region”. More specifically, the “flat region” is a portion of the back surface of the substrate that is kept smooth by polishing, and means a region that is not intentionally uneven. However, the “flat region” may be subjected to a cleaning process (cleaning process) after polishing polishing.
  • the “rough surface region” is a portion of the back surface of the substrate where irregularities are intentionally formed by a process such as etching. If the etching for roughening is anisotropic etching with different etching rates depending on the crystal plane orientation, facets having a plurality of different plane orientations are formed in the roughened area.
  • a semiconductor multilayer structure is formed on the surface (Ga surface) of a nitride semiconductor substrate by a known semiconductor growth method using an epitaxy growth technique.
  • the semiconductor stacked structure includes a p-type region and an n-type region.
  • the semiconductor stacked structure includes a double hetero structure and a structure for confining light and current in a certain space.
  • a special process that is, a step of forming a rough surface region in a predetermined region on the back surface of the nitride semiconductor substrate is performed. This step can be performed by covering a part of the back surface of the substrate with a mask layer and then etching a region not covered with the mask layer.
  • surface treatment for reducing the carbon concentration is performed.
  • This treatment includes a step of covering the back surface of the nitride semiconductor substrate with a layer of deposit, and a step of removing this layer by etching. More preferably, after depositing a silicon dioxide (SiO 2) film on the back side of the nitride semiconductor substrate, this Si o Remove the membrane from the back. According to the experiments of the present inventor, the above treatment is performed on the back surface of the substrate.
  • the concentration of carbon existing on the back of the substrate is greatly increased.
  • the effective contact area increases at the interface between the substrate back surface and the n-side electrode, and the interface
  • the carbon concentration in can be reduced below the detection limit of the measuring device. As a result, the contact resistance is greatly reduced.
  • a plurality of recesses (cleavage guides) that define cleavage lines are formed in the upper part of the semiconductor multilayer structure provided on the substrate main surface side.
  • a recess can be easily formed by, for example, a scribe technique and an etching technique.
  • the cleaving guide is observed through the flat region existing at a position not covered by the n-side electrode, and the primary cleavage is performed from the back surface of the substrate along the cleavage guide. Is performed to divide the nitride semiconductor substrate into a plurality of bars. The individual semiconductor laser chips can then be separated from each bar by performing secondary cleavage for each bar.
  • FIG. 2 schematically shows a cross section of the nitride semiconductor device of this embodiment, that is, a GaN-based semiconductor laser.
  • the element cross section shown in the figure is a plane parallel to the resonator end face, and the resonator length direction is orthogonal to the cross section.
  • the semiconductor laser of this embodiment includes an n-type GaN substrate doped with an n-type impurity (thickness: about
  • the semiconductor multilayer structure 100 includes an n-type GaN layer 12, an n-type AlGaN cladding layer 14, a GaN light guide layer 16, an InGaN multiple quantum well layer 18, an InGaN intermediate layer 20, a p-type AlGaN cap layer 22, and a p-type GaN. Includes light guide layer 24, p-type AlGaN cladding layer 26, and p-type GaN contact layer 28 It is out.
  • the impurity concentration (dope concentration) and thickness of each semiconductor layer included in the semiconductor multilayer structure 100 in the present embodiment are as shown in Table 1 below.
  • the p-type GaN contact layer 28 and the p-type AIGaN cladding layer 26 are processed into a ridge stripe shape extending along the resonator length direction.
  • the width of the ridge stripe is, for example, about 1.5 m, and the resonator length is, for example, 600 m.
  • the chip width (element size in the direction parallel to each semiconductor layer in FIG. 5) is, for example, 200 m.
  • the portion excluding the upper surface of the ridge stripe is the SiO layer 3
  • the upper surface of the ridge stripe is exposed at the center of the SiO layer 30.
  • a stripe-shaped opening to be formed is formed.
  • the surface of the p-type GaN contact layer 28 is in contact with the p-side electrode (Pd / Pt) 32 through the opening of the two layers 30.
  • the back surface of the n-type GaN substrate 10 is divided into a rough surface region 40a where unevenness is formed and a flat region 40b where unevenness is not formed.
  • the n-side electrode (TiZPtZAu) 34 is provided so as to cover the rough surface region.
  • the uneven step in the rough surface area 40a is, for example, in the range of 10 nm or more (preferably 50 nm or more) and 1 ⁇ m or less.
  • the uneven step in the flat region 40b is in the range of, for example, not less than 1 nm and not more than 10 nm.
  • the carbon concentration at the interface between the back surface of the n-type GaN substrate 10 and the n-side electrode 34 is reduced to 5 atomic% or less, more specifically to 2 atomic% or less.
  • an n-type GaN substrate 10 prepared by a known method is prepared.
  • the n-type GaN substrate 10 has a thickness of about 400 m, for example.
  • the surface of the n-type GaN substrate 10 is planarized by a polishing cage.
  • the semiconductor multilayer structure 100 is formed on the surface of the n-type GaN substrate 10.
  • the semiconductor stacked structure 100 can be formed by a known epitaxial growth technique.
  • each semiconductor layer is grown as follows.
  • the n-type GaN substrate 10 is inserted into the chamber of a metal organic chemical vapor deposition (MOVPE) apparatus. Thereafter, the surface of the n-type GaN substrate 10 is subjected to a heat treatment (thermal cleaning) of about 500 to L 100 ° C. This heat treatment is performed, for example, at 750 ° C for 1 minute or longer, preferably 5 minutes or longer. During this heat treatment, gases containing nitrogen atoms (N) (N, NH, hydra) (N, NH, hydra) (N, NH, hydra) containing nitrogen atoms
  • the temperature of the reactor is controlled to about 1000 ° C, and trimethylgallium (TMG) and ammonia (NH3) gases as source gases and carrier gases hydrogen and nitrogen are simultaneously supplied.
  • TMG trimethylgallium
  • NH3 ammonia
  • silane (SiH) gas is supplied as an n-type dopant, and the thickness is about 1 ⁇ m.
  • An n-type GaN layer 12 having an object concentration of about 5 ⁇ 10 17 cm 3 is grown.
  • an n-type AlGaN cladding layer 14 having an Al Ga N force of about 1.5 m in thickness and Si impurity concentration of about 5 ⁇ 10 17 cm- 3 is formed.
  • a GaN optical guide layer16 of GaN with a thickness of about 120 nm
  • the temperature is lowered to about 800 ° C.
  • the carrier gas is changed to nitrogen, and trimethylindium (TMI) and TMG are supplied.
  • TMI trimethylindium
  • a multiple quantum well active layer 18 consisting of m InGaN barrier layers (two layers) is grown. That
  • InGaN intermediate layer 20 made of InGaN is grown.
  • the p-type dopant (Mg) diffusion from the p-type semiconductor layer formed on the active layer 18 to the active layer 18 is greatly suppressed, and the active layer 18 can be maintained in high quality even after crystal growth.
  • the temperature in the reactor is again raised to about 1000 ° C, hydrogen is introduced into the carrier gas, and p-type dopant biscyclopentagel magnesium (Cp Mg) Ga
  • Al Ga N with a film thickness of about 20 nm and an Mg impurity concentration of about l X 10 19 cm— 3
  • P-type AlGaN cap layer 22 with 0.20 0.80 force is grown.
  • a second GaN optical guide layer 24 having a thickness of about 20 nm and an Mg impurity concentration of about 1 ⁇ 10 19 cm ⁇ 3 and having a p-type GaN force is grown.
  • a p-type AlGaN cladding layer 26 made of AlGaN having a thickness of about 0.5 m and an impurity concentration of about 1 ⁇ 10 19 cm ⁇ 3 is grown.
  • a p-type GaN contact layer 28 having a thickness of about 0.1 ⁇ m and an Mg impurity concentration of about 1 ⁇ 10 2Q cm— 3 is grown.
  • FIG. 3 (a) is a plan view of a part of the semiconductor substrate as seen from the upper surface side.
  • the rows of cleavage guides 50 are periodically arranged on the line to be cleaved, and function so that cleavage occurs along that line.
  • Each recess functioning as the cleavage guide 50 has, for example, a depth of 1 to 20 ⁇ m, a width of 1 to 5 ⁇ m, and a length of 1 to 40 ⁇ m, and is formed by a scribe process and an etching process. obtain.
  • FIG. 1 is a plan view of a part of the semiconductor substrate as seen from the upper surface side.
  • the rows of cleavage guides 50 are periodically arranged on the line to be cleaved, and function so that cleavage occurs along that line.
  • Each recess functioning as the cleavage guide 50 has, for example, a depth of 1 to 20 ⁇ m, a width of 1 to 5 ⁇ m, and a length of 1 to 40
  • the arrangement pitch of the recesses corresponds to the arrangement pitch of the semiconductor laser element regions on the substrate, but if the cleavage can be guided in an appropriate direction, the recesses are arranged.
  • the shape and the size of the array pitch are arbitrary.
  • the recess has a rhombus shape having an acute angle in the “cleavage direction” when viewed from the upper surface side of the substrate, and a cross-sectional shape perpendicular to the substrate is a weight. This is because, when the row of concave portions having such a shape is used as a cleavage guide, the cleavage of the substrate back side force also proceeds straight along the row of concave portions, and the cleavage yield is improved immediately.
  • the n-type GaN substrate 10 is polished from the back side, and the thickness of the n-type GaN substrate 10 is reduced to about 100 ⁇ m.
  • a mask layer 42 having a lattice shape is formed on the back surface of the n-type GaN substrate 10, and the region that should be covered with the mask layer 42 is exposed to an etching solution. As a result, a large number of etch pits or protrusions are formed to roughen the surface.
  • the etch ing liquid for example, using a Mizusani ⁇ potassium (KOH) or hot phosphoric acid, 10-6 0 minutes at room temperature, by etching the above number density 5 X 10 6 number ZCM 2, the depth 10 ⁇ : LOO Onm pits can be formed.
  • the formation of the roughened region (rough surface region 40a) may be performed by dry etching instead of the above wet etching or in combination with wet etching.
  • the mask layer 42 has a plurality of openings that define the position and shape of the rough surface region 40a, and can be produced, for example, by exposing and developing a resist film.
  • the portion of the back surface of the n-type GaN substrate 10 that is covered with the mask layer 42 corresponds to a portion where primary cleavage or secondary cleavage is performed. Etch pits are not formed in the area of the back surface of the n-type GaN substrate 10 covered with the mask layer 42, and it functions as a flat area 40b.
  • the rough surface region 40a is formed in the region where the n-side electrode 34 is to be formed on the back surface of the substrate by the above method, the area ratio of the N surface at the contact interface is reduced. , The surface area increases. This has the effect of reducing the carbon concentration at the contact interface, and also increases the effective area of the contact, making it possible to reduce the contact resistance.
  • the thickness of the back surface (polished surface) of the n-type GaN substrate 10 is about 0.5 to 1. by the ECR sputtering method for the purpose of further reducing the contact resistance.
  • the SiO film is removed.
  • the SiO film has at least an n-side current on the back surface of the n-type GaN substrate 10.
  • Etchant used to remove the SiO film is hydrofluoric acid.
  • etching it is not limited to etching, and dry etching or a combination of wet etching and dry etching may be used. Even if irregularities are formed on the back surface of the substrate, a part of the N surface may remain in the rough surface region 42, and carbon may be adsorbed on such an N surface, which may deteriorate the contact characteristics. For this reason, it is preferable to perform the above-mentioned back surface treatment (carbon reduction treatment).
  • each metal layer of TiZPtZAu is continuously deposited on the back surface of the n-type GaN substrate 10 in this order from the substrate side.
  • the position on the mask layer 42 is increased.
  • the lift-off of the metal layer to be placed is performed, and the n-side electrode 34 is also formed on the metal layer force located on the rough surface region 40a.
  • sintering is performed in a nitrogen atmosphere (about 300 ° C). This sintering process has the effect of further reducing the contact resistance of the n-side electrode 34. According to this embodiment, it is possible and child contact resistivity of the n-side electrode 34 below 5 X 10- 4 ⁇ 'cm.
  • the n-side electrode 34 is patterned using the mask layer 42 used for forming the rough surface region 40a, the back surface of the n-type GaN substrate 10, the n-side electrode 34, The contour of the contact region is aligned with the boundary between the rough surface region 40a and the flat region 40b.
  • FIG. 4 is a cross-sectional view showing a part of the n-side GaN substrate 10 at the stage where the n-side electrode 34 is formed.
  • the unevenness formed by etching is formed on a part (rough surface region) of the back surface of the substrate. Such irregularities also constitute facet surface forces where crystal planes other than the (000-1) plane are exposed.
  • the rough surface region in this embodiment has a plurality of protrusions formed by etching, and each protrusion (height: 10 to: LOOOnm) is a polygonal pyramid type or a polygonal frustum type, and its surface Consists of facet faces other than the (000-1) face.
  • FIGS. 5 (a) and 5 (b) schematically show the process of forming the semiconductor substrate force bar 10a by primary cleavage.
  • the semiconductor laser shown in FIG. 2 can be obtained by performing secondary cleavage on the bar 10a obtained by primary cleavage.
  • the direction of secondary cleavage is orthogonal to the direction of primary cleavage.
  • the n-side electrode having the rough surface region 40a as the contact surface is formed, it is possible to increase the effective area of the contact surface and reduce the carbon concentration in the contact surface. Therefore, the contact resistance of the n-side electrode can be reduced. Further, as shown in FIG. 3 (b), the cleavage guide can be observed from the back side of the substrate, so that the cleavage can be performed with a high yield. In addition, the flat region 40b on the back surface of the substrate in each semiconductor laser element in which the substrate force is also divided by cleavage is disposed so as to contact the cleavage position.
  • the region 40b has a band shape having a width of 20 / zm or more, and is located around the rough surface region 40a (see FIG. 3B).
  • the layout of the flat region 40b on the back surface of the substrate is not limited to the example shown in FIG.
  • the flat region 40b may be formed at a position where the cleavage guide 50 can be observed from the back side of the substrate.
  • FIGS. 6 and 7 another embodiment of the nitride semiconductor device according to the present invention will be described.
  • the embodiment shown in FIG. 6 has the same configuration as the semiconductor laser device in Embodiment 1 except that the flat region on the back surface of the n-type GaN substrate is covered with an insulating layer 36.
  • an insulating layer 36 such as a SiO film may remain on a part of the back surface of the substrate.
  • the region force where the n-side electrode 34 should be in contact with the backside of the substrate is a force that needs to remove the insulating film. Even if a part of the insulating film remains around the n-side electrode 34 as the insulating layer 36, the contour There is no effect on the tatoo characteristics. Also, leave the insulating layer 34 with strong force such as SiO on the back of the substrate.
  • the insulating layer 34 absorbs light (stray light) leaking from the active layer 18 to the substrate 10, and an effect of reducing noise can be obtained.
  • the embodiment shown in FIG. 7 has the same configuration as the semiconductor laser device of Embodiment 1 except that the back surface of the substrate is inclined. As shown in FIG. 7, the entire back surface of the substrate may be inclined from the N surface. This can be realized by inclining and fixing the back surface of the substrate with respect to the polishing board during polishing of the back surface of the substrate.
  • the present invention since the contact resistance at the interface between the back surface of the substrate and the n-side electrode is reduced, there is a way to use various kinds of powerful metals as materials for the n-electrode. be opened. That is, metals or alloys such as Ti, Al, Pt, Au, Mo, Sn, In, Ni, Cr, Nb, Ba, Ag, Rh, Ir, Ru, or Hf should be used as the material for the n-side electrode. It becomes possible.
  • a GaN substrate is used as the nitride semiconductor substrate.
  • the nitride semiconductor substrate is not limited to GaN, and is a substrate formed of AlGaN, InGaN, or the like. May be. Further, the substrate may be an off-substrate.
  • the present invention contributes to mass production of highly reliable nitride semiconductor lasers and the like in order to improve the n-side electrode contact characteristics in nitride semiconductor devices that are expected to be used as short-wavelength light sources and high breakdown voltage devices. it can.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

L’invention concerne un dispositif semi-conducteur à base de nitrure (100) qui est pourvu d’un substrat n-GaN (1) ; d’une structure multicouche semi-conductrice qui est formée sur un plan principal du substrat n-GaN (1) et comprend une région de type p et une région de type n ; d’une électrode de côté p (32) en contact avec une partie de la région de type p comprise dans la structure multicouche semi-conductrice ; et d’une électrode de côté n (34) positionnée sur un plan arrière du substrat (1). Le plan arrière du substrat (1) comprend une région de surface rugueuse (40a) et une région de surface plate (40b), et l'électrode de côté n (34) recouvre au moins une partie de la région de surface rugueuse (40a).
PCT/JP2006/309550 2005-05-19 2006-05-12 Dispositif semi-conducteur a base de nitrure et son procede de fabrication Ceased WO2006123580A1 (fr)

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US11/570,147 US7606276B2 (en) 2005-05-19 2006-05-12 Nitride semiconductor device and method for fabricating the same
JP2006536906A JP4842827B2 (ja) 2005-05-19 2006-05-12 窒化物半導体装置及びその製造方法

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JP2008172040A (ja) * 2007-01-12 2008-07-24 Sony Corp 半導体発光素子、半導体発光素子の製造方法、バックライト、ディスプレイおよび電子機器
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JP2011113997A (ja) * 2009-11-24 2011-06-09 Toyota Central R&D Labs Inc 半導体装置とその製造方法
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WO2012090254A1 (fr) * 2010-12-28 2012-07-05 Ｄｏｗａエレクトロニクス株式会社 Électrode pour contact ohmique à semi-conducteur de type n à base de nitrure du groupe iii et son procédé de fabrication
JP2013128150A (ja) * 2013-03-26 2013-06-27 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物半導体からなる発光素子の製造方法
JP2013157350A (ja) * 2012-01-26 2013-08-15 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物半導体レーザ、及びｉｉｉ族窒化物半導体レーザを作製する方法
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JP2015035541A (ja) * 2013-08-09 2015-02-19 ソニー株式会社 発光素子及びその製造方法
JP2015056533A (ja) * 2013-09-12 2015-03-23 株式会社東芝 半導体装置及びその製造方法
JP2015111724A (ja) * 2007-12-21 2015-06-18 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ レーザー光源
JP2015177135A (ja) * 2014-03-17 2015-10-05 株式会社東芝 半導体発光素子
JP2015212733A (ja) * 2014-05-01 2015-11-26 日本電信電話株式会社 半導体基板
JP2023162378A (ja) * 2019-10-29 2023-11-08 京セラ株式会社 半導体素子
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JP2025506635A (ja) * 2022-02-24 2025-03-13 エイエムエス－オスラム インターナショナル ゲーエムベーハー 端面発光半導体レーザダイオード

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US12364085B2 (en) 2020-01-09 2025-07-15 Enkris Semiconductor, Inc. Semiconductor structure and substrate thereof, and manufacturing methods for semiconductor structures and substrates thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016312A (ja) * 2000-06-27 2002-01-18 Sanyo Electric Co Ltd 窒化物系半導体素子およびその製造方法
JP2004071657A (ja) * 2002-08-01 2004-03-04 Nec Corp Ｉｉｉ族窒化物半導体素子、ｉｉｉ族窒化物半導体基板およびｉｉｉ族窒化物半導体素子の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566484A (en) * 1979-06-28 1981-01-23 Sanyo Electric Co Ltd Manufacture of solid state light emitting device
JP3773282B2 (ja) * 1995-03-27 2006-05-10 豊田合成株式会社 窒化ガリウム系化合物半導体の電極形成方法
JP4493127B2 (ja) * 1999-09-10 2010-06-30 シャープ株式会社 窒化物半導体チップの製造方法
JP3660570B2 (ja) * 2000-08-17 2005-06-15 日本電信電話株式会社 結晶性基板の劈開方法
JP4233268B2 (ja) * 2002-04-23 2009-03-04 シャープ株式会社 窒化物系半導体発光素子およびその製造方法
JP2004221112A (ja) * 2003-01-09 2004-08-05 Sharp Corp 酸化物半導体発光素子
US7102175B2 (en) * 2003-04-15 2006-09-05 Matsushita Electric Industrial Co., Ltd. Semiconductor light-emitting device and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016312A (ja) * 2000-06-27 2002-01-18 Sanyo Electric Co Ltd 窒化物系半導体素子およびその製造方法
JP2004071657A (ja) * 2002-08-01 2004-03-04 Nec Corp Ｉｉｉ族窒化物半導体素子、ｉｉｉ族窒化物半導体基板およびｉｉｉ族窒化物半導体素子の製造方法

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JP2015111724A (ja) * 2007-12-21 2015-06-18 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ レーザー光源
US9559496B2 (en) 2007-12-21 2017-01-31 Osram Opto Semiconductors Gmbh Laser light source
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JP2017017365A (ja) * 2007-12-21 2017-01-19 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ レーザー光源及び該レーザー光源の製造方法
US9531158B2 (en) 2007-12-21 2016-12-27 Osram Opto Semiconductors Gmbh Laser light source
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US8963290B2 (en) 2010-12-28 2015-02-24 Dowa Electronics Materials Co., Ltd. Semiconductor device and manufacturing method therefor
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