WO2006119488A1 - An analog to digital conversion method and apparatus for a multiple channel receiver - Google Patents

Abstract

An apparatus and method for first creating and then processing a set of spectral images that allows for recovery of a wide bandwidth signal in a multi-channel satellite receiver (108) while utilizing a low performance ADC (46, 48). More specifically, received analog signals are mixed (36, 38, 40) with a mixing signal to generate a first set of analog signals (i.e., a first spectral image) and a second set of analog signals (i.e., a second spectral image). The received analog signals are within a range of frequencies with each received analog signal having a different frequency and containing a datastream or channel. The mixing signal has a frequency that is within the range of frequencies and that is not equal to the frequency of each received signal. The mixed signals are then converted or digitized using a low performance ADC (46, 48) and the converted signals are processed (50) so a desired channel or datastream is extracted.

Description

AN ANALOG TO DIGITAL CONVERSION METHOD AND

APPARATUS FOR A MULTIPLE CHANNEL RECEIVER

This application claims the benefit under 35 U.S.C. section 119 of provisional application 60/677,497 filed in the United States on May 4, 2005.

FIELD OF THE INVENTION

The present invention relates to communication systems and, more particularly, to a receiver capable of receiving multiple channels simultaneously.

BACKGROUND OF THE INVENTION

This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Communications systems having higher data throughput and greater efficiency in the use of available bandwidth are increasingly in demand. In a typical communications system, such as a satellite communications system, a satellite provides a plurality of communications channels to terrestrial receivers. Each communications channel has associated with it, for example, a particular transponder, a particular polarization and the like. One conventional approach to implement a satellite system having higher data throughput and greater bandwidth efficiency is to utilize a high performance analog to digital converter ("ADC") for converting a received analog signal into a digital signal. High performance ADCs typically have higher sampling rates and larger bandwidths than low performance ADCs. However, there are a number of drawbacks to the utilization of and reliance on high performance ADCs. For example, an increase in the desired data throughput and bandwidth efficiency for the satellite system may outstrip the evolution of ADCs. Furthermore, high performance ADCs cost more than low performance ADCs.

The present invention is directed towards overcoming these drawbacks.

SUMMARY OF THE INVENTION An apparatus and method for first creating and then processing a set of spectral images that allows for recovery of a wide bandwidth signal in a multi-channel satellite receiver while utilizing a low performance ADC. More specifically, received analog signals are mixed with a mixing signal to generate a first set of analog signals (i.e., a first spectral image) and a second set of analog signals (i.e., a second spectral image). The received analog signals are within a range of frequencies with each received analog signal having a different frequency and containing a datastream or channel. The mixing signal has a frequency that is within the range of frequencies and that is not equal to the frequency of each received signal. The mixed signals are then converted or digitized using a low performance ADC and the converted signals are processed so a desired channel or datastream is extracted.

These and other advantages and features of the invention will become readily apparent to those skilled in the art after reading the following detailed description of the invention and studying the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram illustrating a conventional high performance ADC processing arrangement for use in a multiple channel receiver;

Fig. 2 is a block diagram illustrating an ADC processing arrangement of the present invention for use in a multiple channel receiver; Figs. 3-13 illustrate an exemplary signal being processed by the

ADC processing arrangement of Fig. 2; and

Fig. 14 is an exemplary satellite receiver system utilizing the ADC processing arrangement of the present invention.

DETAILED DESCRIPTION

The following is a detailed description of the presently preferred embodiments of the present invention. However, the present invention is in no way intended to be limited to the embodiments discussed below or shown in the drawings. Rather, the description and the drawings are merely illustrative of the presently preferred embodiments of the invention. One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Referring now to Fig. 1, a conventional digital tuner having a high-end ADC processing arrangement 10 is shown. The digital tuner may be used in a receiver such as a satellite receiver. The digital tuner is capable of tuning to a single channel from a plurality of channels provided at the input. The channels may include, inter alia, datastreams of video, audio and graphical information. Some exemplary datastreams may include programming such as broadcast, pay per view and video on demand programming, program guides, and games. The input, containing all of the channels within a received analog signal, is provided to an amplifier 12. Amplifier 12 provides signal gain necessary for input into an analog to digital converter (ADC) 16. Amplifier 12 may be a fixed gain amplifier, or may have the ability for gain adjustment, for instance, through an automatic gain control. A band pass filter 14 is connected between the output of amplifier 12 and the input of ADC 16 in order to remove any unwanted signal energy, particularly signal energy outside the frequency range of interest (both above and below). Bandpass filter 14 also removes signal energy produced by amplifier 12 outside the frequency range of interest due to, for instance, distortion.

Filter 14 connects to the ADC 16. ADC 16 samples the incoming signal using a clock signal (not shown) to produce a series of samples where each sample contains a set of bits. The digital signal from ADC 16 is passed to a plurality of multipliers 18. Each of the plurality of multipliers 18 also receives a second input signal from a plurality of digital signal generators 20. One exemplary digital signal generator is a numerically controlled oscillator (NCO). Each signal generator 20 supplies a sinusoidal signal that is multiplied with the digital signal received from ADC 16 to produce a frequency translation of the digital signal based on the frequency of the sinusoid. The frequency of the sinusoid is selected based on which of the incoming channels in the digital signal is desired. The output of each multiplier 18 represents the incoming digital signal frequency translated such that the desired channel is located at or near baseband frequency range. The output of each multiplier 18 connects to a lowpass filter 22 that filters the desired channel by removing all of the other channels present in the digital signal.

In summary, Fig. 1 represents a multichannel receiver wherein each multiplier 18, signal generator 20 and LPF 22 arrangement may tune to a different channel contained in the digital signal provided by high-end ADC. Although using a high-end ADC in a multiple channel receiver is useful, there are some drawbacks. There are three fundamental factors governing the performance of an ADC. The first factor is the sampling speed. Generally, the higher the sampling speed the higher the performance. It is a requirement that the sampling be at least two times the input signal bandwidth (not necessarily the signal absolute frequency). The second factor is the number of required bits of resolution. The requirement of number of bits of resolution is partly determined by the needed signal to noise ratio (SNR) of the recovered signal and also the signal frequency bandwidth. The higher the number of bits, the better signal to noise ratio can be maintained in the ADC. The third factor is the input operational bandwidth. This factor is often related to sampling speed, but normally focuses on the ability of the ADC properly recognize the signal (in a dynamic sense) rather than whether the signal can be sampled. The interaction between input operational bandwidth and sampling speed leads to the techniques permitting undersampling.

For example, consider a signal at a high frequency but occupying a limited frequency bandwidth such as a L-Band signal present between 1000 and 1500 MHz and occupying a bandwidth of 500 MHz. The signal could be sampled at a frequency of 3000 MHz and properly recovered. The input operational bandwidth would need to be at least 500 MHz, a nominal requirement. It should be noted that ADCs having sampling frequencies of 3000 MHz do not currently exist and when these ADCs are eventually implemented one drawback in their utilization will be that their cost will be prohibitively expensive for most applications. Alternatively, using undersampling the signal could also be sampled at 1000 MHz (two times the signal bandwidth) and be properly recovered. The operational bandwidth of the converter would still need to be at least 500 MHz. Now, however, the output signal would be translated from its original signal position between 1000 to 1500 MHz (which is the position the signal would remain at if sampled at 3000 MHz) to a frequency range from DC to 500 MHz. Further, the final (digital) spectrum with a 1000 MHz sampling rate is 500 MHz, as opposed to 1500 MHz for the 3000 MHz sampling rate. It should be appreciated that the 1500 MHz spectrum may need at least one more bit of resolution in order to maintain an overall high SNR comparable to the SNR of the 500 MHz spectrum. This is because the wider the bandwidth the more likely noise, such as the quantization noise level introduced by ADCs, will be inserted into the signal. In other words, a higher sampling rate may introduce quantization noise and raise the SNR such that additional resolution bits are needed to achieve an acceptable SNR. Of course, the introduction of additional resolution bits has the drawback of increasing the cost of the ADC.

Although ADCs undersampling at 1000 MHz currently exist, one drawback is that undersampling is not always a viable solution. The use of undersampling requires two factors related to the signal to be sampled and the sample clock. First, the bandwidth of the signal must be less than or equal to one half of the sample clock frequency and the position of the signal must be such that the signal falls within a region of frequencies that do not overlap the sample clock frequency or the sample clock's frequency harmonics. As a result, undersampling may not be appropriate or useful for all signals. The present invention, as described below, utilizes the lowest possible performance ADCs by always presenting a signal to each ADC at the lowest frequencies (around DC) and by restricting each signal presented to each ADC to occupy only half the frequency bandwidth of the original signal. For example, restricting each ADC input signal to a bandwidth of 250 MHz, instead of received signal bandwidth of 500 MHz. As a result, both the operational input bandwidth and the sampling speed are lowered relative to the high performance ADC. It should be noted that the lower bandwidth allows a reduction in the number of bits needed for an acceptable SNR which, in turn, lowers the cost of the ADC.

Referring now to Fig. 2, an ADC processing arrangement 30 of the present invention for use in a multichannel receiver is shown. An input signal is provided to an amplifier 32 and the output of amplifier 32 is connected to a bandpass filter 34. The amplifier 32 and bandpass filter 34 have the same characteristics and properties as described in Fig. 1.

The output of the bandpass filter 34 connects to two mixer circuits 36, 38. Each mixer circuit 36, 38 also receives a second input from a signal generator or oscillator 40. Oscillator 40 is capable of producing both an in phase (i.e., cosine) and quadrature (i.e., sine) signal at the same frequency. The in phase frequency signal is provided to the upper mixer 36, while the quadrature frequency signal is provided to the lower mixer 38. The frequency for the oscillator 40 is selected as the arithmetic center of the frequency range of the input signal rather than the frequency of a particular channel with the input signal. For instance, if the incoming frequency range is 950 to 1450 MHz, the signal generator or oscillator 40 may be set to a frequency of 1200 MHz. Oscillator 40 may be controlled by processing a lower frequency signal, such as a crystal oscillator (not shown) and may further be controlled within a phase locked loop structure (also not shown).

Each mixer circuit 36, 38 output connects to a low pass filter 42, 44 that filters out any undesired signals produced in the mixer circuits 36, 38 that are outside of the converted range of the original signal. Each low pass filter 42, 44 output connects to an ADC 46, 48. Each ADC 46, 48 samples the incoming signal using a clock signal (not shown) to produce a series of samples where each sample contains a set of bits.

The signals output by each ADC 46, 48 represent the original signal. More specifically, each signal represents a complex form of the original real format signal. Unlike a real signal, where the energy present in the upper sideband (USB) and the energy in the lower sideband (LSB) is correlated, the complex frequency mixing creates two signals or spectral images each representing a complex signal that is a separately unrecoverable form of the original signal. The complex signal contains upper and lower sidebands that are not correlated and in fact contain different channels now mirrored across the arithmetic center frequency that is translated by mixers 36, 38 to coincide with DC. The presence of the two signals in separate complex form, however, allows both a reconstruction of the original signal and permits further processing of the signal for channel extraction.

The advantage of the signal processing performed by mixers 36, 38 and oscillator 40 is that the processing speed and performance of ADCs 46, 48 is lower than would otherwise be required in the high-end

ADC arrangement of Fig. 1. Although two ADCs 46, 48 are now required, along with additional digital signal processing as will be described below, each ADC 46, 48 may now operate at a sampling rate at least one half of the sampling rate necessary for normal processing and with at least one fewer bit of resolution. For instance, a signal with 500 MHz bandwidth would normally require a sampling rate of at least 1000 MHz at, for instance, 10 bits of resolution. Under the approach of the present invention, the same signal now in a complex form, can be sampled using two ADCs 46, 48 operating at a sampling rate of 500 MHz and requiring only 9 bits of resolution. Since the cost performance curve for devices such as ADCs is not typically linear in either sampling speed or resolution performance but rather often exponential, significant cost savings may be realized even with employing two low-end ADCs 46, 48 instead of one high-end ADC.

Each ADC 46, 48 output is connected to processing circuitry 50 for reconstruction of the original signal and for extracting a channel form the original signal. More specifically, the output of each ADC 46, 48 is split into four separate branches each connected to a multiplier 52-66. Each multiplier 52-66 also has an input from a numerically controlled oscillator 68, 70 that produces both an in phase (i.e. cosine) and quadrature (i.e. sine) signal at a given frequency. The frequency of each numerically controlled oscillator 68, 70 is typically the frequency necessary to recover a desired channel present in either the upper or lower sideband of each of the signals at the output of the ADCs 46, 48. Each of the multiplier outputs are then connected to a set of summing nodes 72-78 for either adding of subtracting a pair of multiplier outputs to recover a desired channel. A subtraction is denoted by showing the addition of an inverter 80, 82 or negative signal at the output of a multiplier 56, 66. The set of summing nodes 72-78 can also add and subtract the multiplier outputs to generate the signal present in the opposite sideband (and also sitting on top or coexistent in frequency as a real signal) in addition to the desired signal. Both of the recovered signals are in phase (I) and quadrature (Q) format, and are denoted in the Fig. 2 as LSB chan I, LSB chan Q, USB, chan I and USB chan Q. The series of multipliers 52-66, NCOs 68, 70 and adders 72-78 illustrate a preferred approach for recovering two channels from the original signal. The two channels that may be recovered, occupy the same frequency range in the new complex signal formed by mixing the original signal in mixers 36, 38. However, two spectral images of the complex signal exist differing only in a phase rotation, an in phase and a quadrature version. By using the in phase and quadrature signals and applying a second in phase and quadrature signal conversion to each of the signals at the outputs of the ADCs 46, 48, a desired channel may be recovered from the set of channels provided in the original signal by adding or subtracting the appropriate "twice converted" and phase rotated signals.

Turning to Figs. 3-13, the processing of an exemplary satellite signal, containing channels T1-T16, by the ADC processing arrangement of the present invention is shown. More specifically, the extraction of channels T2 and T15 from a received satellite signal is illustrated. Referring now to Fig. 3, a conceptual illustration of a received L-

Band signal at point A in the ADC processing arrangement 30 of Fig.2 is shown. More specifically, the L-band signal is shown in its initial position in frequency. A point identified as fmid is shown as a halfway point in the frequency spectrum, to denote the frequency about which the first frequency conversion, using sine and cosine signals, is done. T1-T16 represent channels provided by transponders in a satellite and embedded in a satellite signal received by a multi channel satellite receiver. Referring now to Fig. 4, a conceptual illustration of a signal at point B in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, the figure represents the signal spectrum (in both positive and negative frequency on the real axis) after the signal in Fig. 3 is multiplied or mixed with a cosine signal at a frequency of fmid. Note that the projection onto the positive frequency axis from the negative frequency axis reveals that signal corruption has occurred between the upper and lower sideband (positive and negative) of the resulting signal. For example, the signal energy of channel T15 will be corrupted with signal energy of channel T2. Referring now to Fig. 5, a conceptual illustration of a signal at point C in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, the figure represents the signal spectrum (in both positive and negative frequency on the real axis) after the signal in Fig. 3 is multiplied or mixed with a sine signal at a frequency of fmid. Note that the projection onto the positive frequency axis from the negative frequency axis reveals that signal corruption has occurred between the upper and lower sideband (positive and negative) of the resulting signal as in Fig. 4. Additionally note that the corruption that has occurred is different (as noted by the inversion of the negative axis or LSB). The two separate projections of the signal allow for recovery of the original signal. Referring now to Fig.6, a conceptual illustration of a signal at point D in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, the figure illustrates the signal in Fig. 4 with a further frequency rotation performed by multiplier 52 at a frequency equal to the frequency of the desired channel. As described earlier, both the desired channel, T2 from the LSB, and the undesired channel, T15 from USB, have been co-located or imaged to the DC frequency location. Note that a similar operation exists for the lower point D at the output of multiplier 60, except the desired channel is T15 and undesired channel is T2 Referring now to Fig. 7, a conceptual illustration of a signal at point E in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, the figure illustrates the signal in Fig. 4 with a further frequency rotation performed with multiplier 54 at a frequency equal to the frequency of the desired channel. As described earlier, both the desired channel, T2 from the LSB, and the undesired channel, T15 from USB, have been co-located or imaged to the DC frequency location. Although, in Figs. 6 and 7, the input signals have been multiplied with a signal with the same frequency, in Fig. 6 the signal is a sine signal and in Fig. 7 the signal is a cosine signal. Note that a similar operation exists for the lower point E at the output of multiplier 62 except that the desired channel is T15 and the undesired channel is T2. Referring now to Fig. 8, a conceptual illustration of a signal at point F in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, the figure illustrates the signal in Fig. 5 with a further frequency rotation performed with multiplier 56 at a frequency equal to the frequency of the desired channel. As described earlier, both the desired channel, T2 from the USB, and the undesired channel, T15 from LSB, have been co-located or imaged to the DC frequency location. Note that a similar operation exists for the lower point F at the output of multiplier 64, except that the desired channel is T15 and the undesired channel is T2

Referring now to Fig. 9, a conceptual illustration of a signal at point G in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, the figure illustrates the signal in Fig. 5 with a further frequency rotation performed with multiplier 56 at a frequency equal to the frequency of the desire channel. As described earlier, both the desired channel, T15 from the USB, and the undesired channel, T2 from LSB, have been co-located or imaged to the DC frequency location. Although, in Figs. 8 and 9, the input signals have been multiplied a signal with the same frequency, in Fig. 8 the signal is a sine signal and in Fig. 9 the signal is a cosine signal. Note that a similar operation exists for the lower point G at the output of multiplier 66 except that the desired channel is T15 and undesired channel is T2. Referring now to Fig. 10, a conceptual illustration of a signal at point H in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, at point H the two signals from upper points E and F, following an inversion or negation of the signal at F, are added together. The addition of these signals permits recovery of the channel T2 while removing the channel T15 that was co-located at the same position. The signal that is recovered is a magnitude projection of the in phase signal component of the channel T2. The recovered signal is the in phase or cosine magnitude projection of channel T2. Referring now to Fig. 11, a conceptual illustration of a signal at point J in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, at point J the two channels from upper points D and G are added together. The addition of these channels permits recovery of channel T2 while removing the channel T15 that was co- located at the same position. The signal that is recovered is a magnitude projection of the quadrature signal component of the channel T2. The recovered signal is the quadrature phase or sine magnitude projection of the channel T2.

The in phase and quadrature magnitude projections of the channel T2 are used in further downstream processing operations such as demodulation.

Referring now to Fig. 12, a conceptual illustration of a signal at point K in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, at point K the two channels from lower points E and F are added together. The addition of these channels permits recovery of channel T15 while removing the channel T2 that was co-located at the same position. The signal that is recovered is a magnitude projection of the quadrature signal component of the channel T15. The recovered signal is the quadrature phase or sine magnitude projection of channel T15.

Referring now to Fig. 13, a conceptual illustration of a channel at point L in the ADC processing arrangement 30 of Fig. 2 is shown. More specifically, at point L the two channels from lower points D and

G, following an inversion or negation of the channel at F, are added together. The addition of the channels permits recovery of channel T15 while removing the channel T2 that was co-located at the same position. The signal that is recovered is a magnitude projection of the in phase signal component of the channel T15. The recovered signal is the in phase or cosine magnitude projection of channel T15.

As previously noted in connection with the extraction of the signals for channel T2, the in phase and quadrature magnitude projections of channel T15 are used in further downstream processing such as demodulation.

It should be noted that the approach outlined above represents an image canceling technique through addition and subtraction of signals or channels that have been frequency translated with appropriate phase rotations.

Referring now to Fig. 14, an exemplary satellite receiver system 100 utilizing the ADC processing arrangement of the present invention is shown. More specifically, a signal, containing a number of physical channels, is provided from satellite transponders located on a satellite 102. A satellite dish 104 contains a reflector, a feed horn and a low noise block converter (LNB). The satellite signals are often located in the microwave frequency range, for instance 11-13 Gigahertz (GHz). The LNB in the satellite dish 104 amplifies and converts the satellite signal in the 11-13 GHz range to an L-band signal in the 1-2 GHz frequency range. The L-band signal at the output of the satellite dish 104 is provided to a set top box (STB) 106. STB 106 contains a multichannel satellite receiver 108 that is capable of simultaneously receiving and demodulating a plurality of channels from the L-band signal, using the ADC processing arrangement of the present invention, and supplying the signals to other circuits or devices. In an exemplary embodiment, multichannel satellite receiver 108 supplies two separate digital signals to hard disk drives (HDD) 110, 112. The multichannel satellite receiver 108 also supplies two analog audio and video signals to an external display device 114 such as a two input picture-in-picture (PIP) television. Other circuits necessary for operation of the STB such as a controller and user interface are not shown but are well known to those skilled in the art.

While the present invention has been described in terms of a preferred embodiment above, those skilled in the art will readily appreciate that numerous modifications, substitutions and additions may be made to the disclosed embodiment without departing from the spirit and scope of the present invention. It is intended that all such modifications, substitutions and additions fall within the scope of the present invention which is best defined by the claims below.

Claims

What is claimed is:

1. A method for recovering a datastream, said method comprising the steps of: receiving a plurality of analog signals within a range of frequencies, each received analog signal having a different frequency and containing a datastream; mixing (36, 38, 40) said plurality of analog signals with a mixing signal to generate a first set of analog signals and a second set of analog signals, said mixing signal (40) having a frequency that is within said range of frequencies and is not equal to said frequency of each received signal, said first and second set of analog signals each containing a portion of each datastream of each received analog signal; converting (46, 48) said first and second set of analog signals into a first and second set of digital signals; and processing (50) said first and second set of digital signals to generate a digital signal containing a datastream.

2. The method of claim 1 wherein said first and second sets of analog signals are first and second sets of complex analog signals.

3. The method of claim 1 wherein said first and second sets of digital signals contain all of the datastreams available in the received plurality of analog signals.

4. The method of claim 1 wherein the step of processing (50) further comprises: combining (52-82) said first and second set of digital signals to generate a digital signal containing a datastream.

5. The method of claim 1 wherein the plurality of received analog signals are satellite signals.

6. An apparatus for recovering a datastream, said apparatus comprising: a mixer (36, 38, 40) for mixing a plurality of received analog signals with a mixing signal to generate a first set of analog signals and a second set of analog signals, said plurality of received analog signals being within a range of frequencies, each received analog signal having a different frequency and containing a datastream, said mixing signal having a frequency that is within said range of frequencies and is not equal to said frequency of each received signal, said first and second set of analog signals each containing a portion of each datastream of each received analog signal; an analog to digital converter (46, 48) for converting said first and second set of analog signals into a first and second set of digital signals; and processing circuitry (50) for extracting a datastream from said first and second set of digital signals.

7. The apparatus of claim 6 wherein said first and second sets of analog signals are first and second sets of complex analog signals.

8. The apparatus of claim 6 wherein said first and second sets of digital signals contain all of the datastreams available in the received plurality of analog signals.

9. The apparatus of claim 6, wherein the processing circuitry (50) further comprises: mixing circuitry (52-66) for mixing a mixing signal with said first and second sets of digital signals, said mixing signal having a frequency that matches a frequency of a desired datastream and an undesired datastream in said first and second sets of digital signals; and combinational circuitry (72-78) for combining said mixed first and second sets of digital signals to cancel said undesired datastream and extract said desired datastream.

10. The apparatus of claim 6, wherein the plurality of received analog signals are satellite signals.

11. An apparatus for extracting a channel from a multi-channel signal, said apparatus comprising: means for receiving (32, 34) a plurality of analog signals within a range of frequencies, each received analog signal having a different frequency and containing a channel; means for mixing (36, 38, 40) said plurality of analog signals with a mixing signal to generate a first set of analog signals and a second set of analog signals, said mixing signal having a frequency that is within said range of frequencies and is not equal to said frequency of each received signal, said first and second set of analog signals each containing a portion of each channel of each received analog signal; means for converting (46, 48) said first and second set of analog signals into a first and second set of digital signals; and means for processing (50) said first and second set of digital signals to generate a digital signal containing a channel.

12. The apparatus of claim 11 wherein said first and second sets of analog signals are first and second sets of complex analog signals.

13. The apparatus of claim 11 wherein said first and second sets of digital signals contain all of the channels contained in the received plurality of analog signals.

14. The apparatus of claim 11 wherein the means for processing (50) further comprises: means for combining (52-82) said first and second set of digital signals to generate a digital signal containing a channel.

15. The apparatus of claim 11 wherein the plurality of received analog signals are satellite signals.