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WO2006035500A1 - Systeme de stockage de donnees et carte memoire - Google Patents

Systeme de stockage de donnees et carte memoire Download PDF

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Publication number
WO2006035500A1
WO2006035500A1 PCT/JP2004/014228 JP2004014228W WO2006035500A1 WO 2006035500 A1 WO2006035500 A1 WO 2006035500A1 JP 2004014228 W JP2004014228 W JP 2004014228W WO 2006035500 A1 WO2006035500 A1 WO 2006035500A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
target
bit
bits
storage system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2004/014228
Other languages
English (en)
Japanese (ja)
Inventor
Shinichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2006537602A priority Critical patent/JPWO2006035500A1/ja
Priority to PCT/JP2004/014228 priority patent/WO2006035500A1/fr
Publication of WO2006035500A1 publication Critical patent/WO2006035500A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a data storage system and a memory card, and in particular, is effective when applied to a data storage system including a storage device typified by a memory card and an initiator for reading and writing data to and from the storage device. It is about technology.
  • the following technologies can be considered as the data storage system.
  • various memory card standards such as SD (Secure Digital) memory card and Memory Stick (registered trademark), network type communication type such as USB (Universal Serial Bus) and IEEE (the Institute of Electrical and Electronics Engineers) 1394
  • Serial Bus Universal Serial Bus
  • IEEE the Institute of Electrical and Electronics Engineers 1394
  • FIG. 6 is a diagram for explaining an example of the data transfer system in the conventional data storage system examined as a premise of the present invention.
  • (A) is a simplified diagram of the system configuration
  • (b) is a diagram of the system configuration. It is an operation
  • the data transmission side is the initiator 60
  • the reception side is the target 61
  • the initiator 60 has a value of 5A'h (hexadecimal "5A", the same notation is used hereinafter) of the target 61.
  • the following processing (1) -1 (6) is performed.
  • the target 61 When the target 61 receives a write command from the initiator 60, the target 61 prays the content and extracts the write address and size.
  • the target 61 receives data A from the initiator 60.
  • the target 61 updates its corresponding memory space (here, 1 byte from address N) to data A.
  • an object of the present invention is to provide a data storage system and a memory card capable of improving the time efficiency when storing data.
  • Another object of the present invention is to provide a data storage system and a memory card that can save power when data is stored.
  • a data storage system includes: a second controller that transmits first data having different signal levels when data inversion is required and data holding is required; And a target for receiving the first data and updating the second data by inverting or holding the second data based on the signal level of the first data.
  • examples of the target include a storage device.
  • a data storage system includes an initiator that transmits data and a target that receives the transmitted data. Then, the initiator corresponds to the first signal level and the second signal level for the bit that needs to be inverted and the bit that does not need to be inverted for the second data of multiple bits stored in the target. The plurality of bits of the first data is formed, and the plurality of bits of the first data is transmitted to the target.
  • the target receives first data of a plurality of bits, detects a bit corresponding to the first signal level from the received first data of the plurality of bits, and detects the second data of the plurality of bits.
  • the storage of the second data is updated by inverting the bit data corresponding to the detected bit.
  • the bit data in the memory corresponding to that bit is inverted, and the data in the memory is updated.
  • a system software process is performed using a computer provided in the target, and the system software process is performed for each bit signal for a plurality of bits of first data. Only when the signal level of the determined bit and the determined signal level is the first signal level, the bit data corresponding to the determined bit is read from the second data of the plurality of bits, And the step of reversing the read data and writing it back.
  • the signal level of data received by the target is determined by processing of system software such as a device driver, and based on the determination result! Realize the function to control writing to the memory.
  • the memory card receives a command including a write address and data assigned with different signal levels corresponding to inversion or holding of data, from the initiator.
  • the data stored in the write address is updated by inverting or holding the data stored in the write address based on the signal level of the input data.
  • examples of the memory card include an SD memory card and an MMC card.
  • a new write command to a block or a plurality of blocks may be provided as the command by using a protocol similar to a write command to a block or a plurality of blocks generally provided in such a memory card.
  • Initiator power The time required to store data by transferring data with different signal levels depending on whether the data in the target memory or the like is inverted and held toward the target. Efficiency can be improved. In addition, it is possible to save power when storing data.
  • FIG. 1 is a system schematic diagram showing an example of the configuration of a data storage system according to an embodiment of the present invention.
  • FIG. 2 is a conceptual diagram for explaining a data transfer method between an initiator and a target in comparison with the prior art in the data storage system according to the embodiment of the present invention.
  • FIG. 3 is a diagram showing an example of the operation of the data storage system according to the embodiment of the present invention, where (a) is a simplified diagram of the system configuration and (b) is an operation flow diagram.
  • FIG. 4 In the data storage system according to the embodiment of the present invention, the system software processing of the target is compared between the case of using the conventional data transfer method and the case of using the data transfer method of the present invention.
  • (A) is an example of a processing flow when using the prior art
  • (b) is an example of a processing flow when using the present invention.
  • FIG. 5 is an explanatory diagram showing an example of a command specification of a memory card defined when a memory card is used as a target in the data storage system of one embodiment of the present invention
  • FIG. 6 is a diagram for explaining an example of the data transfer system in the prior art data storage system examined as a premise of the present invention, (a) is a simplified diagram of the system configuration, and (b) Is an operation flow diagram.
  • FIG. 1 is a system schematic diagram showing an example of the configuration of a data storage system according to an embodiment of the present invention.
  • the data storage system shown in FIG. 1 includes an initiator 10 that transmits data and a target 11 that receives data, and the initiator 10 and the target 11 are connected by a communication network 12.
  • Examples of the initiator 10 and the target 11 include a memory card host device, a USB device, or an IEEE 1394 device.
  • the initiator 10 and the target 11 have the same configuration, and include, for example, an application 13a, a file system 13b, a device driver 13c, an interface controller 13d, a memory and / or a register, and the like.
  • an application 13a a file system 13b
  • a device driver 13c an interface controller 13d
  • a memory and / or a register and the like.
  • the application 13a is software including, for example, an explorer having a function of operating folders and files, an audio player having a function of reproducing music data, and the like.
  • the file system 13b is system software that converts data input / output via the device driver 13c into a file so that processing can be performed by the application 13a, for example. Specific examples include those conforming to FAT (File Allocation Table) such as FAT16 and FAT32.
  • the device driver 13c is software that performs control of the interface controller 13d, management of transactions and command sequences, and the like.
  • the initiator 10 and the target 11 include, for example, a computer such as a microphone processor, and thereby the software as described above is executed.
  • the software described above may be configured with an OS including a file system, an application, and a device driver when the initiator 10 and the target 11 are PCs (Personal Computers) or the like.
  • the interface controller 13d is hardware that performs command transmission, response reception, data transmission / reception, and the like via the communication network 12 in which the initiator 10 and the target 11 are connected.
  • Examples of the communication network 12 include a wiring line to a memory card, a USB cable, an IEEE1394 cable, and the like, and data transfer is performed on the communication network 12 by an electrical signal.
  • the memory of the storage unit 13e stores, for example, files and data necessary for the system, and the register is used for specific purposes such as device operation control.
  • the data transfer between the initiator 10 and the target 11 is not necessarily performed using a wired communication network.
  • the interface controller 13d may be a wireless controller and the data may be transferred wirelessly. .
  • FIG. 2 shows a conventional technique for transferring data between an initiator and a target in a data storage system according to an embodiment of the present invention. It is a conceptual diagram for demonstrating compared with a technique.
  • the memory content on the target side is 5A′h
  • the memory content is updated to 5B′h by data transfer from the initiator to the target.
  • the initiator power is also transferred to the target as raw data (5B, M Binary "01011011") and overwritten and stored in the memory content B'h on the initiator side.
  • data indicating the presence / absence of update for each bit is transferred toward the target with the initiator power. That is, in Fig. 2, if '1' ('H, level) is set to the bit with update and' 0, ('L, level) is set to the bit without update, only the last bit is updated. Therefore, the data of 01'h is transferred. Then, the target side receives the data of 0 l 'h, inverts the data of the bit (here, the last bit) corresponding to the bit with the intermediate update of the data in its own memory and stores it again.
  • the data is considered as a bitmap image, and the bit updated (inverted) by data transfer is changed to “1”, and the bit holding the value as it is is changed to “0”. Then, data having bit information to be updated (inverted) is transferred to the target.
  • the following effects can be obtained.
  • Time to write and update received data is reduced, and this time can be allocated to other functions of the product (decoding multimedia data, etc.).
  • the present invention is not limited to this, and the present invention can be applied to all products in which the data to be transferred and the corresponding addresses of the memory Z register are associated one-to-one.
  • the system area of the file system is updated in units of sectors (512 bytes, etc.), and only a few bytes are updated, and the one-to-one correspondence described above is provided. ing. Therefore, the effect becomes large when applied to a product having such a file system.
  • FIG. 3 is a diagram showing an example of the operation of the data storage system according to the embodiment of the present invention.
  • (A) is a simplified diagram of the system configuration, and (b) is an operation flow diagram.
  • the target 31 When the target 31 receives the write command from the initiator 30, the target 31 prays the content and extracts the write address and size. (3) After extraction, the target 31 prepares to receive data from the initiator 30.
  • the target 31 receives the data A from the initiator 30.
  • the target 31 updates its corresponding memory to data A.
  • This data it is possible to use a method that inverts only the bits that need to be updated.
  • the data A 'itself contains information on the bits that need to be updated, so it is possible to use this updating method easily. become.
  • FIG. 4 shows the target system software processing in the data storage system according to the embodiment of the present invention when the conventional data transfer method is used and when the data transfer method of the present invention is used. It is a figure to compare, (a) is an example of the processing flow at the time of using a prior art, (b) is an example of the processing flow at the time of using this invention.
  • S405a the I-th bit of data N is taken out and is designated as N [I]. Then, control goes to S406a. [0066] In S406a, it is compared whether N [I] and A [I] are different from each other. If they are different, the process proceeds to S407a. Otherwise, the process proceeds to S408a.
  • the bit extraction counter determines whether or not the force is effective. If it is valid, the process proceeds to S409b, and if not, the process ends.
  • CMD60 DIFFERENTIAL—WRITE—BLOCK
  • CMD61 DIFFERENTIAL—WRITE—MULTIPLE—BLOCK
  • the write command protocol between the initiator and target using CMD60 and CMD61 is exactly the same as CMD24 and CMD25, respectively, and only the data contents are changed to those with bit inversion information.
  • the command formats of CMD60 and CMD61 are as shown in Fig. 5 (a) and (b), respectively.
  • FIGS. 5A and 5B are diagrams illustrating an example of command specifications of a memory card defined when a memory card is used as a target in the data storage system according to the embodiment of the present invention.
  • (A) shows the specification example of CMD60
  • (b) shows the specification example of CMD61.
  • the CMD60 is an adtc (addressed (point-to-point) data transfer commands) type command.
  • a command is issued to a specific memory card specified from the CMD line, and after this specific memory card returns a response, data is transferred to the memory card through the DAT line.
  • the memory card writes data for the block size specified by the SET-BLOCKLEN command from the address specified by the argument when issuing CMD60.
  • the data transferred to the memory card is data having bit inversion information as described above.
  • CMD61 is an adtc type command and It has become.
  • Data transfer from the host to the memory card causes the memory card to continuously write data from the address specified by the argument when issuing CMD61 until it is stopped by the STOP-TRANSMISION command. Multiple blocks are written.
  • the data transferred to the memory card is data having the bit inversion information as described above.
  • a new command is defined for a memory card such as an SD memory card or an MMC card, and a command determination function or a bit inversion information as described above is provided in the memory card as a function for responding to the command. It is possible to improve the data transfer efficiency of the memory card by providing a function for processing this.
  • the data storage system and the memory card of the present invention are applied to a data storage system including various memory cards such as an SD memory card and a memory stick, a USB flash memory, and so on, and a serial transfer storage device. It is particularly useful. Not only these, but also hard disks with ATA connection, memory-powered host devices such as SD audio, DVD drives connected with IEEE 1394, various storage devices, and storage media not limited to storage devices. It is widely applicable to data storage systems including various devices in which addresses and data are assigned one-to-one.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

Dans un cas explicatif de mise à jour du contenu de mémoire au niveau d’une extrémité cible, qui est dans ce cas, par exemple, de 5A'h à 5B'h par l’intermédiaire d’une émission de données d’un initiateur vers la cible, l’initiateur émet, vers la cible, des données de 01'h indiquant si une mise à jour doit être effectuée par bit (un bit à mettre à jour vaut « 1 » et un bit à ne pas mettre à jour vaut « 0 »). Lors de la réception des données de 01'h, la cible récupère, parmi les données de ses propres contenus de mémoire, et inverse les données du bit (dans ce cas, le dernier bit) correspondant à un bit à mettre à jour, et ensuite restaure les données telles qu’inversées.
PCT/JP2004/014228 2004-09-29 2004-09-29 Systeme de stockage de donnees et carte memoire Ceased WO2006035500A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006537602A JPWO2006035500A1 (ja) 2004-09-29 2004-09-29 データ記憶システムおよびメモリカード
PCT/JP2004/014228 WO2006035500A1 (fr) 2004-09-29 2004-09-29 Systeme de stockage de donnees et carte memoire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2004/014228 WO2006035500A1 (fr) 2004-09-29 2004-09-29 Systeme de stockage de donnees et carte memoire

Publications (1)

Publication Number Publication Date
WO2006035500A1 true WO2006035500A1 (fr) 2006-04-06

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PCT/JP2004/014228 Ceased WO2006035500A1 (fr) 2004-09-29 2004-09-29 Systeme de stockage de donnees et carte memoire

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WO (1) WO2006035500A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008527535A (ja) * 2005-01-13 2008-07-24 サムスン エレクトロニクス カンパニー リミテッド ホスト装置、携帯用保存装置、及び携帯用保存装置に保存された権利オブジェクトのメタ情報を更新する方法。

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002268941A (ja) * 2001-03-09 2002-09-20 Fujitsu Ltd 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05191454A (ja) * 1992-01-16 1993-07-30 Nec Corp データ転送方式
JP2002358222A (ja) * 2001-06-04 2002-12-13 Hitachi Ltd データ二重化システム及び方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002268941A (ja) * 2001-03-09 2002-09-20 Fujitsu Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008527535A (ja) * 2005-01-13 2008-07-24 サムスン エレクトロニクス カンパニー リミテッド ホスト装置、携帯用保存装置、及び携帯用保存装置に保存された権利オブジェクトのメタ情報を更新する方法。

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