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WO2006034355A3 - METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY - Google Patents

METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY Download PDF

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Publication number
WO2006034355A3
WO2006034355A3 PCT/US2005/033851 US2005033851W WO2006034355A3 WO 2006034355 A3 WO2006034355 A3 WO 2006034355A3 US 2005033851 W US2005033851 W US 2005033851W WO 2006034355 A3 WO2006034355 A3 WO 2006034355A3
Authority
WO
WIPO (PCT)
Prior art keywords
subcollector
metal silicide
refractory metal
hbt
isolation region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/033851
Other languages
French (fr)
Other versions
WO2006034355A2 (en
Inventor
Peter J Geiss
Peter B Gray
Alvin J Joseph
Qizhi Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to CN2005800316215A priority Critical patent/CN101432892B/en
Priority to EP05798479.1A priority patent/EP1794806B1/en
Priority to JP2007532649A priority patent/JP5090168B2/en
Publication of WO2006034355A2 publication Critical patent/WO2006034355A2/en
Anticipated expiration legal-status Critical
Publication of WO2006034355A3 publication Critical patent/WO2006034355A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate (12) including at least a subcollector (13); a buried refractory metal silicide layer (28) located on the subcollector; and a shallow trench isolation region (30) located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.
PCT/US2005/033851 2004-09-21 2005-09-20 METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY Ceased WO2006034355A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2005800316215A CN101432892B (en) 2004-09-21 2005-09-20 Method for forming collector in bipolar complementary metal oxide semiconductor technology
EP05798479.1A EP1794806B1 (en) 2004-09-21 2005-09-20 METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY
JP2007532649A JP5090168B2 (en) 2004-09-21 2005-09-20 Hetero bipolar transistor (HBT) and manufacturing method thereof (collector forming method in BiCMOS technology)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/711,479 US7002190B1 (en) 2004-09-21 2004-09-21 Method of collector formation in BiCMOS technology
US10/711,479 2004-09-21

Publications (2)

Publication Number Publication Date
WO2006034355A2 WO2006034355A2 (en) 2006-03-30
WO2006034355A3 true WO2006034355A3 (en) 2009-04-16

Family

ID=35810621

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/033851 Ceased WO2006034355A2 (en) 2004-09-21 2005-09-20 METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY

Country Status (7)

Country Link
US (2) US7002190B1 (en)
EP (1) EP1794806B1 (en)
JP (1) JP5090168B2 (en)
KR (1) KR100961738B1 (en)
CN (1) CN101432892B (en)
TW (1) TWI364795B (en)
WO (1) WO2006034355A2 (en)

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Publication number Priority date Publication date Assignee Title
TW200727367A (en) * 2005-04-22 2007-07-16 Icemos Technology Corp Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches
DE102005021932A1 (en) * 2005-05-12 2006-11-16 Atmel Germany Gmbh Method for producing integrated circuits
US8435873B2 (en) * 2006-06-08 2013-05-07 Texas Instruments Incorporated Unguarded Schottky barrier diodes with dielectric underetch at silicide interface
WO2008013255A1 (en) 2006-07-28 2008-01-31 Shimadzu Corporation Radiographic apparatus
US7709338B2 (en) * 2006-12-21 2010-05-04 International Business Machines Corporation BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices
US20090072355A1 (en) * 2007-09-17 2009-03-19 International Business Machines Corporation Dual shallow trench isolation structure
JP2009099815A (en) * 2007-10-18 2009-05-07 Toshiba Corp Manufacturing method of semiconductor device
US9059196B2 (en) 2013-11-04 2015-06-16 International Business Machines Corporation Bipolar junction transistors with self-aligned terminals
US9570564B2 (en) 2014-08-05 2017-02-14 Globalfoundries Inc. Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
CN108110051B (en) * 2017-12-19 2019-11-12 上海华力微电子有限公司 A bipolar transistor with trench structure and its manufacturing method
US11640975B2 (en) 2021-06-17 2023-05-02 Nxp Usa, Inc. Silicided collector structure

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US20050250289A1 (en) * 2002-10-30 2005-11-10 Babcock Jeffrey A Control of dopant diffusion from buried layers in bipolar integrated circuits

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US4589193A (en) * 1984-06-29 1986-05-20 International Business Machines Corporation Metal silicide channel stoppers for integrated circuits and method for making the same
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US4949151A (en) 1986-09-24 1990-08-14 Hitachi, Ltd. Bipolar transistor having side wall base and collector contacts
JPS63278347A (en) * 1987-05-11 1988-11-16 Toshiba Corp Semiconductor device and manufacture thereof
EP0306213A3 (en) * 1987-09-02 1990-05-30 AT&T Corp. Submicron bipolar transistor with edge contacts
JPH01146361A (en) * 1987-12-02 1989-06-08 Fujitsu Ltd Semiconductor device
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US20050250289A1 (en) * 2002-10-30 2005-11-10 Babcock Jeffrey A Control of dopant diffusion from buried layers in bipolar integrated circuits

Also Published As

Publication number Publication date
TWI364795B (en) 2012-05-21
JP2008514018A (en) 2008-05-01
JP5090168B2 (en) 2012-12-05
KR20070053280A (en) 2007-05-23
EP1794806A2 (en) 2007-06-13
US7002190B1 (en) 2006-02-21
CN101432892B (en) 2010-08-25
CN101432892A (en) 2009-05-13
EP1794806A4 (en) 2011-06-29
US7491985B2 (en) 2009-02-17
TW200614383A (en) 2006-05-01
WO2006034355A2 (en) 2006-03-30
EP1794806B1 (en) 2014-07-02
US20060124964A1 (en) 2006-06-15
KR100961738B1 (en) 2010-06-10

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