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WO2006015350A2 - Module de ports pour adaptateur de cable - Google Patents

Module de ports pour adaptateur de cable Download PDF

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Publication number
WO2006015350A2
WO2006015350A2 PCT/US2005/027360 US2005027360W WO2006015350A2 WO 2006015350 A2 WO2006015350 A2 WO 2006015350A2 US 2005027360 W US2005027360 W US 2005027360W WO 2006015350 A2 WO2006015350 A2 WO 2006015350A2
Authority
WO
WIPO (PCT)
Prior art keywords
communication
port module
module
port
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/027360
Other languages
English (en)
Other versions
WO2006015350A3 (fr
Inventor
David Gellerman
Tilman Foust
Vernon May
George R. Bailey
Richard Stillwell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spirent Communications of Rockville Inc
Original Assignee
Spirent Communications of Rockville Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/938,948 external-priority patent/US20060034180A1/en
Application filed by Spirent Communications of Rockville Inc filed Critical Spirent Communications of Rockville Inc
Publication of WO2006015350A2 publication Critical patent/WO2006015350A2/fr
Publication of WO2006015350A3 publication Critical patent/WO2006015350A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
    • H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
    • H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
    • H04M3/302—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop using modulation techniques for copper pairs
    • H04M3/304—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop using modulation techniques for copper pairs and using xDSL modems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • H04M11/062—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors using different frequency bands for speech and other data

Definitions

  • the present invention relates to communication circuit testing equipment. More particularly, the present invention relates to a system and method for providing test access to communication circuits associated with a network device.
  • an apparatus for providing test access to communication circuits associated with a network device includes a first plurality of ports.
  • the first plurality of ports are configured to couple the apparatus to the network device.
  • the apparatus includes a second plurality of ports.
  • the second plurality of ports are configured to couple the apparatus to a connection means.
  • the apparatus includes a selector matrix module in communication with the first and second plurality of ports.
  • the selector matrix module is configured to switch signals between the network device and the connection means.
  • the apparatus includes a controller module in communication with the selector matrix module.
  • the apparatus is configured to receive power signals over a communication link for powering the apparatus.
  • the controller module is configured to modulate the power signals over the communication link to communicate information signals for testing the communication circuits.
  • the apparatus can include an interface module in communication with the controller module and the communication link for receiving the power signals and for communicating the information signals from the apparatus.
  • the apparatus can include a system controller.
  • the system controller can be coupled between the apparatus and the at least one test module.
  • the system controller can provide the power signals to the apparatus over the communication link.
  • An information signal communicated between the system controller and the apparatus can comprise a transmission frame.
  • the transmission frame can comprise, for example, at least a command field, an address field, a visual indicator field, a communication circuit identifier field, an access mode field, an error detection/correction field, an event timing field and an apparatus response field.
  • the information signal communicated between the system controller and the apparatus can comprise a start of transmission frame flag.
  • the system controller can include a power controller and communication interface module for providing power to the apparatus and for modulating the power signals to communicate the information signals to the apparatus.
  • the system controller can include a test bus matrix module for connecting one of the at least one test device to the apparatus.
  • the information signals received over the communication link can comprise pulse-width modulated power signals.
  • the controller module can be configured to generate a signal for increasing a current load on the power signals received by the apparatus to modulate the information signals for transmission from the apparatus.
  • the controller module can comprise a programmable logic device.
  • the apparatus can include a connector module for providing programmable access control to the programmable logic device.
  • the apparatus can include a power converter module for converting the modulated power signals to supply power to the apparatus.
  • the apparatus can include an access mode selection module for selecting one of a plurality of access modes of the apparatus.
  • the plurality of access modes can comprise a split access mode, an AC monitor access mode and a DC monitor access mode.
  • the apparatus can include a circuit protection module for protecting the apparatus from power transients.
  • the apparatus can also include a monitor transformer.
  • the network device can comprise a digital subscriber line access multiplexer (DSLAM), and the connection means can couple the apparatus through a main distribution frame towards an end user.
  • DSLAM digital subscriber line access multiplexer
  • a system for providing test access to communication circuits associated with network devices includes at least one port module.
  • Each port module includes at least one of a first port configured to connect the port module to a network device.
  • Each port module includes at least one of a second port configured to connect the port module to a connection means.
  • Each port module includes a selector matrix circuit in communication with the first and second ports configured to switch signals between the network device and the connection means.
  • Each port module includes a port module controller in communication with the selector matrix circuit.
  • the system includes a system controller in communication with at least one test device and each port module. The system controller is configured to provide power signals to each port module over a respective communication link and for modulating the power signals to communicate information signals to each port module for testing the communication circuits.
  • each port module can include an interface circuit in communication with the port module controller and a communication link for receiving the power signals and for communicating the information signals from the port module.
  • An information signal communicated between the system controller and each port module can comprise a transmission frame.
  • the transmission frame can comprise at least a command field, an address field, a visual indicator field, a communication circuit identifier field, an access mode field, an error detection/correction field, an event timing field and a port module response field.
  • the information signal communicated between the system controller and each port module can comprise a start of transmission frame flag.
  • the system controller can comprise a test device matrix circuit for connecting one of the at least one test device to a port module.
  • the information signals communicated over the communication link by the system controller can comprise pulse-width modulated power signals.
  • the port module controller can be configured to generate a signal for increasing a current load on the power signals received from the system controller over the communication link to modulate the information signals for transmission to the system controller.
  • the port module controller of each port module can comprise a programmable logic device.
  • Each port module can comprise a connector circuit for providing programmable access control to the programmable logic device.
  • each port module can comprise a power converter for converting the modulated power signals received from the system controller to supply power to the port module.
  • Each port module can comprise an access mode selector for selecting one of a plurality of access modes of the port module.
  • the plurality of access modes can comprise a split access mode, an AC monitor access mode and a DC monitor access mode.
  • Each port module can comprise a circuit protector for protecting the port module from power transients.
  • Each port module can comprise a monitor transformer.
  • the network devices can comprise DSLAMs, and the connection means of each port module can couple the port module through a main distribution frame towards an end user.
  • an apparatus for providing test access to communication circuits associated with a network device includes a first plurality of port means for coupling the apparatus to the network device.
  • the apparatus includes a second plurality of port means for coupling the apparatus to a connection means.
  • the apparatus includes a selector means in communication with the first and second plurality of port means for switching signals between the network device and the connection means.
  • the apparatus includes a controller means in communication with the selector means for controlling the apparatus.
  • the apparatus is configured to receive power signals over a communication link for powering the apparatus.
  • the controller means is configured to modulate the power signals over the communication link to communicate information signals for testing the communication circuits.
  • the apparatus can include an interface means in communication with the controller means and the communication link for receiving the power signals and for communicating the information signals from the apparatus.
  • the apparatus can include a system controller means for providing the power signals to the apparatus over the communication link.
  • the system controller module is coupled between the apparatus and the at least one test means.
  • An information signal communicated between the system controller means and the apparatus can comprise a transmission frame.
  • the transmission frame can comprise at least a command field, an address field, a visual indicator field, a communication circuit identifier field, an access mode field, an error detection/correction field, an event timing field and a port module response field.
  • the information signal communicated between the system controller means and the apparatus can comprise a start of transmission frame flag.
  • the system controller means can comprise a power controller and communication interface means for providing power to the apparatus and for modulating the power signals to communicate the information signals to the apparatus.
  • the system controller means can comprise a test bus selector means for connecting one of the at least one test means to the apparatus.
  • the information signals received over the communication link can comprise pulse-width modulated power signals.
  • the controller means can be configured to generate a signal for increasing a current load on the power signals received by the apparatus to modulate the information signals for transmission from the apparatus.
  • the controller means can comprise a programmable logic means.
  • the apparatus can include a connector means for providing programmable access control to the programmable logic means.
  • the apparatus can include a power converter means for converting the modulated power signals to supply power to the apparatus.
  • the apparatus can include an access mode selection means for selecting one of a plurality of access modes of the apparatus.
  • the plurality of access modes can comprise a split access mode, an AC monitor access mode and a DC monitor access mode.
  • the apparatus can include a circuit protection means for protecting the apparatus from power transients.
  • the apparatus can include a monitor means for performing an AC monitor of the apparatus.
  • the network device can comprise a DSLAM, and the connection means of each port module can couple the port module through a main distribution frame towards an end user.
  • a system for providing test access to communication circuits associated with network devices includes at least one port module means.
  • Each port module means includes at least one of first port means for coupling the port module means to a network device.
  • Each port module means includes at least one of second port means for coupling the apparatus to a connection means.
  • Each port module means includes a selector means in communication with the first and second port means for switching signals between the network device and the connection means.
  • Each port module means includes a port module controller means in communication with the selector means for controlling the port module means.
  • the system includes a system controller means in communication with at least one test means and each port module means for providing power signals to each port module means over a respective communication link and for modulating the power signals to communicate information signals to each port module means for testing the communication circuits.
  • each port module means can include an interface means in communication with the port module controller means and a communication link for receiving the power signals and for communicating the information signals from the port module means.
  • An information signal communicated between the system controller means and each port module means can comprise a transmission frame.
  • the transmission frame can comprise at least a command field, an address field, a visual indicator field, a communication circuit identifier field, an access mode field, an error detection/correction field, an event timing field and an apparatus response field.
  • the information signal communicated between the system controller means and each port module means can comprise a start of transmission frame flag.
  • the system controller means can comprise a test selector means for connecting one of the at least one test means to a port module means.
  • the information signals communicated over the communication link by the system controller means can comprise pulse-width modulated power signals.
  • the port module controller means can be configured to generate a signal for increasing a current load on the power signals received from the system controller means to modulate the information signals for transmission to the system controller means.
  • each port module controller means can comprise a programmable logic means.
  • Each port module means can comprise a connector means for providing programmable access control to the programmable logic means.
  • Each port module means can comprise a power converter means for converting the modulated power signals received from the system controller means to supply power to the port module means.
  • Each port module means can comprise an access mode selector means for selecting one of a plurality of access modes of the port module means. The plurality of access modes can comprise a split access mode, an AC monitor access mode and a DC monitor access mode.
  • Each port module means can comprise a circuit protection means for protecting the port module means from power transients.
  • Each port module means can comprise a monitor means for performing an AC monitor of the port module means.
  • a method of providing test access to communication circuits associated with a network device includes the steps of: a.) connecting an apparatus to the network device; b.) connecting the apparatus to a connection means; c.) switching signals between the network device and the connection means via the apparatus; d.) receiving power signals at the apparatus over a communication link to power the apparatus; and e.) modulating the power signals over the communication link to communicate information signals for testing the communication circuits.
  • an information signal can comprise a transmission frame.
  • the transmission frame can comprise at least a command field, an address field, a visual identifier field, a communication circuit number field, an access mode field, a error detection/correction field, an event timing field and an apparatus response field.
  • the information signal can comprise a start of transmission frame flag.
  • the method can include the step of: f.) coupling one of the at least one test device to the apparatus.
  • the information signals received over the communication link can comprise pulse-width modulated power signals.
  • the method can include the steps of: g.) generating a signal for increasing a current load on the power signals received at the apparatus to modulate the information signals for transmission from the apparatus; h.) converting the modulated power signals to supply power to the apparatus; and i.) selecting one of a plurality of access modes of the apparatus.
  • the plurality of access modes can comprise a split access mode, an AC monitor access mode and a DC monitor access mode.
  • the method can include the step of: j.) protecting the apparatus from power transients.
  • the network device can comprise a DSLAM, and the connection means of each port module can couple the port module through a main distribution frame towards an end user.
  • a port module for providing test access to communication circuits associated with a network element includes at least one of a first port. Each first port is configured to couple the port module to the network element.
  • the port module includes at least one of a second port. Each second port is configured to couple the port module to a connection means.
  • the port module includes a selector matrix circuit in communication with the first and second ports. The selector matrix module is configured to switch signals between the network element and the connection means.
  • the port module includes a controller circuit in communication with the selector matrix circuit.
  • the port module is configured to receive power signals over a communication link for powering the port module.
  • the controller circuit is configured to modulate the power signals over the communication link to communicate information signals for testing the communication circuits.
  • FIG. 1 is a diagram illustrating a system for providing test access to communication circuits associated with a network device, in accordance with an exemplary embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an access point relay matrix for supporting up to ninety-six two-wire communication circuits, in accordance with an exemplary embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a circuit for generating row and column control line signals of the access point relay matrix, in accordance with an exemplary embodiment of the present invention.
  • FIGS. 4 A and 4B are diagrams illustrating exemplary circuit designs for high-side and low-side relay drivers, respectively, used by a port module, in accordance with an exemplary embodiment of the present invention.
  • FIG. 5 is a diagram illustrating an exemplary 32-bit transmission frame, in accordance with an exemplary embodiment of the present invention.
  • FIG. 6 is a timing diagram illustrating the timing of the communication of transmission frames, in accordance with an exemplary embodiment of the present invention
  • FIG. 7 is a flowchart illustrating steps for providing test access to communication circuits associated with a network device, in accordance with an exemplary embodiment of the present invention.
  • Exemplary embodiments of the present invention are directed to a system and method for providing test access to communication circuits associated with a network device.
  • a Cable Adapter Port Module (CAPM) and an associated system controller can be used as a metallic access device for Digital Subscriber Loop (DSL) circuits and the like.
  • DSL Digital Subscriber Loop
  • the CAPM can use an in-line design that does not extend beyond the width and height of the existing cabling and cable connector volume allowance of the DSLAM.
  • the CAPM can be connected between the DSLAM and, for example, the DF as a type of cable connector or interconnection.
  • the CAPM is configured to provide test access to the communication circuits with minimal space and cabling requirements.
  • the CAPM receives power signals from an associated system controller over a communication link.
  • the system controller is also connected to one or more test equipment devices for testing the communication circuits.
  • the CAPM and system controller communicate information signals between each other over the communication link by modulating the power signals.
  • the communication circuits can then be tested by passing test signals, command signals and other information signals from the test equipment through the system controller and the CAPM (and on to the network equipment and communication circuits) by modulating the power signals passed between the system controller and the CAPM. Consequently, the CAPM can provide test access to communication circuits without taking any rack space and without incurring any communication circuit cable or cable routing costs.
  • a "communication circuit” can be any suitable type of communication circuit, such as, for example, POTS (Plain Old Telephone Service) or any of the different variants of DSL technologies for transmitting high-bandwidth information over twisted-pair (i.e., copper wire) telephone lines, including, for example, ADSL, including ADSL2, ADSL2+ and ADSL2++, ADL ADSL, SDSL, HDSL, VDSL, VDSL2, RADSL, UDSL, CDSL, G.Lite or DSL Lite, IDSL, and any other variant of DSL (such as, for example, EC-ADSL, SHDSL, ESHDSL, 1 OMDSL, IOOMDSL (DSM), M2DSL, BDSL, READSL (LDSL), ReachDSL and MMDSL), all collectively referred to as "xDSL.”
  • the port module 105 includes a first plurality of ports 110.
  • the first plurality of ports 110 is configured to couple the port module 105 to a network device 112 (referred to herein as the "equipment side").
  • the port module 105 also includes a second plurality of ports 115.
  • the second plurality of ports 115 is configured to couple the port module 105 to a connection means 117(referred to herein as the "facility side").
  • Any suitable type of electrical connection or connector can be used for the first and second plurality of ports 110 and 115.
  • the first plurality of ports 110 can be comprised of four 25-pair (male) CHAMP-type connectors, three 32-pair (male) CHAMP-type connectors, or any other suitable type of electrical connections.
  • the second plurality of ports 115 can be comprised of four 25-pair (female) CHAMP-type connectors, three 32-pair (female) CHAMP-type connectors, or any other suitable type of electrical connections.
  • Each of the first and second plurality of ports 110, 115 can be comprised of any number of ports.
  • the port module 105 includes a selector matrix circuit 120 in communication with the first and second plurality of ports 110, 115.
  • the selector matrix circuit 120 is configured to switch signals between the network device 1 12 and the connection means 117.
  • the port module 105 also includes a controller circuit 125 in communication with selector matrix circuit 120.
  • the controller circuit 125 can be comprised of, for example, a programmable logic device (PLD), such as, for example, an Altera 3128 CPLD or the like.
  • PLD programmable logic device
  • the controller circuit 125 can be used for all interface, control, timing and memory functions of the port module 105, including reception and interpretation of commands, and to set the mode selection and access relays accordingly.
  • the port module 105 can include a connector circuit 127, such as a standard JTAG connector or the like, for providing access to in-circuit programming functions of the controller circuit 125.
  • the port module 105 is configured to receive power signals over a communication link portion of a system link 130 for powering the port module 105. Additionally, the controller circuit 125 is configured to modulate the power signals over the communication link portion of the system link 130 to facilitate communication of information signals for purposes of testing the communication circuits.
  • the port module 105 uses a matrix scheme for activating the communication circuit selection relays.
  • FIG. 2 is a diagram illustrating an access point relay matrix 200 for supporting up to ninety-six two-wire communication circuits, in accordance with an exemplary embodiment of the present invention.
  • the matrix 200 can be arranged in a 8 x 12 pattern.
  • the row control lines 205 of the matrix 200 can be generated by a high-side driver 210 (e.g., P-channel FET or the like) and can connect to the positive side of the relay coils.
  • a high-side driver 210 e.g., P-channel FET or the like
  • the column control lines 215 of the matrix 200 can be generated by a low-side driver 220 (e.g., a ULN2803 Darlington pair or the like) and can connect to the negative side of the relay coils. Activating a single row control line 205 and a single column control line 215 simultaneously can access a selected communication circuit.
  • a low-side driver 220 e.g., a ULN2803 Darlington pair or the like
  • FIG. 3 is a diagram illustrating a circuit 300 for generating the row and column control line 205 and 215 signals of the matrix 200, in accordance with an exemplary embodiment of the present invention.
  • the address of the communication circuit to be accessed i.e., communication circuit 1-96
  • the communication circuit address number can be reduced by one using a subtraction element 310 in communication with the register 305, giving a resultant circuit number of 0 to 95 (i.e., 000 0000 through 101 1111 in binary).
  • the resulting circuit number can be applied to a 7-bit matrix register 315 in communication with the subtraction element 310.
  • the lowest three bits of the resulting circuit number can be used to select the active column, using a 3 x 8 decoder 320 in communication with the register 315.
  • the upper four bits of the resulting circuit number can be used to select the row, using a 4 x 16 decoder 325 also in communication with register 315 (the upper four bits of the decoder 325 can remain unused).
  • a special case can exist if the active communication circuit number is zero. Such a case signifies that no communication circuit access is currently being performed.
  • a zero detector 330 in communication with the register 305 and the decoders 320, 325, detects that the communication circuit number is zero, then the zero detector 330 can send an appropriate signal to the decoders 320, 325 to hold the decoders 320, 325 in reset so that no communication circuit relays are asserted.
  • FIGS. 4A and 4B are diagrams illustrating exemplary circuit designs for the high-side and low-side relay drivers 405 and 450, respectively, used by the port module 105, in accordance with an exemplary embodiment of the present invention.
  • a row enable signal 407 is applied to the gate of a first N-channel MOSFET transistor 410, having its source coupled to a reference voltage (e.g., ground) and its source and drain connected across a first internal diode 412.
  • the drain of first transistor 410 is in communication with a voltage source 415 (e.g., +12V DC supplied via the communication link portion of system link 130) through a first resistor 420 (e.g., 100 k ⁇ ).
  • the drain of first transistor 410 is also in communication with the gate of a second P-channel MOSFET transistor 425 through a second resistor 430 (e.g., 10 k ⁇ ).
  • the drain of the second transistor 425 is in communication with the voltage source 415.
  • a capacitor 435 e.g., 0.1 ⁇ F is in communication between the gate and drain of the second transistor 425.
  • the source of the second transistor 425 (which is also connected to its drain across a second internal diode 427) provides the row control signal 440.
  • a column enable signal 455 is applied across a first resistor 460 (e.g., 2.7 k ⁇ ) to the base of a first NPN transistor 465.
  • the collector of first NPN transistor 465 is connected to the voltage source 415 through a diode 467.
  • the base of first NPN transistor 465 is connected to its emitter through a second resistor 470 (e.g., 7.2 kO), which is in turn in communication with the base of a second NPN transistor 475.
  • the base and the emitter of the second NPN transistor 475 are connected through a third resistor 480 (e.g., 3.0 k ⁇ ), along with the emitter, to a reference voltage (e.g., a ground).
  • the collector of the second NPN transistor 475 is in communication with the collector of the first NPN transistor 465 and the voltage source 415, so as to form, for example, a Darlington pair.
  • the outputs of the collectors of the first and second NPN transistors 465, 475 provide the column control signal 485.
  • Other configurations of the high-side and low-side relay drivers 405 and 450 are possible, as other components and other suitable values of the components can be used.
  • the low-side should be deactivated before the high-side, when releasing a circuit access.
  • An RC circuit can be used on the gate of the P-channel FET of the high-side driver to facilitate this ordering of release should power be removed totally.
  • the port module 105 includes an interface circuit 135 in communication with the controller circuit 125 and the system link 130 for receiving the power signals and for communicating the information signals from the port module 105.
  • the interface circuit 135 can comprise a single jack of the type used for RJ-45 service or the like, with a single-shielded, CAT 5 Ethernet patch cable (8-conductor) or the like used for the system link 130.
  • the system link 130 can include the leads for the test circuit pairs, as well as the port module's 105 external power supply and ground connections.
  • the power supply to the port module 105 over the communication link portion of system link 130 also acts as the information communication medium.
  • Ethernet cable includes eight conductors, only six conductors are needed according to an exemplary embodiment.
  • two conductors can each be paralleled with an additional conductor to effectively form two lower-resistance conductors, thereby permitting an extended system link 130.
  • These two lower-resistance conductors can be utilized to transport the commingled power and information signals.
  • the four remaining conductors can be used as two pairs to present the network device 112 selected pair, and simultaneously, but separately, present the corresponding connection means 117 pair, to a test device 133.
  • the interface circuit 135 can include, for example, accommodations for two LEDs embedded in the system link 130 jack or other suitable type of visual indicators, such as, for example, a green LED for power indication and a yellow LED for a test access indicator.
  • the port module 105 can support a single test access of any of the ninety-six communication circuits, as one of the ninety-six communication circuits can be accessed at any one time. The remaining ninety-five communication circuits can be blocked from access until the current access is discontinued. However, on a system basis, any number of communication circuits can be supported, with any number of accesses supported at any time.
  • the port module 105 can include an access mode selector circuit 140 for selecting one of a plurality of access modes of the port module 105.
  • the access mode selector circuit 140 is in communication with the controller circuit 125 and the interface circuit 135.
  • the access mode selector circuit 140 is also in communication with the selector matrix circuit 120.
  • the test circuit pairs can be protected through a protection circuit to protect down-stream test devices from potentially damaging over- currents and over- voltages. For example, a 1.25 A fuse can be inserted in each lead of the facility access pair, and a 320V surge absorber can be connected across the pair. Other configurations for the protection circuit can be used.
  • Port module 105 can support several access modes. In an idle (no access) mode, all communication circuits are passed through the port module 105, connecting the first plurality of ports 110 with the second plurality of ports 115. This state can be maintained while the port module 105 is powered down. In a DC monitor access mode, the front-end relays can be activated, while the selected communication circuit continuity can be maintained via the monitor relays on the side of the first plurality of ports 110 (i.e., the equipment side). The tapped communication circuit pair can be routed to the interface circuit 135. Build-out resistors can be inserted in the test access pair to support a DC monitor access mode with reasonable isolation.
  • a monitor transformer included in a monitor access circuit 145 can be inserted into the communication circuit under test.
  • the accessed communication circuit can be routed from the second plurality of ports 115 (the facility side), through the monitor access circuit 145, then back to the first plurality of ports 110 (the equipment side).
  • the monitor circuit can generate an independent signal from the test circuit, and the signal can be routed to the interface circuit 135.
  • a split access mode both pairs of the communication circuit (from the first and second plurality of ports 110, 115) are routed to the interface circuit 135.
  • the split access mode if circuit continuity is required, it can then be supplied by the appropriate test device 133.
  • other monitor access modes can be supported by the port module 105, such as that described in commonly-assigned U.S. patent application serial no. 10/632, 901, entitled “System and Method for Hitless Monitoring Access of A Communication Circuit," filed August 4, 2003.
  • the port module 105 can include a circuit protection circuit 150 in communication with the interface circuit 135 for protecting the port module 105 from power transients.
  • the port module 105 receives its power from a power signal received over the communication link portion of the system link 130.
  • the port module 105 can receive a +12V DC supply signal over the communication link portion of the system link 130, although any suitable supply voltage can be received, depending on the power requirements of the port module 105.
  • the circuit protection circuit 150 can provide polarity protection of the power signal, which can be limited with an internal 750 mA fuse or the like, and filtered with a series inductor of appropriate inductance to protect the port module 105 from voltage transients.
  • the controller circuit 125 is in communication with the circuit protection circuit 150 for communicating information signals modulated on the power signals transmitted over the communication link portion of the system link 130.
  • the port module 105 can include a power converter circuit 155 for converting the modulated power signals received on the interface circuit 135 to power suitable to supply the power needs of the port module 105.
  • the port module 105 can use a +12V DC power supply to power, for example, the test bus relays. However, a lower supply voltage may be needed for other components of the port module 105.
  • the controller circuit 125 and buffers used in the port module 105, can require a lower voltage 3.3V supply.
  • the power converter circuit 155 can include action as a linear regulator to convert the 12V power signal to a 3.3V power signal.
  • the power converter circuit 155 can regulate the power signal to any desired lower level signal, depending on the power requirements of the port module 105 and its components.
  • the system 100 includes a system controller 160 coupled to each of the port modules 105 via the communication link portion of the respective system links 130, and coupled to the test devices 133.
  • the system controller 160 provides or otherwise supplies the power signals to the port modules 105 over the communication link portion of the respective system links 130.
  • the system controller 160 can be powered from a single power supply 162 (e.g., a - 48 V source) received on power input 163.
  • the voltage feeds to the system controller 160 can be polarity protected, over-voltage protected by a varistor (e.g., a 82 V varistor), and over-current protected with an on-board fuse (e.g., a IA fuse).
  • a varistor e.g., a 82 V varistor
  • an on-board fuse e.g., a IA fuse
  • the system controller 160 can also include suitable voltage converters or regulators for converting the voltage received on the power supply 162 to the appropriate level(s) for use by the system controller 160 (e.g., +3.3 V DC and the like) and for distribution to the port modules 105 (e.g., +12 V DC).
  • port modules 105 can be powered down when not in use to conserve system resources, while port modules 105 with active tests can have power supplied to them. In the powered down state, a port module 105 can be electrically passive, thereby conforming in this mode, by default, to, for example, mandated Electromagnetic Compatibility (EMC) requirements. The port module 105 can remain powered down until an access within the address space of the port module 105 is requested.
  • EMC Electromagnetic Compatibility
  • the system controller 160 includes a power controller and communication interface circuit 165 for providing power to each of the port modules 105 and for modulating the power signals to communicate the information signals to each of the port modules 105.
  • communication between the system controller 160 and a port module 105, and supply of the power signals from the system controller 160 to the port module 105 is conducted using a single communication link within the system link 130.
  • An information signal communicated between the system controller 160 and the port module 105 can comprise a transmission frame and a start of transmission frame flag. The start of transmission frame flag can be used to reset the input registers and counters of the port module 105 prior to reception of a transmission frame.
  • FIG. 5 is a diagram illustrating an exemplary 32-bit transmission frame 500, in accordance with an exemplary embodiment of the present invention.
  • the first four bits of the transmission frame 500 can comprise a command field 505, such as, for example, read and write commands. Commands that can be supported include, for example, "write registers" (1001), "read registers” (0101), and "read assembly information" (0110), while all other combinations can be either invalid or used to support additional suitable commands.
  • the next four bits of the transmission frame 500 can comprise a differentiating address field 510 for port modules 105 arranged in a daisy-chain.
  • the next bit of the transmission frame 500 can comprise a visual indicator field 515 to produce a visual indication in the port module 105, such as to turn on or off an LED or the like in the interface circuit 135.
  • a "0" in the visual indicator field 515 can cause a LED to turn off, while a "1" can cause a LED to turn on.
  • the next seven bits of the transmission frame 500 can comprise a communication circuit number field 520.
  • bit values 0000001 to 1100000 can be used to represent each of communication circuits 1 to 96
  • 0000000 can be used to represent a "no access”
  • 1100001 to 1111111 can be invalid or reserved for future use.
  • the range of bit values used for representing the communication circuits will change, depending on the number of actual communication circuits.
  • the next four bits of the transmission frame 500 can comprise an access mode field 525.
  • a "xlxx” can represent a monitor access mode enable
  • a "xxlx” can represent a monitor transformer access mode enable
  • a "xxxl” can represent a build-out resistor access mode enable (where a "x” is a "don't care” and "lxxx” is unused).
  • the access mode field 525 will vary, depending on the number and types of access modes available for a particular port module 105.
  • the next four bits of the transmission frame 500 can comprise an error detection/correction field 530.
  • the error detection/correction field 530 can comprise a checksum of twenty bits of the transmission frame 500 on a write command, or twelve bits of the transmission frame 500 on a read command.
  • the error detection/correction field 530 can comprise any suitable checksum, cyclic redundancy code (CRC) or the like.
  • the command and address fields 505 and 510 can be generated by the system controller 160 (i.e., always information bits toward the port module 105).
  • the system controller 160 can send control data to the port module 105.
  • the visual indicator field 515, communication circuit number field 520, access mode field 525, and error detection/correction field 530 can be sent toward the port module 105.
  • the port module 105 can dump its current control data to the system controller 160.
  • the visual indicator field 515, communication circuit number field 520, access mode field 525, and error detection/correction field 530 can be output from the port module 105 toward the system controller 160.
  • the next four bits of the transmission frame 500 can comprise an event timing field 535.
  • the event timing signals can be generated by transitions on the communication link portion of the system link 130. These event timing signals can be asserted by the port module 105 in the write mode transactions for command verification and register assertion (although no data is asserted to the output registers until the checksum is verified). For example, event timing signal one can represent that the checksum has been verified and the port module 105 response has been loaded. Event timing signal two can represent that the visual indicator (e.g., LED) and access modes and tree relays have been asserted. Event timing signal three can represent that a communication circuit access relay has been asserted. Event timing signal four can represent that no action is being taken. Any four values of the bits of event timing field 535 can be used to represent each of the event timing signals. Additional or alternative event timing signals can be used for event timing field 535, depending on, for example, the commands used to control the port module 105.
  • the remaining four bits of the transmission frame 500 can comprise a port module response field 540.
  • the port module response field 540 is sent by the port module 105 to the system controller 160. For example, if a write operation has occurred, a "1010" response can be sent by the port module 105 to indicate that a write command has been completed (and that the error detection/correction field 530 was verified). A “1100” response can be sent by the port module 105 to indicate that a read command has been completed. A "0110” can be sent to indicate that there was a failure in verifying the error detection/correction field 530. A "0000" can indicate that the port module 105 has not been addressed, while the remaining bit values can be either invalid or reserved for future uses.
  • FIG. 6 is a timing diagram illustrating the timing of the communication of transmission frames, in accordance with an exemplary embodiment of the present invention.
  • a system controller signaling clock signal 605 is used internally by the system controller 160 to generate the transmission data pulses.
  • the system controller signaling clock signal 605 does not appear on the port module 105, but is included in the timing diagram as a timing reference only.
  • the power feed to the port module 105 also acts as its communication medium.
  • the +12V power feed to the port module 105 is toggled by the system controller 160 (i.e., the power feed is switched on and off) to produce data bits for transmission to the controller circuit 125 of the port module 105.
  • the signaling state signal 610 can be the logical inverse of the power feed of the port module 105 (e.g., when the power feed is at +12V, the controller circuit 125 "sees" a logical 0 (or logical de-assertion) on its input data pin, and when the power feed is off, the controller circuit 125 "sees" a logical 1 (or a logical assertion)).
  • data transmission from the system controller 160 to the port module 105 can be conducted through a pulse- width modulation technique, or the like, applied to the power signals supplied from the system controller 160 to the port module 105.
  • Each data bit sent from the system controller 160 to the port module 105 can have a period of four master clock cycles.
  • the data interpreted by the port module 105 can be determined by the width of the generated pulse as follows: a 1 -cycle pulse width can represent a Data 0; a 2-cycle pulse width can represent a Data 1 ; and a 3-cycle pulse width can indicate a start of transmission frame flag.
  • the edge detect pulse signal 615 can be activated.
  • the signaling edge detect pulse signal 615 can begin to charge an RC timing circuit on the port module 105 board.
  • the signaling edge detect pulse signal 615 can be de-activated, and the secondary pulse signal 620 is activated.
  • the secondary pulse signal 620 can remain active until the RC timing circuit discharges below a logic-low trip level (e.g., a Schmitt trigger gate or the like can be used for level tripping).
  • the state of the communication link portion of the system link 130 can be read by the port module 105 on the falling edge of the signaling edge detect pulse signal 615 and interpreted as a logical 1 or 0.
  • the state of the communication link portion of the system link 130 can also be read on the falling edge of the secondary pulse signal 620.
  • a logical 1 received on the communication link portion of the system link 130 at this latter time can indicate the start of a transmission frame condition, as indicated by start of frame detect signal 625. All input counters and registers of the controller circuit 125 can be reset when the start of transmission frame flag is detected.
  • the data bits to be sent to the system controller 160 can be logically asserted on the falling edge of the secondary pulse signal 620, resulting in a port module logical response signal 630.
  • the port module logical response signal 630 can be used to control a transistor on the port module 105.
  • the transistor can be used to increase the current load presented to the port module 105 power feed received over the communication link portion of the system link 130.
  • the system controller 160 will detect the current increase on the power feed, and translate the current increase into a logical 1.
  • the port module 105 can thus modulate the power signals to transmit information signals to the system controller 160 via step current variations on the power feed.
  • the system controller 160 can sample the port module 105 current at, for example, the rising edge of the fourth interval of the system controller signaling clock 605 to recover the information signals emanating from the port module 105.
  • the system controller 160 can include a test device matrix circuit 170 for connecting one of the at least one test devices 133 to a port module 105.
  • the system controller 160 can support, for example, two system test busses allowing for two simultaneous and independent test accesses, although any suitable number of test busses can be supported.
  • the test device matrix circuit 170 can use a matrix structure for connecting the active port module 105 to the appropriate test bus and associated test device 133 through relay switching (e.g., two 20-to-l relay switching matrices according to one exemplary embodiment, although other relay switching matrices can be used).
  • the system controller 160 can include a test bus expander port (e.g., a 96-pin DIN connector or the like) to expand the number of available system test busses using a relay-matrix daughter card or the like.
  • the system controller 160 can include other suitable electrical and/or electronic components for performing the functions described herein.
  • the system controller 160 can include a PLD (e.g., an Altera 7256 CPLD or any suitable PLD).
  • the system controller 160 can also include a central processing unit (CPU) (e.g., a Motorola MPC852T Quad Integrated Communications Controller clocked by a 10 MHz crystal oscillator, or any other similarly suitable CPU).
  • CPU central processing unit
  • 852T CPU such a CPU contains numerous types of communication ports, including one Serial Peripheral Interface (SPI).
  • SPI Serial Peripheral Interface
  • communication between the PLD and CPU of the system controller 160 can be conducted via a four-wire SPI (e.g., serial_clock, data_in, data out, and enable signal).
  • SPI serial_clock, data_in, data out, and enable signal
  • enabling signals one for port module communications and one for the internal PLD registers.
  • messages on the system controller 160 SPI bus can be ignored, and the SPI data out pin can be tri-stated.
  • the PLD registers can begin accepting data transmissions from the CPU.
  • SPI register reads/writes involve sending an address and then eight data bits. For example, when writing to PLD registers through the SPI interface, first the four-bit address can be transmitted, then the eight bits of data.
  • the PLD can be programmed to have a parallel interface for its internal registers.
  • a rising edge on a SPI-PLD port module enable signal can start a process for writing to a selected port module 105.
  • the first eight bits of serial data received after the SPI-PLD port module enable signal becomes active can be stored as the module select bits.
  • up to an additional 1 16 bits can be passed along to the selected port module 105, although the total number of bits can vary depending upon the modulation scheme used.
  • Table 1 illustrates an exemplary port module bit stream.
  • bits 3 to 7 are used to select or otherwise specify a port module 105 to which the data is to be directed.
  • the system address of a port module 105 can be defined by which physical RJ-45 connection on the system controller 160 to which the port module 105 is connected (via the communication link of the respective system link 130).
  • Bit 8 is the start of transmission frame flag.
  • the "PORT MODULE COMMAND BITS" comprise the fields of the transmission frame 500, as discussed previously. Other configurations of the serial data are possible.
  • communication between the CPU and the port modules 105 is established via the system controller 160 PLD and the SPI bus.
  • This mode is activated via the SPI-PMC port module enable signal.
  • the PLD acts as a data pass through, from sender to receiver, after the port module address is received.
  • Data is transferred to the active port module 105 port as specified in the first eight SPI data bits (as illustrated in Table 1).
  • the SPI bit stream from the CPU master creates a pulse width modulated (PWM) signal for the port module 105.
  • PWM pulse width modulation is accomplished by latching the output data high after a logical 1 is clocked in, and keeping the output data high until a logical 0 is clocked in.
  • Twenty-nine port module 105 command bits can be encoded, as shown in the following Table 2:
  • the system controller 160 can include other suitable electrical and/or electronic components for performing additional functions.
  • the system controller 160 can include an Ethernet interface port 175 for supporting Base 10/100 twisted pair interface media connections.
  • the system controller 160 can include an asynchronous interface port 180 to provide a RS-232 asynchronous port for communication via an external RJ-45 like connector.
  • the system controller 160 can include a test access port for performing boundary scan testing of the CPU and to program the PLD.
  • the test access port can be JTAG compatible and can use, for example, a five signal dedicated interface on the CPU.
  • the system controller 160 can also include a monitor access amplifier. For example, when a communication circuit is accessed in the AC monitor access mode, the system controller 160 can insert a wideband monitor amplifier into the system test bus.
  • This circuit amplifies the current generated from the in-circuit monitor current transformer within monitor access circuit 145 on the port module 105.
  • the monitor access amplifier can mimic the impedance versus frequency characteristics of a suitable transmission-line, so that the current sensed from the test circuit is interpreted to more accurately reflect the power spectrum of the circuit under test.
  • the system controller 160 can also supply the DC current to bias the monitor current transformer within monitor access circuit 145 of the port module 105 (the derived AC current waveform can ride on the DC current carrier).
  • the system controller 160 can also include additional and/or alternative components, such as, for example, any suitable type of memory (e.g., flash memory to store system controller 160 firmware, RAM, ROM, EPROM and the like), a real-time clock, voltage monitors (e.g., to ensure that voltages are properly generated), and the like, depending on the desired characteristics of the system 100.
  • any suitable type of memory e.g., flash memory to store system controller 160 firmware, RAM, ROM, EPROM and the like
  • a real-time clock e.g., to ensure that voltages are properly generated
  • voltage monitors e.g., to ensure that voltages are properly generated
  • the network device 112 can comprise any suitable type of network element, such as, for example, a DSLAM or the like.
  • the communication circuits can be associated with the network device by, for example, being terminated on or otherwise connected to the DSLAM.
  • the connection means 1 17 can be any suitable type of connection capable of coupling the port module 105 through an MDF, an intermediate distribution frame (IDF) or the like towards an end user.
  • the port module 105 is configured to be connected directly to, for example, a recessed portion of a back (front) plane of a DSLAM like a type of cable connector, the port module 105 can be situated anywhere between the network device 112 and the connection means 117, so long as it can provide a connection for the communication circuits from the DSLAM (i.e., equipment side) to the MDF and/or IDF (i.e., the facility side).
  • FIG. 7 is a flowchart illustrating steps for providing test access to communication circuits associated with a network device, in accordance with an exemplary embodiment of the present invention.
  • an apparatus e.g., a port module 105
  • the apparatus is connected to a connection means.
  • one of the at least one test device is coupled to the apparatus, hi step 720, signals are switched between the network device and the connection means via the apparatus.
  • power signals are received at the apparatus over a communication link to power the apparatus, hi step 730, the power signals are modulated over the communication link to communicate information signals for testing the communication circuits.
  • an information signal can comprise a transmission frame.
  • the transmission frame can comprise, for example, a command field, an address field, a visual identifier field, a communication circuit number field, an access mode field, an error detection/correction field, an event timing field, an apparatus response field, and any other suitable fields.
  • the information signal can also include a start of transmission frame flag.
  • the information signals received over the communication link can comprise pulse-width modulated power signals.
  • a signal is generated for increasing a current load on the power signals received at the apparatus to modulate the information signals for transmission from the apparatus.
  • the modulated power signals are converted to supply power to the apparatus.
  • one of a plurality of access modes of the apparatus is selected.
  • the plurality of access modes can comprise a split access mode, an AC monitor access mode, a DC monitor access mode or any other suitable test access modes.
  • the apparatus is protected from power transients.
  • Exemplary embodiments of the present invention can be in conjunction with, for example, communications testing equipment for testing communications circuits, such as, for example, xDSL circuits, particularly where space and cabling restrictions for adding testing equipment are severe.
  • Exemplary embodiments of the present invention can be embodied, in whole or in part, in hardware, firmware, any other type of electronic circuitry, software, or any combination thereof.
  • Exemplary embodiments of the present invention can substantially simplify installation procedures for test access equipment and reduce installation costs, particularly with respect to the size, length and routing of cabling to support such test access equipment.
  • exemplary embodiments can allow the elimination of the added loop circuit cabling between the network device and an access element required in conventional schemes, the elimination of the rerouting of the network- device-to-distribution- frame loop circuit cabling in favor of a minor re-connection near the network device, and the elimination of separate power and communication circuit wiring to each access element, among other features.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Small-Scale Networks (AREA)

Abstract

Un module de ports pour adaptateur de câble (CAPM) est destiné à assurer l'accès aux circuits de communication associés à un multiplexeur d'accès à ligne numérique d'abonnés (DSLAM); il comprend une première pluralité de ports destinés au couplage de CAPM avec DSLAM. CAPM comprend une deuxième pluralité de ports destinés au couplage de CAPM avec un répartiteur (DF). CAPM comprend également un circuit de matrice de sélecteur, destiné à commuter les signaux entre DSLAM et DF. CAPM comprend un circuit de contrôleur en communication avec le circuit de matrice de sélecteur destiné à contrôler CAPM. CAPM reçoit les signaux d'alimentation via une liaison de communication de façon à alimenter CAPM. Le circuit contrôleur module les signaux d'alimentation dans la liaison de communication de manière à communiquer les signaux d'informations pour tester les circuits de communication.
PCT/US2005/027360 2004-07-30 2005-08-01 Module de ports pour adaptateur de cable Ceased WO2006015350A2 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US59219204P 2004-07-30 2004-07-30
US60/592,192 2004-07-30
US10/938,948 2004-09-13
US10/938,948 US20060034180A1 (en) 2004-07-30 2004-09-13 Cable adapter port module
CN200410078070 2004-09-20
CN200410078070.5 2004-09-20

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WO2006015350A2 true WO2006015350A2 (fr) 2006-02-09
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2007200039B1 (en) * 2006-09-30 2007-09-27 Huawei Technologies Co., Ltd. Access apparatus and method for digital subscriber line test
WO2009036680A1 (fr) 2007-09-19 2009-03-26 Huawei Technologies Co., Ltd. Procédé, dispositif et système d'identification de configuration de matériel d'accès d'essai
CN102479165A (zh) * 2010-11-30 2012-05-30 英业达股份有限公司 测试装置的识别码的自动配置方法
CN109213640A (zh) * 2017-06-29 2019-01-15 罗森伯格（上海）通信技术有限公司 一种配线架扫描装置
US10277384B2 (en) 2017-04-04 2019-04-30 Cisco Technology, Inc. Intermediate distribution frame for distributed radio heads

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826280B1 (en) * 1999-12-14 2004-11-30 Adc Telecommunications, Inc. Systems and methods for managing digital subscriber line (DSL) telecommunications connections
US6768794B1 (en) * 2000-09-14 2004-07-27 Adc Telecommunications, Inc. Testing box for a telecommunications system
US6917683B2 (en) * 2002-11-04 2005-07-12 Mphase Technologies, Inc. Signal splitter with test relays on auxiliary circuit board and system using same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2007200039B1 (en) * 2006-09-30 2007-09-27 Huawei Technologies Co., Ltd. Access apparatus and method for digital subscriber line test
US8249221B2 (en) 2006-09-30 2012-08-21 Huawei Technologies Co., Ltd. Access apparatus and method for digital subscriber line test
WO2009036680A1 (fr) 2007-09-19 2009-03-26 Huawei Technologies Co., Ltd. Procédé, dispositif et système d'identification de configuration de matériel d'accès d'essai
EP2093935A4 (fr) * 2007-09-19 2009-12-02 Huawei Tech Co Ltd Procédé, dispositif et système d'identification de configuration de matériel d'accès d'essai
CN102479165A (zh) * 2010-11-30 2012-05-30 英业达股份有限公司 测试装置的识别码的自动配置方法
US10277384B2 (en) 2017-04-04 2019-04-30 Cisco Technology, Inc. Intermediate distribution frame for distributed radio heads
CN109213640A (zh) * 2017-06-29 2019-01-15 罗森伯格（上海）通信技术有限公司 一种配线架扫描装置
CN109213640B (zh) * 2017-06-29 2023-12-12 普罗斯通信技术（苏州）有限公司 一种配线架扫描装置

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