WO2006011239A1 - Capacitive mems device and process for fabricating same, and high-frequency device - Google Patents
Capacitive mems device and process for fabricating same, and high-frequency device Download PDFInfo
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- WO2006011239A1 WO2006011239A1 PCT/JP2004/011219 JP2004011219W WO2006011239A1 WO 2006011239 A1 WO2006011239 A1 WO 2006011239A1 JP 2004011219 W JP2004011219 W JP 2004011219W WO 2006011239 A1 WO2006011239 A1 WO 2006011239A1
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- film
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- upper electrode
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- lower electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/10—Auxiliary devices for switching or interrupting
- H01P1/12—Auxiliary devices for switching or interrupting by mechanical chopper
- H01P1/127—Strip line switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/16—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/16—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes
- H01G5/18—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes due to change in inclination, e.g. by flexing, by spiral wrapping
Definitions
- the present invention relates to a capacitive type MEMS (Micro-Electro-Mechanical Systems) element and a manufacturing method thereof. Furthermore, another aspect of the present invention relates to a high-frequency device equipped with the capacitive MEM S element.
- Capacitance type MEMS elements are elements that turn on / off high-frequency electrical signals by changing the capacitance value. It is useful for high-frequency electrical signals from several megahertz to several terahertz. Background art
- the M E M S element is known as a fine electromechanical component that turns off electrical signals.
- a thin dielectric film is formed on the signal line, which is a two-part electrode, and ground lines are formed in parallel on both sides of the signal line.
- the ground wire is electrically connected with a membrane composed of a metal anchor, spring, and upper electrode. This membrane is formed in such a way that a space is provided vertically across the dielectric film formed on the signal line.
- a metal film called a floating metal is formed on the dielectric film on the lower electrode located below the upper electrode.
- the basic operation of the element is as follows.
- the membrane functioning as the upper electrode and the signal line as the lower electrode when no DC voltage is applied between the membrane functioning as the upper electrode and the signal line as the lower electrode, it is between the membrane and the dielectric film formed on the signal line.
- the switch operation is on (membrane up), and the input signal reaches the output terminal.
- the membrane When a DC voltage is applied, the membrane is attracted to the signal line side by the electrostatic force (that is, Coulomb force) generated by the potential difference between the membrane and the signal line, and elastically deforms and bends to the substrate side.
- the capacitive MEMS element of Reference 1 the upper electrode is in contact with the dielectric film on the signal line
- the capacitive MEMS switch of Reference 2 the upper electrode is on the dielectric film. It will be in contact with the formed floating metal.
- the capacitor structure including the membrane, the dielectric film, and the signal line is formed in both of the two structures, so that the switch operation is in the off (membrane down) state. In this state, the input signal cannot reach the output end.
- the capacitance value in the off state can be obtained in a stable and high value as compared with the structure of Reference 1.
- the structure of Document 2 has a characteristic that a switching characteristic for a high-frequency signal is better than that of the element of Document IV.
- the M E M S element of the above-mentioned method is called a capacitive M E M S element (switch) as well as an electrostatic drive type M E M S element (switch) because of its operating principle.
- a capacitive M E M S element switch
- an electrostatic drive type M E M S element switch
- M E M S switches There are two types of M E M S switches: a series connection type switch that connects M E M S elements in series with the signal line, and a shunt type switch that is connected in parallel.
- a shaver type will be described as an example unless otherwise specified. It goes without saying that the present invention can be used for any type of switch. Disclosure of the invention
- a main object of the present invention is to provide a capacitive M E M S element which can obtain a good and stable switching characteristic for a high-frequency signal and which operates at a low voltage, and a method for manufacturing the same. Furthermore, another object of the present invention is to provide a high-performance high-frequency device equipped with the capacitive M E M S element of the present invention.
- the main forms of the capacitive M E M S element of the present invention are as follows.
- the upper electrode faces the lower electrode and is disposed at least with a gap from the conductor layer on the dielectric layer, and contact with the conductor layer on the dielectric layer is controlled.
- the conductor layer on the said dielectric material layer is the said insulating group. 2004/011219
- a conductor layer on the dielectric layer exists in a part of the facing area, and the upper electrode
- the area of the region where the conductor layer on the dielectric layer exists in the region where the electrode and the lower electrode face each other is the area of the region where the conductor layer on the dielectric layer does not exist in the opposite region, etc. It is important to be small or small.
- Another form of the capacitive M E M S element of the present invention is as follows.
- the upper electrode is disposed so as to face the lower electrode and at least have a gap with the conductor layer on the dielectric layer, and contact / non-contact with the conductor layer on the dielectric layer is controlled.
- the conductor layer on the dielectric layer is connected to a desired potential in a direct current manner through a resistor for high-frequency signals.
- Another aspect of the present invention is to provide a high-frequency device having the various capacitance type M E M S elements.
- FIG. 1A is a plan view for explaining a first embodiment of a capacitor MEMS element according to the present invention.
- FIG. 1B is a sectional view taken along line BB ′ in FIG. 1A.
- FIG. 2A is a plan view for explaining another means for solving the problems of the prior art.
- FIG. 2B is a sectional view taken along line BB ′ in FIG. 2A.
- FIG. 3A is a plan view for explaining a conventional capacitive MEMS element.
- FIG. 3B is a sectional view taken along line BB ′ in FIG. 3A.
- FIG. 4A is a top view for explaining a conventional capacitive MEMS element.
- FIG. 4B is a cross-sectional view taken along line 8-8 in Fig. 4.
- FIG. 5 is a plan view for explaining means for solving the problems of the prior art.
- FIG. 6 is a plan view for explaining another means for solving the problems of the prior art.
- FIG. 7A is a plan view for explaining the first embodiment of the capacitor M EMS element according to the present invention.
- FIG. 7B is a cross-sectional view taken along line 8-8 'in Fig. 7.
- FIG. 8 is a plan view for explaining a third embodiment of the present invention.
- FIG. 9A is a plan view for explaining a fourth embodiment of the capacitor MEMS element according to the present invention.
- FIG. 9B is a sectional view taken along line 8-8 ′ in FIG.
- FIG. 9C is a schematic perspective view for explaining the structure of the membrane in the example of FIG. 9A.
- FIG. 1 O A is a plan view for explaining a fifth embodiment of the capacitor M E M S element according to the present invention.
- FIG. 108 is a cross-sectional view taken along line BB ′ in FIG.
- FIG. 11A is an equivalent circuit diagram of the control circuit of the sixth embodiment.
- FIG. 11B is an equivalent circuit diagram of the control circuit of the seventh embodiment.
- FIG. 12A is a cross-sectional view showing the membrane in an up state in the sixth embodiment.
- FIG. 12B is a cross-sectional view showing the membrane in a down state in the sixth embodiment.
- FIG. 13 is an equivalent circuit diagram for explaining the control circuit used in the eighth embodiment.
- FIG. 14 is a block diagram for explaining the ninth embodiment.
- FIG. 15 is a cross-sectional view showing an example of the manufacturing process of the capacitive M EMS element according to the first embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
- the inventors first made a prototype of a capacitive MEMS device having a structure substantially equivalent to that of Document 1, and evaluated the absolute value and the capacitance ratio of the capacitor during the switch operation (on / off) as described above. did.
- FIG. 3A is a plan view of the element
- FIG. 3B is a sectional view.
- a signal line 1 is provided on the insulating substrate 3. Surround this with the ground wire
- a dielectric film 5 is formed so as to cover the signal line 1.
- An upper electrode 12 is provided while maintaining a gap 80 with the dielectric film 5 while being in contact with the ground wire 2.
- Panels 1 1 are formed at both ends of the upper electrode 12.
- the member composed of 0 is called membrane 8.
- Membrane 8 has an anchor 10 connected to a grounding wire 21 (hereinafter referred to as “earth”), a panel 11 1 having a meander (bending structure), and an upper electrode 12 having a body structure. .
- opposing area The area of the opposing area (the area where both the upper and lower electrodes overlap when viewed from the vertical direction: hereinafter simply referred to as “opposing area” unless otherwise noted) is 2 0 0 micrometer X 2 0 0 It's a micro-meat.
- the distance of the space 80 between the upper electrode 12 / dielectric film 5 is about 1.3 micrometers, and a dielectric formed on a part of the lower electrode signal line 1 and part of the insulating substrate 3 As the material of the film 5, an alumina film having a film thickness of 0.3 micrometers was used.
- the membrane 8 is made of Au (gold) with a film thickness of 2.5 micrometers.
- the signal line 1 which is the lower electrode and the ground wire 2 connected to the membrane 8 are connected to the lower layer.
- a sacrificial layer pattern to be removed later is formed under the membrane to form a membrane 8 that floats in the air.
- the upper electrode 2 is provided with a plurality of 10-micrometer hole holes at intervals of 20 micrometers. The sacrificial layer will be described later.
- materials used for the sacrificial layer there are generally a silicon oxide film, a photoresist film, a polyimide film, and the like, but a polyimide film was used for the production of the capacitive MEMS element.
- the voltage applied to signal line 1 was gradually increased from 0 V (where earth 2 was grounded).
- upper electrode 1 connected to earth 2 2 / For the capacitance value (about 0.5 p F) obtained when no voltage is applied between the lower electrode 1 that is the signal line (0 V: membrane up), the upper electrode 1 2 Z lower Even if a DC voltage of 6 V is applied between the electrodes 1 and the upper electrode 1 2 is attracted in the direction of the lower electrode 1 and comes into contact with the dielectric film 5 (membrane down), the capacitance value 2004/011219
- the upper electrode 12 is completely in contact with the dielectric film 5 (membrane), so that the capacitance value is higher than when the membrane is up (ie, at 0 V).
- the increase in the capacitance value was extremely small in the actual prototype.
- the capacitance value is reduced due to the formation of a low dielectric region between the upper and lower electrodes due to the air gap.
- FIG. 4A is a plan view of the element
- FIG. 4B is a cross-sectional view taken along line B B '.
- a signal line 1 serving as a lower electrode is provided on the insulating substrate 3.
- a grounding wire 2 is disposed around the signal line 1.
- a floating metal (a metal film in a flow ⁇ state) 6 is disposed on the dielectric film 5.
- An upper electrode 12 is provided in contact with the ground line 2 while maintaining a gap 80 with the floating metal 6 and the dielectric film 5.
- the membrane 8 connected to the spring 11 and the panel is formed at both ends of the upper electrode 12.
- the membrane 8 is composed of an upper electrode 1 2, a spring 1 1, and an anchor 0.
- the structure shown in FIGS. 3A and 3B is formed with a floating metal 6 that is not electrically connected to anywhere at all times. It is.
- the metal film 6 is an Au (gold) film having a thickness of 100 nm on the dielectric film 5 in the facing region 8 1.
- the area of the floating metal 6 was smaller than the opposing region 8 1 of the two electrodes, and the dimensions were 1800 micrometers ⁇ 180 micrometers.
- the positions formed are covered from the outer peripheral four sides of the opposing area 8 1 to the area inside 10 micrometers each.
- the upper electrode 1 As a result of evaluation using the capacitive M E M S element having the above structure, the upper electrode 1
- an operating voltage of about 20 V which is about 3 times higher than that without the floating metal 6, is required. Furthermore, after repeating the up-and-down movement of the membrane several times and leaving it to stand for several seconds while applying the voltage of 20 V, the capacitance value between the upper and lower electrodes becomes the initial value (0.
- the capacitance value is 2 0
- the EMS element requires a high voltage for the operation of the element and can provide extremely unstable switching characteristics, particularly when applied to a high-frequency switch that handles high-frequency signals of several hundred megahertz or more.
- the essence of the present invention is a capacitive MEMS element having a floating metal made of a conductor layer.
- the area ratio of the layer (floating metal) should be 50% or less of the entire opposing region (otherwise the dielectric film exposed region).
- another means for solving the above problem is to connect the conductor layer (floating metal) in a direct current manner with a substance having a desired potential through a substance that becomes a resistance to a high-frequency signal.
- the substance that becomes a resistance to the high-frequency signal is a resistor that exhibits an electrical resistance value of at least ⁇ k ⁇ and less than 1 M ⁇ , and a high-frequency signal that is at least 1 ° ⁇ or more. It is desirable that the inductor has an impedance of less than ⁇ .
- the substance having the desired potential may be any of the group consisting of the upper electrode, a ground region (ground), and a control electrode that controls the vertical movement of the upper electrode by applying a DC voltage. It is also desirable to facilitate the device fabrication. In this way, it is fundamentally possible to prevent a tipping.
- the pattern shape of the floating metal is not particularly limited to a specific shape. For example, by providing an opening having a predetermined shape inside the pattern as long as the area ratio in the facing region is protected. The exposed region of the dielectric film may be secured.
- the panel, the anchor, and the upper electrode have an integral structure and are formed of a continuous metal body.
- the metal body is preferably formed of a substance mainly composed of at least a low-resistance metal material.
- a single-layer film containing aluminum, a laminated film of an aluminum-containing film and another metal film According to any one of a single-layer film containing gold, or a laminated film of a gold-containing film and another metal film, a single-layer film containing copper, or a laminated film of a copper-containing film and another metal film It is desirable that it be formed.
- the film is formed of any one of a laminated film with another metal film, a single-layer film containing copper, or a laminated film of a copper-containing film and another metal film. That is, in general, it is preferably formed of a substance mainly composed of a low-resistance metal material.
- the electrostatic force is greater than the restoring force of the panel to which the upper electrode is connected in order for the upper electrode to be attracted toward the lower electrode by electrostatic force.
- the upper electrode and the floating metal have the same potential, and the electrostatic force generated from the floating metal to the upper electrode disappears.
- the electrostatic force that attracted the upper electrode was smaller than the restoring force of the panel, and the upper electrode moved away from the floating metal, resulting in a smaller capacitance value.
- the floating metal is electrically insulated, the accumulated charge is released only by spontaneous discharge. And natural discharge takes tens of seconds.
- the size of the facing region between the upper electrode and the lower electrode of the capacitive MEMS element used in this experiment is 2 0 0 micrometer x 2 0 0 micrometer as described above, and the dimensions of the floating metal are 1 0 0 respectively.
- Microphone mouth (25% of the total), 120 micrometer port (36% of the total), 1550 micrometer port (56% of the total), 1700 micrometer ⁇ (total 7 2% of the body). The formed position was formed so that the center of the facing region and the center of the floating metal were aligned.
- the element with 1 50 micrometer ⁇ floating metal shows the behavior of changing the capacitance by 1 (/ 5), while the element with ⁇ 4 ⁇ micrometer ⁇ floating metal has a mysterious capacitance change. Does not occur. Therefore, the area of floating metal that can actually be applied 19
- the ratio is preferably 50% or less of the entire opposite area.
- an element with the structure shown in Fig. 5 was created and evaluated.
- the structure of FIG. 5 is substantially the same as the structure of FIG. 4A, except that the floating metal 6 is formed on the dielectric film 5 outside the opposing region from the floating metal 6 formed in the opposing region. It is also formed as a continuous series of patterns. At this time, the area ratio of the floating metal in the facing region viewed from the vertical direction is about 45% of the entire facing region.
- the operating voltage was 9.8 V, and it did not show a mysterious capacitance value behavior due to the voltage application.
- the capacitance value was about 45 pF, which was about 90 times the initial value (0.5 pF).
- a resistor pattern 7 having an electrical resistance value of 1 k ⁇ or more (3.7 k ⁇ in actual measurement) is arranged between the floating metal 6 and the case 2 of the element shown in FIG.
- a capacitive MEMS device with the structure shown in the figure was fabricated.
- a DC voltage was applied between the upper and lower Z electrodes, and the presence or absence of changes in the capacitance value due to leaving the operating voltage and the operating voltage applied was evaluated.
- the capacitive MEMS element is mainly used as a switch for a high-frequency signal, and has a relatively high resistance as a property of the high-frequency signal. Since it is not possible to pass through a substance or an inductor that has high impedance as an impedance, in this experiment, the metal resistor of 1 ⁇ or more was used as an example.
- the existence of the resistor is one of the methods for quickly releasing the electric charge that is considered to be accumulated in the floating metal.
- the connection destination of the floating metal is grounded.
- the floating metal is short-circuited in terms of direct current, but remains floating in terms of high-frequency.
- the operating voltage itself was increased to 15 V, the inexplicable behavior of the capacitance value was not observed when the voltage was left applied.
- the upper electrode connected to the ground and the floating metal connected via the resistor are always at the same potential in terms of DC. Therefore, no electrostatic force is generated between the floating metal and the upper electrode, and only in the narrow facing area between the lower electrode under the dielectric film exposure area other than the floating metal and the upper electrode in the area facing it. It can be estimated that this is because they are attracting each other.
- the switching time / loss (On / Offf) switching time and loss of the switch deteriorate.
- the amount of charge remaining on the floating metal is inversely proportional to the exponential function of time.
- the time constant dt at which the amount of charge is 1 / e is the product of the capacitance C f of the floating metal and the ground C f, and the resistance value R f of the resistive element used C f ⁇ Represented by R f. Since the time constant dt must be smaller than the required on / off switching time dt 0 ff, dt 0 ff >> dt Need to be. In the case of a low-loss switch operating in the GHz band, C f needs to be 5 p F to 20 p F and dtoff ⁇ 0.1 msec, so that R f ⁇ 5 R to 20 M ⁇ There is a need.
- the switch loss it is necessary to consider the balance with the Q value of the electronic components (and filters, etc.) connected to the switch.
- the Q value of the filter is about 20 to 200, and especially in the case of a high Q filter, the switch is required to have high performance.
- the floating metal is connected to the ground.
- the same effect can be obtained when the voltage terminal is used.
- an inductor is used to change the resistance element, the same effect can be obtained by replacing it with impedance in the frequency band in which R f is operated.
- FIGS. 2A and 2B Fig. 2A is a plan view and Fig. 2B is a cross-sectional view along line BB.
- Fig. 2A is a plan view
- Fig. 2B is a cross-sectional view along line BB.
- This example differs from the example in Fig. 6 in the shape and area ratio of the floating metal 6. Therefore, other detailed explanation is omitted.
- the area ratio of the floating metal 6 was designed to be 5% of the entire facing area.
- the area of the floating metal 6 in the opposing region is remarkably reduced, and the floating metal 6 is extended and formed on the dielectric film 5 other than the opposing region. Furthermore, floating metal 6 is short-circuited to ground 2 through a resistance element of about 2 k ⁇ . It is the structure made to do.
- the operating voltage was 6.2 V. This voltage value is almost the same value as when no floating metal was provided, and the capacitance value obtained at this time was 3 2 p F, which was approximately 60 times the initial value.
- the floating metal itself is connected in direct current to a substance having a desired potential via a substance that becomes a resistance to a high-frequency signal.
- the capacitive M E M that operates at an operating voltage almost equivalent to the structure without the floating metal
- S element can be manufactured.
- the floating metal can be used as long as the restrictions on the area ratio of the formation pattern in the opposing region are observed. You may form widely also in area
- the shape of the floating metal in the facing region is not particularly limited, and may be provided in any shape. 19
- the substance that becomes a resistance to the high-frequency signal is, for example, a high-resistance body having an electrical resistance value of 1 to 1 M ⁇ or an inductor that exhibits an impedance of 1 to 1 M ⁇ .
- the substance having a desired potential refers to, for example, a ground wire, an upper electrode, a lower electrode, a control electrode, etc., depending on the structure of the element.
- the anchor, the panel, and the upper electrode form an integral structure to form a membrane and be formed of a continuous and same low-resistance metal body.
- the metal body is preferably a single metal film having a low resistance of gold, aluminum, or copper, or a laminated film of the metal species and another metal.
- the low-resistance metal film formed on the dielectric film is also preferably made of a low-resistance metal material, and in particular, a material that can significantly reduce the contact resistance with the upper electrode is preferable. Specifically, it is desirable to be a single metal film such as gold, aluminum, or copper, or a laminated film of the above metal species and another metal.
- the surface of the floating metal made of the low-resistance metal film is the same material as the floating metal, or other materials unless the surface of the floating metal is in contact with the upper electrode at a constant time (when no voltage is applied), except for a flat surface.
- One or a plurality of upward projections made of a low-resistance metal material may be provided.
- the present invention As described above in detail, according to the present invention, extremely good and stable switching characteristics and isolation characteristics can be obtained for high-frequency signals. It is. Furthermore, according to the present invention, it is possible to provide a capacitive MEMS element that operates at a low voltage with high reliability, and a high-performance high-frequency device equipped with the capacitive MEMS element of the present invention.
- the capacitance value at the time of switching off (when applying voltage) when functioning as a high-frequency switch is also used to extend the floating metal on the dielectric film located on the lower electrode other than the opposing region.
- the capacitance value almost as calculated can be easily realized from the area of the entire floating metal, so the design of the switch element becomes extremely easy.
- the floating metal formation area can be expanded to areas other than the opposing area, and the upper electrode only needs to be in contact with the floating metal at one location. Can be small. As a result, the bending / deformation due to the residual internal stress of the membrane including the upper electrode made of a metal body may be remarkably suppressed.
- Floating metal made of a low-resistance metal film in contact with the upper electrode is also extremely low because the contact resistance and series resistance can be reduced by using a metal film mainly composed of Au, AI, and Cu with low resistance. High frequency signals can be transmitted without loss.
- the capacitive MEMS element of the present invention in addition to its use as a high-frequency switch, one or more of these elements can be connected in parallel and in series, so that an SP n T switch, It can also be applied to variable capacitance devices that can vary a wide range of capacitance values.
- the capacitive MEMS element of the present invention requires a very slight increase in process from the viewpoint of the manufacturing process, an increase in manufacturing cost can be suppressed to a small extent. Since the capacitive MEMS element of the present invention can be easily manufactured by a general semiconductor manufacturing process, it is formed on the same substrate as a semiconductor active device such as an FET or a bipolar transistor and other passive devices. Therefore, it is possible to easily manufacture a module device that is smaller than before.
- FIG. 1A and 1B schematically show a first embodiment of the present invention.
- FIG. 1A is a plan view of the element
- FIG. 1B is a cross-sectional view along the line B B '.
- a signal line 1 that also functions as a lower electrode of the element is formed on an insulating substrate 3, and a ground 2 is formed around it.
- the insulating substrate 3 is formed of an insulating material such as a glass substrate, a compound semiconductor substrate, a high-resistance silicon substrate, or a piezoelectric substrate.
- the insulating substrate 3 may be a semi-insulating substrate whose surface is covered with an insulating film typified by silicon oxide, or a conductive substrate.
- the signal line 1 functions as a coplanar type high-frequency signal line extending in the front and back direction of Fig. 1B, together with the ground 2 installed at a predetermined distance.
- the membrane 8 formed so as to straddle the signal line 1 from the ground 2 is composed of four springs 1 having four anchors 10 connected to the ground 2 and meanders (bending structure) connected to the anchor 10. 1 and the upper electrode 1 2 form a body structure.
- a part on the signal line ⁇ ⁇ and a part on the insulating substrate 3 are covered with a dielectric film 5 made of an alumina film having a film thickness of 0.2 micrometer and located on the signal line 1.
- the surface of the dielectric film 5 has a T i ZA u two-layer structure.
- a floating metal 6 made of a low resistance metal film is formed.
- the area ratio of the floating metal 6 in the opposing region between the signal line 1 and the upper electrode 8 is 15% of the entire opposing region, and the dielectric located on the signal line 1 outside the opposing region On the film 5, the floating metal 6 is extended and formed widely.
- Floating metal 6 is grounded through resistance element 7 with an electrical resistance of 15 k ⁇ .
- Earth 2 is also grounded (DC potential 0 V) in DC. Therefore, the upper electrode 12 is grounded via the spring 11 and the anchor 10. However, since the floating metal 6 is connected to the ground 2 through the resistance element 7, it is grounded only in a direct current manner.
- the distance of the space between the upper electrode 12 and the dielectric film 5 is about 1.2 micrometers.
- the upper layer A u gold, film thickness 0.5 micrometer is used.
- a polyimide film is used as a sacrificial layer for forming the membrane 8 that floats in the air.
- the upper electrode 12 is provided with a plurality of through holes of 10 micrometers 0 at intervals of 20 micrometers.
- FIG. 7A and FIG. 7B schematically show the second embodiment of the present invention.
- the present invention is applied to a capacitive MEMS element having a structure using a cantilever made of a metal body.
- FIG. 7A is a plan view of the element
- FIG. 7B is a sectional view taken along the line BB ′.
- a signal line 13 having a function as a lower electrode of the element is formed on a glass substrate 5 whose surface is covered with silicon oxide, and a ground wire 4 is formed around the signal line 13.
- the cantilever beam 1 6 formed so as to cover a part of the signal line 1 3 from the ground pole 4 is composed of an anchor 1 7 connected to the ground 1 4 and a panel 1 8 connected to the anchor 1 7.
- the upper electrode 19 has a body structure. The area of the upper electrode 19 is 20 micrometers to 50 micrometers.
- Part of the signal line 1 3 and part of the Si substrate 15 are covered with a dielectric film 20 made of a silicon nitride film having a thickness of 0.15 micrometers.
- a floating metal 21 made of AI is formed on the surface of the dielectric film 20 located above.
- the area ratio of the floating metal 21 in the opposing region between the signal line 13 and the upper electrode 9 is 10% of the entire opposing region, and the signal line 1 outside the opposing region is Also on the dielectric film 20 located on 3, the floating metal 2 1 is extended and widely formed.
- the floating metal 2 1 is connected to the ground 14 through a resistance element 2 2 having an electric resistance value of 500 k ⁇ .
- ground 14 is also grounded (DC potential 0 V), so the upper electrode 19 connected to ground 14 is also grounded.
- the cantilever 16 as a whole is made of AI (aluminum) with a thickness of 2.0 micrometers, and the signal line 1 3 and ground 14 are also AI (aluminum, thickness 0). 4 micrometer) A single membrane is used.
- the sacrificial layer used to form the cantilever 16 having the upper electrode 19 that is connected to the earth 14 and floated in the hollow is made of a photoresist film.
- the upper electrode 19 is provided with a plurality of through-holes of a 2-micrometer meter opening at intervals of 5 micrometers.
- the operating voltage (voltage at which the upper electrode contacts the low-resistance metal film) of the M E M S element having the above structure was 1.5 V, and the capacitance value at that time was about 24 pF. This is a value of about 120 times the capacitance value at 0 V compared with about 0.2 pF.
- the overall size of the device is also smaller than that in the first embodiment.
- the operating voltage was lowered to 1.5 V, and the obtained capacitance value was almost the same as that of the first embodiment.
- the structure of the present invention it is possible to manufacture a high-capacity capacitive MEMS element having a smaller size and superior switching characteristics.
- FIG. 8 An example of a capacitive MEMS element in which a control terminal is provided separately from a signal line and ground will be described. An example of this is shown in the plan view of Figure 8.
- a signal line 6 1 is formed on a glass substrate 60, and a ground 6 2 is formed around the signal line 61.
- Membrane 64 has an electrostatic force between anchor 65 connected to control terminal 63, panel 6 6 having meander (bent structure) connected to anchor 65, and ground 62.
- the anchors 65 are formed at four locations, but only one anchor is connected to the control terminal 63, and all other anchors are formed on the glass substrate 60.
- Part of the signal line 6 1, part of the glass substrate 60, and part of the ground 6 2 were covered with a dielectric film 6 9 made of oxide oxide and having a thickness of 25 50 nanometers.
- a floating metal 70 is formed on the dielectric film 69 located on the signal line 61.
- the floating metal 70 is connected to the signal line 61 through an inductor element 71 having an impedance characteristic of about 150 k ⁇ for a high frequency signal of about 1 GHz.
- the signal line 6 1, the earth 6 2, the control terminal 6 3, the membrane 6 4, and the floating metal 70 are all made of copper.
- the structure described above is based on the floating mem Inductor element 7 1 is provided in order to prevent charge accumulation in Tal 70.
- the capacitance value obtained when the membrane contacts the floating metal by applying voltage to the control terminal has the feature that it can be remarkably increased.
- Shank connection type element has been described as an example, but the present invention has the same effect even in the series connection type.
- FIG. 9A, FIG. 9B, and FIG. 9C schematically show the fourth embodiment of the present invention.
- Fig. 9A is a plan view of the device
- Fig. 9B is a cross-sectional view along line B B '.
- This figure shows a capacitive M E M S element with a seesaw structure membrane.
- FIG. 9C is a schematic perspective view illustrating the structure of the membrane.
- An input signal line 24 made of Cu (copper) with a film thickness of 500 nm is formed on a glass substrate 28, and output signal lines 2 5 (left side) and 2 6 (right side) are formed on both sides thereof. ) Is formed. Around that area, a ground 27 is formed.
- a membrane 29 made of A u connected to an input signal line 24 formed on a glass substrate 28 is a first torsion spring that connects two anchors 30 and the two anchors 30 in a hollow state.
- One spring 3 1 a second spring 3 2 extending from the first spring 3 1 to the left and right sides, and a second spring 3 2 connected to the left and right sides ), And 3 4 (right side of the figure).
- the input signal line 24 is connected to the left and right upper electrodes 33 and 34, and on the glass substrate 28 located below the upper electrodes, from the lower electrode Cu to the lower electrode.
- the area ratio of the left and right floating metals 3 6 and 3 7 in the area facing the left and right output signal lines 25 and 26 and the left and right upper electrodes 3 3 and 3 4 is Both of them are 35% of the entire opposing region, and floating metal 3 6 and 3 7 are also formed on the dielectric film 35 located on the output signal lines 25 and 26 outside the opposing region. Each is extended and formed widely.
- Floating metals 3 6 and 3 7 are connected to ground 2 7 through inductor elements 3 8 and 3 9 that exhibit an impedance of about 30 O k Q for high-frequency signals of about 1 GHz to 5 GHz. ing.
- the capacitive MEMS element having the above structure operates by applying a DC voltage between the input signal line 24 and either one of the output signal lines 25 and 26 arranged on the left and right.
- the upper electrode 3 3 on the left is attracted to the line 25 and comes into contact with the floating metal 36 on the left, thereby forming a capacitor structure.
- the high-frequency signal input to the input signal line 24 is output from the left output signal line 25 through this capacitor.
- the upper electrode 34 on the opposite side rises upward, so that the isolation between the output signal line 26 and the upper electrode 34 increases.
- the upper electrode 3 3 on the left side can be moved away from the low resistance metal film 36.
- the upper electrode 3 4 on the right side By being attracted to the output signal line 26 and coming into contact with the floating metal 37 on the right side, a high frequency signal is now output from the output signal line 26 on the right side.
- the isolation between the output signal line 25 and the upper electrode 33 increases.
- the capacitive M E M S element of the basic invention generally has a structure called S P D T switch that can selectively switch between two paths for one signal line.
- S P D T switch that can selectively switch between two paths for one signal line.
- FIG. 10A is a plan view of the element
- FIG. 10B is a cross-sectional view along the line B B '.
- the present example is an example in which the present invention is applied to an ONONIS switch having a series connection type, although it has a membrane having substantially the same structure as that described in the first embodiment.
- the signal line is divided into the input side and the output side, a voltage is applied between the input side and the output side, and the high frequency signal is generated when the membrane contacts the low resistance metal film. It has a mechanism that flows to the output side.
- An AI input signal line 40 is formed on the Si substrate 43 whose surface is covered with silicon oxide, and has a predetermined interval inside the U-shaped region of the line 40.
- an output signal line 4 1 made of AI is formed.
- the membrane 4 4 connected to the U-shaped region of the input signal line 40 and straddling the output signal line 4 1 is composed of four anchors 4 5 and meanders (folds) connected to the anchors 4 5.
- the four panels 46 6 having the structure) and the upper electrode 47 have a body structure.
- a floating metal 49 having an opening made of Au is formed on the lower surface of the upper electrode 47.
- a plurality of protrusions 50 made of Au are formed downward.
- the area ratio of the floating metal 49 in the opposing region of the output signal line 4 1 and the upper electrode 47 is 15% of the entire opposing region, and the output signal line 4 outside the opposing region is 1 Floating metal 49 extending from the opposing region is also widely formed on the dielectric film 48 located above
- the distance of the space between the upper electrode 47 and the floating metal 49 is about 1.0 micrometer, and the protrusion 50 provided on the lower surface of the upper electrode 47 has a height of about 0.3 micrometer. Therefore, the distance from the tip of the protrusion 50 to the floating metal 49 is 0.7 micrometers.
- the membrane 4 4 is made of Cu (copper) with a thickness of 1.5 ⁇ m, and the input signal line 40, the output signal line 4 1, and the ground 4 2 have AI ( A single film with a thickness of 0.6 micrometers) is used.
- a photosensitive polyimide film is used for the sacrificial layer to form a membrane that floats in the hollow.
- the sacrificial layer is removed by wet stripping using a special stripper and carbon dioxide as the final step. A quick drying process was applied. 19
- the upper electrode 4 7 connected to the input signal line 40 is connected to the output signal line by applying a voltage between the input signal line 40 and the output signal line 41.
- a capacitor structure is formed by being attracted to the line 4 1 and in contact with the low-resistance metal film 49. At this time, the high-frequency signal input to the input signal line 40 flows to the output signal line 41 through this capacitor.
- a resistance element or the like for discharging the charge accumulated in the floating metal is not provided.
- the area ratio of the floating metal in the opposite region is as small as 15%, what is necessary for the element operation? It operates normally as a switch without causing any trouble.
- FIG. 11A shows a capacitive MEMS element according to the present invention described in the first embodiment as a high-frequency device equipped with a capacitive MES element according to the present invention.
- FIG. 7 is an equivalent circuit diagram of the MEMS element and the control circuit when applying (shown in FIG. B).
- a signal line 1 and an upper electrode 12 of the M E M S element are shown in a circuit form.
- FIGS. 12A and 12B are cross-sectional views of the MEMS element showing the up-down state of each membrane in this example. Each part in the cross-sectional view is indicated by the same reference numeral as that in the first embodiment.
- the upper electrode 12 of the MEMS element functions as the high-frequency switch 52 of the present invention connected in parallel to the signal line 1.
- Reference numerals 5 3 and 5 4 denote an input terminal and an output terminal for the signal line 1, respectively.
- the signal line 1, which is the lower electrode, floats in a DC manner, and the control terminal 5 5 is connected to the signal line 1 through an inductance L and a resistance R that exhibit high impedance to high frequencies. Is connected. That is, when a control DC voltage is applied to the control terminal 55, the DC voltage is applied to the signal line 1 via the inductance L and the resistance R.
- the upper electrode 12 In this switch-off state, the upper electrode 12 is in electrical contact with the floating metal 6, and therefore consists of the floating metal 6, the dielectric film 5 and the signal line 1 connected via the upper electrode 12. It constitutes a capacity evening. As a result, at high frequencies, signal line 1 is equivalent to being grounded. Therefore, most of the high-frequency signal flowing from the input terminal 5 3 to the signal line 1 is reflected at the portion where the floating metal 6 in contact with the upper electrode 12 2 is in contact with the dielectric film 5. Almost no reach.
- FIG. 11B shows a capacitive MEMS element having the series connection type according to the present invention described in the fifth embodiment (shown in FIG. 1 OA and FIG. 10B) similar to the above switch.
- the equivalent circuit diagram of the MEMS element and the control circuit when applied to is shown.
- An input signal line 40 and an output signal line 41 are shown in circuit form.
- Reference numerals 7 3, 7 4, and 7 5 indicate an input terminal, an output terminal, and a control terminal, respectively.
- the upper electrode 47 connected to the input signal line 40 functions as the high-frequency switch 72 of the present invention connected in series to the output signal line 41.
- the output signal line 41 is connected to the control terminal 75 via an inductance L and a resistance R that exhibit high impedance to high frequencies. That is, when a control DC voltage is applied to the control terminal 75, the DC voltage is applied to the output signal line 4 1 via the inductance L and the resistance R.
- the upper electrode 4 7 is sufficiently away from the output signal line 4 1, so the input signal is the output signal line 4 1 Not reach.
- the high frequency switch equipped with the capacitive MEMS element of the present invention can obtain extremely good switching characteristics for high frequency signals.
- a high-frequency device according to the eighth embodiment will be described.
- the capacitive MEMS element of the present invention described in the fourth embodiment switching that can switch one input signal to two paths
- FIG. 9A and Fig. 9B shows an equivalent circuit diagram of the MEMS element and control circuit. The same reference numerals in FIG. 13 are used for the same parts as those in FIGS. 9A and 9B.
- Reference numeral 24 denotes an input signal line
- reference numerals 25 and 26 denote a left output signal line and a right output signal line, respectively.
- Reference numeral 2 9 is a membrane
- 3 3 and 3 4 are left upper electrodes
- right upper electrodes 5 6 are input terminals
- 5 7 and 5 8 are output terminals
- 5 9 is a control terminal.
- the membrane 29 is not connected to the ground but is connected to the input terminal 56 via the input signal line 24. Then, the upper electrode 33 on the left side of the membrane 29 is connected to the output signal line 25 at a high frequency and connected to the output terminal 57, or the upper electrode 34 on the right side is connected to the output signal line 26. Is connected to the output terminal 58 at a high frequency.
- the output terminal 5 7 is DC 3 V via a resistor R 1 and an inductance L 1 that block high-frequency signals, while the output terminal 5 8 is a resistor R 2 and an inductance L that blocks high-frequency signals.
- Capacitance C 1 is used to ground the DC 3 V terminal at high frequency.
- the membrane 29 is floated in a DC manner by the capacitor C 2, and a control voltage is applied to the control terminal 59 via a resistor R 3 and an inductance L 3 that cut off a high-frequency signal. Therefore, when 5 V is applied to the control terminal 5 9, the input terminal 5 6 is connected to the output terminal 5 8 in terms of high frequency, and when 0 V is applied to the control terminal 5 9, it is connected to the output terminal 5 7.
- the feature of the applied capacitive MEMS element is 2004/011219
- a single push-pull type capacitive MEMS device realizes a 1-input 2-output switching switch with low loss and significantly reduced off-line signal wrapping due to excellent off-state isolation characteristics can do.
- FIG. 14 is a block diagram for explaining the ninth embodiment.
- a high frequency filter 94 is disposed on a substrate 9 1, and an antenna 96, and a connection part 9 2 to a reception system and a connection part 93 to a transmission system are connected to the opposite side.
- a switch is arranged at least in the front stage, the rear stage, or both the front and rear stages of the high frequency filter 94.
- a switch based on the form shown in the seventh embodiment of the present invention or a form mounted with a switch based on the form shown in the sixth embodiment is used.
- the good switching characteristics of the present invention can be obtained. Reflecting this, signals of multiple frequency bands received from the antenna are switched and input to the desired connection path with low loss and low noise. Conversely, signals of multiple frequency bands are low loss and It is possible to output with low noise. Furthermore, there is an advantage that the wraparound of the output signal to the input signal side can be significantly reduced.
- the high-frequency filter and the capacitive MEMS element of the present invention are formed on the same substrate material as that of the filter, because the capacitive MEMS element of the present invention can be manufactured by any general semiconductor manufacturing technology. There is an advantage that it can be manufactured and made into one chip together with other passive elements.
- logic IC composed of active elements such as Si-MOFS FE T that transmits a control signal from the control terminal can be fabricated on the same substrate and made into one chip for the same reason as described above.
- the capacitive M EMS element of the present invention can be manufactured on the same substrate using a general semiconductor manufacturing technique together with an active element and other passive elements.
- the capacitive MEMS element of the present invention in addition to the use as a switch as described above, one or a plurality of this element can be connected and arranged in parallel and in series to provide an SP n T switch. Needless to say, the present invention can also be applied to variable capacity devices capable of changing the capacitance values in a wide range.
- FIG. 15 shows an example of the method for manufacturing the M E M S element of the present invention.
- a lift-off two-layer resist pattern composed of an inverted pattern of the signal line 1 and the ground 2 is formed by using a photolithography technique. After this, using electron beam evaporation, deposit 0.05 ⁇ m of Ti on the first layer and 0.5 ⁇ m of Au (gold) on the second layer. . Then, unnecessary metal films and resists are removed using a known lift-off method to form a signal line 1 pattern and a ground 2 pattern ((a) in FIG. 15).
- pattern formation is performed using the well-known Kiso lithography technology. Thereafter, the alumina film in the unmasked region is removed by etching, and the dielectric film 5 pattern is formed only in the desired region ((b) in FIG. 15).
- a two-layer resist pattern for lift-off in which only a desired region on the signal line is opened is formed.
- use electron beam evaporation to deposit a 0.05-micrometer-thickness meter T i on the first layer and a 0.2-micrometer thick Au (gold) on the second layer.
- unnecessary metal films and resists are removed by using a known lift-off method to form a pattern of the floating metal 6 having a desired shape ((c) in FIG. 15).
- a two-layer resist pattern for lift-off in which only a desired region on the insulating substrate 3 is opened is formed. Thereafter, a high resistance film is deposited using an electron beam evaporation method. Then, by using a known lift-off method, unnecessary metal film and resist film are removed to form a resistance element 7 pattern having a desired shape ((d) in FIG. 15).
- the film thickness of the polyimide film was adjusted so that the film thickness after curing with high temperature baking was 1.2 micrometers ((e) in Fig. 15).
- an Au film having a thickness of 2.5 micrometers is deposited on the entire surface of the insulating substrate 3 by using a well-known electron beam evaporation method.
- the membrane 8 is formed using the well-known photolithography technique and Ar + ion milling method. ((F) in Fig. 15). PT / JP2004 / 011219
- the sacrificial layer 51 is removed by chemical dry etching to complete the capacitive MEMS element of the present invention ((g) in FIG. 15).
- a lead line pattern is formed from the floating metal, and the external resistive element or inductor element is formed at the element mounting stage. May be connected.
- a processing method most suitable for the metal material to be used such as a chemical dry etching method, a wet etching method, and a lift-off method, can be used. It goes without saying that it is good.
- the film thickness of the membrane was 2.5 ⁇ m.
- the film thickness does not cause bending in each metal material,
- the optimum film thickness varies depending on the deposition method and is not particularly limited.
- the material cost can be reduced by using the electrolytic Au plating method in which only a desired region is patterned by patterning with a photoresist or the like.
- the membrane using the AU in the manufacturing method, an example was shown in which only Au was deposited directly.
- several chromium, molybdenum, etc. were used as an adhesive layer with the adjacent layer. Adhesion can be improved by providing about nm to several tens of nm.
- the floating metal patterning which is the main component of the present invention, has been described with respect to an example of patterning using the multilayer resist technique and the lift-off method. However, when other methods such as AI are used, Needless to say, chemical dry etching, etching, etc. may be used.
- alumina film formed by sputtering is used as the dielectric film
- other methods generally used in the normal semiconductor manufacturing process such as a CVD method, may be used for the deposition method.
- the dielectric film material any material can be applied as long as it is a solid material having at least an insulating property and a dielectric constant, such as an alumina film, a silicon oxide film, a silicon nitride film, and tantalum oxide. Further, a laminated film of these dielectric materials may be used instead of a single film. The larger the dielectric constant, the easier the device can be miniaturized and the better the electrical characteristics when the membrane is lowered.
- the capacitive MEMS element of the present invention manufactured by the above manufacturing method is different from the conventional element in structure in that the area ratio of the floating metal in the opposing region is limited and the high-frequency signal is transmitted from the floating metal.
- the present invention has a great effect on the device characteristics with a small increase in the number of processes. That is, if the capacitive M E M S element of the present invention is manufactured according to the manufacturing method, a capacitive M E M S element having extremely good switching characteristics for a high frequency signal can be provided at a low price.
- An upper electrode connected to the panel and elastically deforming the panel to move above the substrate;
- a dielectric formed on a part of the lower electrode and a part of the substrate so as to cover at least a region wider than the upper electrode when viewed from the vertical direction of the substrate.
- a low-resistance metal film formed in contact with a part of the dielectric film located on the lower electrode and at least facing a part of the upper electrode;
- the area where only the dielectric film is formed is mixed, and the area of the area where the dielectric film and the low-resistance metal film are stacked in the area where the upper electrode and the lower electrode face each other is as follows.
- a capacitive MEMS element characterized by being equal to or smaller than the area of the region where the dielectric film is exposed in the region.
- An upper electrode connected to the panel and elastically deforming the panel to move above the substrate;
- a dielectric formed on a part of the lower electrode and a part of the substrate so as to cover at least a region wider than the upper electrode when viewed from the vertical direction of the substrate.
- a low-resistance metal film formed in contact with a part of the dielectric film located on the lower electrode and at least facing a part of the upper electrode;
- the upper electrode When a DC voltage is applied between the upper electrode and the lower electrode, the upper electrode is attracted downward by the electrostatic force generated between the upper electrode and the lower electrode facing each other, and the upper electrode Part of the low
- the upper electrode connected via the low-resistance metal film by electrically connecting the upper electrode and the low-resistance metal film in contact with a part of the anti-metal film, and the dielectric
- a capacitive MEMS element in which a capacitor structure composed of a body film and the lower electrode is formed
- the capacitive M E M S element wherein the low-resistance metal film is connected to a substance having a desired potential in a direct current manner through a substance that is resistant to a high-frequency signal.
- the substance that becomes a resistance to the high-frequency signal is an inductor that exhibits an impedance of at least 1 k ⁇ and less than 1 M ⁇ with respect to the high-frequency signal.
- the region where only the dielectric film according to claim 1 is formed is provided by an opening having a predetermined shape in the low-resistance metal film.
- the capacitive MEMMS device according to the item (8), wherein the metal body is formed of a single layer film containing at least copper or a laminated film of a copper-containing film and another metal film.
- the low-resistance metal film comprises a single-layer film containing at least gold, or a laminated film of a gold-containing film and another metal film.
- the low-resistance metal film is a single-layer film containing at least copper, or a laminated film of a copper-containing film and another metal film,
- the low-resistance metal film is a floating metal that is not connected to a high-frequency signal when no voltage is applied between the upper electrode and the lower electrode.
- Capacitive MEMS device as described in 4).
- a high-frequency device that is mounted on an on / off switch for high-frequency signals.
- a high-frequency device characterized in that the capacitive MEMS element described in the items (1) to (15) is mounted on a high-frequency signal output switching switch.
- a high-frequency device wherein the capacitive MEMS element described in the items (1) to (15) is mounted on a high-frequency filter module for a mobile phone.
- An upper electrode connected to the panel and elastically deforming the panel to move above the substrate;
- a dielectric formed on a part of the lower electrode and a part of the substrate so as to cover at least a region wider than the upper electrode when viewed from the vertical direction of the substrate.
- the area where only the dielectric film is formed is mixed, and the area of the area where the dielectric film and the low-resistance metal film are stacked in the area where the upper electrode and the lower electrode face each other is as follows.
- a method for manufacturing a capacitive MEMS element characterized in that it is equal to or smaller than the area of the region where only the dielectric film in the region is formed,
- Forming an anchor, the panel, and the upper electrode in an integrated structure by depositing and processing a metal film at a desired position on the substrate including the sacrificial film pattern;
- Capacitive type M E comprising a step of removing the sacrificial film
- the element of the present invention can be used as an electric signal switching element.
- it is useful for high-frequency signals, and a high-frequency device using the element can be provided. It is also possible to provide a method for manufacturing such an element.
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Abstract
Description
4011219 4011219
明 細 書 容量型 M E M S素子とその製造方法、 及び高周波装置 技術分野 Description Capacitance type M E M S element, manufacturing method thereof, and high frequency device Technical Field
本願発明は、 容量型 M E M S (Mi cro- El ectro-Mechanical Systems) 素子及びその製造方法に係わるものである。 更に、 本願発明の別な観 点は前記容量型 M E M S素子を搭載した高周波装置に関するものであ る。 尚、 容量型 M E M S素子は容量値を可変することによって高周波 の電気信号をオン/オフする素子である。 そして、 数メガヘルツから 数テラへルツの高周波の電気信号に対して有用である。 背景技術 TECHNICAL FIELD The present invention relates to a capacitive type MEMS (Micro-Electro-Mechanical Systems) element and a manufacturing method thereof. Furthermore, another aspect of the present invention relates to a high-frequency device equipped with the capacitive MEM S element. Capacitance type MEMS elements are elements that turn on / off high-frequency electrical signals by changing the capacitance value. It is useful for high-frequency electrical signals from several megahertz to several terahertz. Background art
従来、 電気信号を才ン オフする微細な電気機械部品として、 M E M S素子が知られている。 Conventionally, the M E M S element is known as a fine electromechanical component that turns off electrical signals.
特に高周波信号をオン/オフする高周波スィツチに適用された M E M S素子として、 例えば、 J. J. Yao., TOPICAL REVIEW "RF MEMS f rom a devi ce perspective. " J. Mi cromech. Mi croeng. 10 (2000) R9-R38. (特に、 R13, f igure5) (文献 1 ) に開示された容量型 (静電駆動型) M E M S 素子、 及び H. A. C, Ti Imams. , "RF - MEMS metal contact capac i t i ve swi tches. " 4th Round Tabl e on MINT for Space. 20/22 May, 2003 (ESTEC, Noordwi jk, NL. Page4-Page7) (文献 2 ) に開示された 容量型 M E M Sスィッチがある。 これらは、 電圧印加による上部電極 の上下運動によって上下電極間の容量値を変化させる機能を有してい る。 In particular, as a MEMS element applied to a high-frequency switch for turning on / off a high-frequency signal, for example, JJ Yao., TOPICAL REVIEW "RF MEMS fro a device perspective." J. Mi cromech. Mi croeng. 10 (2000) R9 -R38. (Especially R13, figure5) Capacitive (electrostatic drive) MEMS devices disclosed in (Reference 1), and HA C, Ti Imams., "RF-MEMS metal contact capaciti ve switches. "4 th Round Tabl e on MINT for Space. 20/22 may, 2003 (ESTEC, Noordwi jk, NL. Page4-Page7) is capacitive MEMS switch disclosed in (Reference 2). These have the function of changing the capacitance value between the upper and lower electrodes by the vertical movement of the upper electrode by voltage application.
'文献 1 に示された容量型 M E M S素子では、 基板上に形成された下 T JP2004/011219 'In the capacitive MEMS device shown in Reference 1, T JP2004 / 011219
2 部電極である信号線路上に薄い誘電体膜が形成されており、 信号線路 の両側には接地線が平行に形成されている。 そして、 その接地線には 金属のアンカ、 バネ、 及び上部電極の一体構造からなるメンプレンが 電気的に接綺されている。 そして、 このメンプレンは信号線路上に形 成された誘電体膜に対して空間を設けて垂直に跨ぐかたちで形成され ている。 A thin dielectric film is formed on the signal line, which is a two-part electrode, and ground lines are formed in parallel on both sides of the signal line. The ground wire is electrically connected with a membrane composed of a metal anchor, spring, and upper electrode. This membrane is formed in such a way that a space is provided vertically across the dielectric film formed on the signal line.
文献 2に示された構造の特徴として、 上部電極の下方に位置する下 部電極上の誘電体膜上に、 フローティングメタルと呼ばれる金属膜が 形成されている。 As a feature of the structure shown in Document 2, a metal film called a floating metal is formed on the dielectric film on the lower electrode located below the upper electrode.
素子の基本動作は、 次の通りである。 前記 2種類の M E M S素子で は、 上部電極として機能するメンブレンと下部電極である信号線路と の間に直流電圧が印加されないときは、 メンブレンと信号線路上に形 成された誘電体膜との間の空間によって、 スィツチ動作としてはオン (メンプレンアップ) 状態になっており、 入力された信号は出力端へ 到達する。 直流電圧が印加されると、 メンブレンと信号線路との間の 電位差によって生じる静電気力 (即ち、 クーロン力) によって、 メン プレンが信号線路側に引き付けられ、 弾性変形して基板側に曲がる。 そして、 例えば、 文献 1 の容量型 M E M S素子では、 上部電極部は信 号線路上の誘電体膜に接触するかたちとなり、 一方、 文献 2の容量型 M E M Sスィッチでは、 上部電極部は誘電体膜上に形成されたフロー ティングメタルに接触するかたちとなる。 The basic operation of the element is as follows. In the above-mentioned two types of MEMS elements, when no DC voltage is applied between the membrane functioning as the upper electrode and the signal line as the lower electrode, it is between the membrane and the dielectric film formed on the signal line. Depending on the space, the switch operation is on (membrane up), and the input signal reaches the output terminal. When a DC voltage is applied, the membrane is attracted to the signal line side by the electrostatic force (that is, Coulomb force) generated by the potential difference between the membrane and the signal line, and elastically deforms and bends to the substrate side. For example, in the capacitive MEMS element of Reference 1, the upper electrode is in contact with the dielectric film on the signal line, while in the capacitive MEMS switch of Reference 2, the upper electrode is on the dielectric film. It will be in contact with the formed floating metal.
それによつて、 前記の 2つの構造とも、 メンプレンと誘電体膜、 及 び信号線路からなるキャパシダ構造が形成されるため、 スィツチ動作 としてはオフ (メンプレンダウン) 状態になる。 この状態では、 入力 された信号は出力端へ到達できなくなる。 しかし、 文献 2に開示され た構造では、 誘電体膜上に密着して形成されたフローティングメタル 11219 As a result, the capacitor structure including the membrane, the dielectric film, and the signal line is formed in both of the two structures, so that the switch operation is in the off (membrane down) state. In this state, the input signal cannot reach the output end. However, in the structure disclosed in Reference 2, the floating metal formed in close contact with the dielectric film 11219
3 の効果により、 文献 1 の構造よリもオフ状態での容量値は安定した高 い値が得られる。 この為、 文献 2の構造は、 高周波信号に対するスィ ツチング特性において、 文献〗 の素子よりも良好な特性が得られる特 徴がある。 Due to the effect of 3, the capacitance value in the off state can be obtained in a stable and high value as compared with the structure of Reference 1. For this reason, the structure of Document 2 has a characteristic that a switching characteristic for a high-frequency signal is better than that of the element of Document IV.
尚、 前記方式の M E M S素子は、 容量型 M E M S素子 (スィッチ) という呼び名のほか、 その動作原理から静電駆動型 M E M S素子 (ス イッチ) とも呼ばれている。 本願明細書での以下の説明では、 前記複 数の呼び名の素子は、 特に断りがない場合は同一のものとする。 In addition, the M E M S element of the above-mentioned method is called a capacitive M E M S element (switch) as well as an electrostatic drive type M E M S element (switch) because of its operating principle. In the following description of the present specification, the elements having the plural names are the same unless otherwise specified.
M E M Sスィッチには、 信号線に対して直列に M E M S素子を接続 したシリーズ接続型スィッチと、 並列に接続したシャン卜型スィッチ がある。本明細書では、特に断らない限りシャン卜型を例に説明する。 本願発明がいずれの型のスィツチにも用いることが出来ることはいう までもない。 発明の開示 There are two types of M E M S switches: a series connection type switch that connects M E M S elements in series with the signal line, and a shunt type switch that is connected in parallel. In this specification, a shaver type will be described as an example unless otherwise specified. It goes without saying that the present invention can be used for any type of switch. Disclosure of the invention
本発明の主たる目的は、 高周波信号に対して良好且つ安定したスィ ツチング特性が得られ、 更には低電圧で動作する容量型 M E M S素子 及びその製造方法を提供することにある。 更には、 本発明の容量型 M E M S素子を搭載した高性能な高周波装置を提供することにある。 A main object of the present invention is to provide a capacitive M E M S element which can obtain a good and stable switching characteristic for a high-frequency signal and which operates at a low voltage, and a method for manufacturing the same. Furthermore, another object of the present invention is to provide a high-performance high-frequency device equipped with the capacitive M E M S element of the present invention.
本願発明の容量型 M E M S素子の主な形態は次の通りである。即ち、 絶縁性基板と、 前記絶縁性基板上に形成された下部電極と、 前記下部 電極上に形成された誘電体層と、 前記誘電体層上に形成された導体層 と、 上部電極を有する。 この上部電極は前記下部電極に対向し且つ少 なくとも前記誘電体層上の導体層と間隙を有して配置され、 且つ前記 誘電体層上の導体層への接触■非接触の制御がなされる。 The main forms of the capacitive M E M S element of the present invention are as follows. An insulating substrate; a lower electrode formed on the insulating substrate; a dielectric layer formed on the lower electrode; a conductor layer formed on the dielectric layer; and an upper electrode. . The upper electrode faces the lower electrode and is disposed at least with a gap from the conductor layer on the dielectric layer, and contact with the conductor layer on the dielectric layer is controlled. The
そして、 本願発明では、 前記誘電体層上の導体層は、 前記絶縁性基 2004/011219 And in this invention, the conductor layer on the said dielectric material layer is the said insulating group. 2004/011219
板の垂直方向から見て、 前記上部電極と前記下部電極とが対向する領 域において、 その対向面積の一部に当該誘電体層上の導体層が存在す るように形成され、 且つ前記上部電極と前記下部電極とが対向する領 域における前記誘電体層上の導体層が存在する領域の面積が、 当該対 向領域における前記誘電体層上の導体層が存在せざる領域の面積と等 しいか小さいことが肝要である。 In a region where the upper electrode and the lower electrode face each other when viewed from the vertical direction of the plate, a conductor layer on the dielectric layer exists in a part of the facing area, and the upper electrode The area of the region where the conductor layer on the dielectric layer exists in the region where the electrode and the lower electrode face each other is the area of the region where the conductor layer on the dielectric layer does not exist in the opposite region, etc. It is important to be small or small.
更に、本願発明の容量型 M E M S素子の別な形態は次の通りである。 即ち、 絶縁性基板と、 前記絶縁性基板上に形成された下部電極と、 前 記下部電極上に形成された誘電体層と、 前記誘電体層上に形成された 導体層と、 上部電極を有する。 この上部電極は、 前記下部電極に^向 し且つ少なくとも前記誘電体層上の導体層と間隙を有して配置され、 且つ前記誘電体層上の導体層への接触 ·非接触の制御がなされる。 そ して、 前記誘電体層上の導体層は、 高周波信号に対する抵抗体を介し て所望電位に直流的に接続されていることが肝要である。 Furthermore, another form of the capacitive M E M S element of the present invention is as follows. An insulating substrate; a lower electrode formed on the insulating substrate; a dielectric layer formed on the lower electrode; a conductor layer formed on the dielectric layer; and an upper electrode. Have. The upper electrode is disposed so as to face the lower electrode and at least have a gap with the conductor layer on the dielectric layer, and contact / non-contact with the conductor layer on the dielectric layer is controlled. The It is important that the conductor layer on the dielectric layer is connected to a desired potential in a direct current manner through a resistor for high-frequency signals.
更に、 本願発明の別な観点は、 前記諸容量型 M E M S素子を有する 高周波装置を提供するものである。 図面の簡単な説明 Furthermore, another aspect of the present invention is to provide a high-frequency device having the various capacitance type M E M S elements. Brief Description of Drawings
第 1 A図は、 本発明に係る容量 M E M S素子の第 1 の実施形態を説 明するための平面図である。 FIG. 1A is a plan view for explaining a first embodiment of a capacitor MEMS element according to the present invention.
第 1 B図は、 第 1 A図における B— B ' 線による断面図である。 FIG. 1B is a sectional view taken along line BB ′ in FIG. 1A.
第 2 A図は、 従来技術の課題を解決する他の手段を説明するための 平面図である。 FIG. 2A is a plan view for explaining another means for solving the problems of the prior art.
第 2 B図は、 第 2 A図における B— B ' 線による断面図である。 FIG. 2B is a sectional view taken along line BB ′ in FIG. 2A.
第 3 A図は、 従来の容量型 M E M S素子を説明するための平面図で ある。 第 3 B図は、 第 3 A図における B— B ' 線による断面図である。 第 4 A図は、 従来の容量型 M E M S素子を説明するための上面図で ある。 FIG. 3A is a plan view for explaining a conventional capacitive MEMS element. FIG. 3B is a sectional view taken along line BB ′ in FIG. 3A. FIG. 4A is a top view for explaining a conventional capacitive MEMS element.
第 4 B図は、 第 4 図にぉける 8— 8, 線による断面図である。 第 5図は、 従来技術の課題を解決する手段を説明する為の平面図で ある。 Fig. 4B is a cross-sectional view taken along line 8-8 in Fig. 4. FIG. 5 is a plan view for explaining means for solving the problems of the prior art.
第 6図は、 従来技術の課題を解決する他の手段を説明する為の平面 図である。 FIG. 6 is a plan view for explaining another means for solving the problems of the prior art.
第 7 A図は、 本発明に係る容量 M E M S素子の第 1 の実施形態を説 明するための平面図である。 FIG. 7A is a plan view for explaining the first embodiment of the capacitor M EMS element according to the present invention.
第 7 B図は、 第 7 図にぉける已— 8 ' 線による断面図である。 第 8図は、本発明の第 3の実施形態を説明するための平面図である。 第 9 A図は、 本発明に係る容量 M E M S素子の第 4の実施形態を説 明するための平面図である。 Fig. 7B is a cross-sectional view taken along line 8-8 'in Fig. 7. FIG. 8 is a plan view for explaining a third embodiment of the present invention. FIG. 9A is a plan view for explaining a fourth embodiment of the capacitor MEMS element according to the present invention.
第 9 B図は、 第 9 図にぉける 8— 8 ' 線による断面図である。 第 9 C図は、 第 9 A図の例のメンブレンの構造を説明する概略斜視 図である。 FIG. 9B is a sectional view taken along line 8-8 ′ in FIG. FIG. 9C is a schematic perspective view for explaining the structure of the membrane in the example of FIG. 9A.
第 1 O A図は、 本発明に係る容量 M E M S素子の第 5の実施形態を 説明するための平面図である。 FIG. 1 O A is a plan view for explaining a fifth embodiment of the capacitor M E M S element according to the present invention.
第 1 0 8図は、第 1 O A図における B— B '線による断面図である。 第 1 1 A図は、 第 6の実施形態の制御回路の等価回路図である。 第 1 1 B図は、 第 7の実施形態の制御回路の等価回路図である。 第 1 2 A図は、 第 6の実施形態での、 メンブレムのアップの状態を 示した断面図である。 FIG. 108 is a cross-sectional view taken along line BB ′ in FIG. FIG. 11A is an equivalent circuit diagram of the control circuit of the sixth embodiment. FIG. 11B is an equivalent circuit diagram of the control circuit of the seventh embodiment. FIG. 12A is a cross-sectional view showing the membrane in an up state in the sixth embodiment.
第 1 2 B図は、 第 6の実施形態での、 メンブレムのダウンの状態を 示した断面図である。 T JP2004/011219 FIG. 12B is a cross-sectional view showing the membrane in a down state in the sixth embodiment. T JP2004 / 011219
6 第 1 3図は、 第 8の実施形態に用いた制御回路の説明用等価回路図 である。 6 FIG. 13 is an equivalent circuit diagram for explaining the control circuit used in the eighth embodiment.
第 1 4図は、 第 9の実施形態を説明するためのブロック図である。 第 1 5図は、 第 1 の実施形態の容量型 M E M S素子の製造工程例を 示す断面図である。 発明を実施するための最良の形態 FIG. 14 is a block diagram for explaining the ninth embodiment. FIG. 15 is a cross-sectional view showing an example of the manufacturing process of the capacitive M EMS element according to the first embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
<問題点の考察 > <Consideration of problems>
発明を実施するための諸形態を具体的に説明するに先立って、 これ までの容量型 M E M S素子に関して、 発明者らが見出した問題点を説 明、 考察する。 Prior to concrete description of various embodiments for carrying out the invention, the problems found by the inventors will be explained and discussed with respect to the conventional capacitive MEMS element.
本発明者等は、 先ず、 文献 1 の構造とほぼ同等の構造を有する容量 型 M E M S素子を試作して、 前記と同様のスィツチ動作 (オン/オフ) 時における容量の絶対値及び容量比を評価した。 The inventors first made a prototype of a capacitive MEMS device having a structure substantially equivalent to that of Document 1, and evaluated the absolute value and the capacitance ratio of the capacitor during the switch operation (on / off) as described above. did.
この時試作した容量型 M E M S素子は、 第 3 A図、 第 3 B図に示し た構造である。 第 3 A図は素子の平面図、 第 3 B図は断面図である。 絶縁基板 3の上部に信号線路 1 が設けられる。 これを囲んで接地線 The prototype capacitive M E M S element at this time has the structure shown in Fig. 3A and Fig. 3B. FIG. 3A is a plan view of the element, and FIG. 3B is a sectional view. A signal line 1 is provided on the insulating substrate 3. Surround this with the ground wire
2が配置される。 この信号線路 1 を覆って誘電体膜 5が形成される。 接地線 2に接触しながら、 前記誘電体膜 5と間隙 8 0を保って上部電 極 1 2が設けられる。 尚、 上部電極 1 2の両端部にパネ 1 1 が形成さ れている。 上部電極 1 2、 パネ 1 1 、 及びパネに接続されるアンカ 12 is arranged. A dielectric film 5 is formed so as to cover the signal line 1. An upper electrode 12 is provided while maintaining a gap 80 with the dielectric film 5 while being in contact with the ground wire 2. Panels 1 1 are formed at both ends of the upper electrode 12. Upper electrode 1 2, panel 1 1, and anchor 1 connected to panel
0で構成される部材をメンブレン 8と称する。 The member composed of 0 is called membrane 8.
メンプレン 8は、 接地線 2 1 (以降 「アース」 と称する) に接続さ れたアンカ 1 0、 ミアンダ (曲折構造) を有するパネ 1 1 、 及び上部 電極 1 2がー体構造を成している。 メンブレン 8の下方の基板 ( 3 ) 上に接して形成された下部電極である信号線路 1 と上部電極 1 2との 04 011219 Membrane 8 has an anchor 10 connected to a grounding wire 21 (hereinafter referred to as “earth”), a panel 11 1 having a meander (bending structure), and an upper electrode 12 having a body structure. . The signal line 1 and the upper electrode 12, which are lower electrodes formed in contact with the substrate (3) below the membrane 8, 04 011219
7 対向領域 (垂直方向から見て上部電極と下部電極の両者が重なった領 域: 以降、 特に断りが無い場合には単に 「対向領域」 と略す) の面積 は、 2 0 0マイクロメータ X 2 0 0マイクロメ一夕である。 7 The area of the opposing area (the area where both the upper and lower electrodes overlap when viewed from the vertical direction: hereinafter simply referred to as “opposing area” unless otherwise noted) is 2 0 0 micrometer X 2 0 0 It's a micro-meat.
上部電極 1 2 /誘電体膜 5間の空間 8 0の距離は約 1 . 3マイクロ メータで、 下部電極である信号線路 1 上の一部及び絶縁基板 3上の一 部に形成された誘電体膜 5の材料には、膜厚が 0 . 3マイクロメータの アルミナ膜を用いた。 The distance of the space 80 between the upper electrode 12 / dielectric film 5 is about 1.3 micrometers, and a dielectric formed on a part of the lower electrode signal line 1 and part of the insulating substrate 3 As the material of the film 5, an alumina film having a film thickness of 0.3 micrometers was used.
メンブレン 8には、 膜厚が 2 . 5マイクロメータの A u (金) を用い ており、 一方、 下部電極である信号線路 1 とメンブレン 8に接続され た接地線 2には下層 Τ ί (膜厚が 0 . 0 5マイクロメータ) との上層 A u (金、 膜厚が 0 . 5マイクロメ一夕) の積層膜を用いた。 The membrane 8 is made of Au (gold) with a film thickness of 2.5 micrometers. On the other hand, the signal line 1 which is the lower electrode and the ground wire 2 connected to the membrane 8 are connected to the lower layer. A laminated film of an upper layer A u (gold, film thickness of 0.5 μm) with a thickness of 0.5 μm) was used.
又、 製造プロセス途中では、 中空に浮いたメンブレン 8を形成する ために、 後に除去することとなる犠牲層パターンをメンプレン下に形 成している。 この犠牲層の除去を容易にするために、 図示していない が、上部電極 Ί 2には 1 0マイクロメータ口の穴が 2 0マイクロメータ 間隔で複数箇所設けられている。 犠牲層に関しては後述される。 In the middle of the manufacturing process, a sacrificial layer pattern to be removed later is formed under the membrane to form a membrane 8 that floats in the air. In order to facilitate the removal of the sacrificial layer, although not shown, the upper electrode 2 is provided with a plurality of 10-micrometer hole holes at intervals of 20 micrometers. The sacrificial layer will be described later.
犠牲層に用いられる材料としては、 一般に酸化シリコン膜、 ホ卜レ ジス卜膜、 ポリイミ ド膜等があるが、 前記容量型 M E M S素子の作製 にはポリィミ ド膜を用いた。 As materials used for the sacrificial layer, there are generally a silicon oxide film, a photoresist film, a polyimide film, and the like, but a polyimide film was used for the production of the capacitive MEMS element.
前記構造の容量型 M E M S素子を用いて、 信号線路 1 に 0 Vから 徐々に印加電圧を上げていった (尚、 アース 2は接地されている) 結 果、 アース 2に接続された上部電極 1 2 /信号線路である下部電極 1 間に電圧を印加していない (0 V : 即ち、 メンブレンアップ) 時に得 られた容量値 (約 0 . 5 p F ) に対して、 上部電極 1 2 Z下部電極 1 間に直流電圧を 6 V印加して、 上部電極 1 2が下部電極 1 の方向に引 き付けられて誘電体膜 5に接触 (メンプレンダウン) しても、 容量値 2004/011219 Using the capacitive MEMS element with the above structure, the voltage applied to signal line 1 was gradually increased from 0 V (where earth 2 was grounded). As a result, upper electrode 1 connected to earth 2 2 / For the capacitance value (about 0.5 p F) obtained when no voltage is applied between the lower electrode 1 that is the signal line (0 V: membrane up), the upper electrode 1 2 Z lower Even if a DC voltage of 6 V is applied between the electrodes 1 and the upper electrode 1 2 is attracted in the direction of the lower electrode 1 and comes into contact with the dielectric film 5 (membrane down), the capacitance value 2004/011219
8 は約 3倍程度の値 (約 1 . 6 p F ) にしか増大しなかった。 8 increased only to about three times the value (about 1.6 pF).
前記容量型 M E M S素子の動作に関して、 シミュレーションによる 計算では、 上部電極 1 2が誘電体膜 5に完全に接する (メンプレンダ ゥン) ことにより、 メンブレンアップ時 (即ち、 0 V時点) よりも容 量値が約 5 0倍程度増大する結果が得られているにもかかわらず、 実 際の試作では上述の通り容量値増加は極めて小さかった。 Regarding the operation of the capacitive MEMS element, in the calculation by simulation, the upper electrode 12 is completely in contact with the dielectric film 5 (membrane), so that the capacitance value is higher than when the membrane is up (ie, at 0 V). However, as described above, the increase in the capacitance value was extremely small in the actual prototype.
この原因を調査したところ、 上部電極 1 2が誘電体膜 5に完全に接 する電圧を印加した場合でも、 両者の間には僅かな隙間 (エアギヤッ プ) が生じていることが判明した。 As a result of investigating the cause, it was found that even when a voltage in which the upper electrode 12 was completely in contact with the dielectric film 5 was applied, a slight gap (air gap) was generated between them.
即ち、 このエアギャップにより、 上部/下部電極間に低誘電領域が 形成されて容量値が小さくなってしまったものと考えられる。 That is, it is considered that the capacitance value is reduced due to the formation of a low dielectric region between the upper and lower electrodes due to the air gap.
一方、 文献 2に開示された構造についても実際に試作し、 前記と同 様の電圧印加時における容量の絶対値及び容量比.を評価した。 On the other hand, the structure disclosed in Document 2 was also prototyped, and the absolute value of capacitance and the capacitance ratio when a voltage similar to that described above was applied were evaluated.
この時試作した容量型 M E M S素子は第 4 A図、 第 4 B図に示した 構造である。 第 4 A図は素子の平面図、 第 4 B図は線 B B ' での断面 図である。 The prototype capacitive M E M S element at this time has the structure shown in Figs. 4A and 4B. FIG. 4A is a plan view of the element, and FIG. 4B is a cross-sectional view taken along line B B '.
絶縁基板 3の上部に下部電極となる信号線路 1 が設けられる。 この 信号線路 1 を囲んで接地線 2が配置される。 本例では、 この誘電体膜 5の上にフローティングメタル (フロー卜状態の金属膜) 6が配置さ れている。 接地線 2に接触しながら、 前記フローティングメタル 6及 び誘電体膜 5と間隙 8 0を保って上部電極 1 2が設けられる。 尚、 上 部電極 1 2の両端部にバネ 1 1 及びパネに接続されるメンブレン 8が 形成される。 メンブレン 8は上部電極 1 2、 バネ 1 1 、 及びアンカ Ί 0で構成される。 A signal line 1 serving as a lower electrode is provided on the insulating substrate 3. A grounding wire 2 is disposed around the signal line 1. In this example, a floating metal (a metal film in a flow 卜 state) 6 is disposed on the dielectric film 5. An upper electrode 12 is provided in contact with the ground line 2 while maintaining a gap 80 with the floating metal 6 and the dielectric film 5. In addition, the membrane 8 connected to the spring 11 and the panel is formed at both ends of the upper electrode 12. The membrane 8 is composed of an upper electrode 1 2, a spring 1 1, and an anchor 0.
本例は、 前記第 3 A図、 第 3 B図で示した構造に、 定常時は電気的 にどこにも接続されていないフローティングメタル 6を形成したもの である。 本例では、 この金属膜 6は、 対向領域 8 1 内の誘電体膜 5上 に、 膜厚が 1 0 0ナノメ一トルの A u (金) 膜とした。 In this example, the structure shown in FIGS. 3A and 3B is formed with a floating metal 6 that is not electrically connected to anywhere at all times. It is. In this example, the metal film 6 is an Au (gold) film having a thickness of 100 nm on the dielectric film 5 in the facing region 8 1.
このフローティングメタル 6の面積は、 前記両電極の対向領域 8 1 よりも小さく、 寸法を 1 8 0マイクロメータ X 1 8 0マイクロメ一夕 とした。 形成した位置としては、 対向領域 8 1 の外周部 4辺からそれ ぞれ 1 0マイクロメータ内側の領域まで覆われている。 The area of the floating metal 6 was smaller than the opposing region 8 1 of the two electrodes, and the dimensions were 1800 micrometers × 180 micrometers. The positions formed are covered from the outer peripheral four sides of the opposing area 8 1 to the area inside 10 micrometers each.
前記構造の容量型 M E M S素子を用いて評価した結果、 上部電極 1 As a result of evaluation using the capacitive M E M S element having the above structure, the upper electrode 1
2 Z下部電極 1 間に直流電圧を印加して、 上部電極 1 2が下部電極 1 方向に引き付けられてフローティングメタル 6に接触 (メンプレンダ ゥン) させた時に、 容量値が 2 4 p F ( 0 V時の約 5 0倍) という極 めて高い容量値を示した。 2 When a DC voltage is applied between the Z lower electrode 1 and the upper electrode 1 2 is attracted in the direction of the lower electrode 1 and brought into contact with the floating metal 6, the capacitance value is 2 4 p F (0 The capacitance value was extremely high (about 50 times that at V).
しかし、 動作電圧としては約 2 0 Vという前記フローティングメタ ル 6がない場合の約 3倍以上の高い電圧を必要とした。 更に、 何回か 前記メンプレンの上下動を繰り返させた後、 前記 2 0 Vの電圧をかけ たまま数秒間放置すると、 上部./下部電極間の容量値が初期値 ( 0 . However, an operating voltage of about 20 V, which is about 3 times higher than that without the floating metal 6, is required. Furthermore, after repeating the up-and-down movement of the membrane several times and leaving it to stand for several seconds while applying the voltage of 20 V, the capacitance value between the upper and lower electrodes becomes the initial value (0.
5 p F程度) に戻ってしまう現象が発生した。 The phenomenon of returning to about 5 pF occurred.
更に、 この状態から、 印加電圧を 0 Vに戻すと、 また容量値は 2 0 Furthermore, when the applied voltage is returned to 0 V from this state, the capacitance value is 2 0
P F以上にまで増大するが、 数秒の後に初期値 ( 0 . 5 p F程度) に 戻る、 という不可解な現象も起こった。 There was also a mysterious phenomenon that increased to P F or more, but returned to the initial value (about 0.5 p F) after a few seconds.
以上のことから、 上述のフローティングメタル 6を備えた容量型 M From the above, capacitive type M with the above-mentioned floating metal 6
E M S素子は、 特に数百メガヘルツ以上の高周波信号を扱う高周波ス イッチに適用した場合、 素子の動作に高電圧を要し、 且つ極めて不安 定なスイッチング特性しか得られないことが判明した。 It has been found that the EMS element requires a high voltage for the operation of the element and can provide extremely unstable switching characteristics, particularly when applied to a high-frequency switch that handles high-frequency signals of several hundred megahertz or more.
<本願発明と現象の考察 > <Consideration of Invention and Phenomenon>
本発明の骨子は、 前述した通り、 導体層からなるフローティングメ タルを備えた容量型 M E M S素子において、 対向領域内における導体 層 (フローティングメタル) の面積比率を、 対向領域全体の 5 0 %以 下 (それ以外は誘電体膜露出領域) にすることにある。 As described above, the essence of the present invention is a capacitive MEMS element having a floating metal made of a conductor layer. The area ratio of the layer (floating metal) should be 50% or less of the entire opposing region (otherwise the dielectric film exposed region).
更に、 上記問題を解決する別な手段は、 前記導体層 (フローテイン グメタル) を、 高周波信号に対して抵抗となる物質を介して、 所望の 電位を有する物質と直流的に接続することである。 この時、 前記高周 波信号に対して抵抗となる物質は、少なくとも〗 k Ω以上で 1 M Ω未満 の電気抵抗値を示す抵抗体や、高周波信号に対して少なくとも 1 ί< Ω以 上で〗 Μ Ω未満のインピーダンスを示すィンダクタであることが望ま しい。 Furthermore, another means for solving the above problem is to connect the conductor layer (floating metal) in a direct current manner with a substance having a desired potential through a substance that becomes a resistance to a high-frequency signal. . At this time, the substance that becomes a resistance to the high-frequency signal is a resistor that exhibits an electrical resistance value of at least〗 kΩ and less than 1 MΩ, and a high-frequency signal that is at least 1 ° <Ω or more. It is desirable that the inductor has an impedance of less than Ω.
前記所望の電位を有する物質は、 素子の構造にもよるが、 前記上部 電極、 接地領域 (アース)、 直流電圧を印加して前記上部電極の上下動 を制御する制御電極、 の群のうち何れか一つであることが素子作製を 容易にする上でも望ましい。 このことによって、 基本的にチヤ一ジァ ップを防止するものである。 Depending on the structure of the element, the substance having the desired potential may be any of the group consisting of the upper electrode, a ground region (ground), and a control electrode that controls the vertical movement of the upper electrode by applying a DC voltage. It is also desirable to facilitate the device fabrication. In this way, it is fundamentally possible to prevent a tipping.
フローティングメタルのパターン形状は、 特に、 特定の形状に限定 するものではなく、 前記対向領域における面積比率が守られるのであ れば、 例えば、 パターン内部に所定の形状を有する開口部を設けるこ とによって、 前記誘電体膜の露出領域を確保しても構わない。 The pattern shape of the floating metal is not particularly limited to a specific shape. For example, by providing an opening having a predetermined shape inside the pattern as long as the area ratio in the facing region is protected. The exposed region of the dielectric film may be secured.
又、 前記パネと前記アンカと前記上部電極は、 一体構造を成し、 且 つ連続した金属体によって形成されていることが望ましい。 Further, it is desirable that the panel, the anchor, and the upper electrode have an integral structure and are formed of a continuous metal body.
前記金属体は、 少なくとも低抵抗な金属材料を主体とした物質によ つて形成されていることが好ましく、 例えばアルミニウムを含む単層 膜、 もしくはアルミニウム含有膜と他の金属膜との積層膜や、 金を含 む単層膜、 もしくは金含有膜と他の金属膜との積層膜、 銅を含む単層 膜、 もしくは銅含有膜と他の金属膜との積層膜、 の何れか一つによつ て形成されていることが望ましい。 T JP2004/011219 The metal body is preferably formed of a substance mainly composed of at least a low-resistance metal material. For example, a single-layer film containing aluminum, a laminated film of an aluminum-containing film and another metal film, According to any one of a single-layer film containing gold, or a laminated film of a gold-containing film and another metal film, a single-layer film containing copper, or a laminated film of a copper-containing film and another metal film It is desirable that it be formed. T JP2004 / 011219
11 又、 前記誘電体膜上の導体層についても、 例えばアルミニウムを含 む単餍膜、 もしくはアルミニウム含有膜と他の金属膜との積層膜や、 金を含む単層膜、 もしくは金含有膜と他の金属膜との積層膜、 銅を含 む単層膜、 もしくは銅含有膜と他の金属膜との積層膜、 の何れか一つ によって形成されていることが望ましい。 即ち、 一般に、 低抵抗な金 属材料を主体とした物質によって形成されていることが好ましい。 11 For the conductor layer on the dielectric film, for example, a single-layer film containing aluminum, a laminated film of an aluminum-containing film and another metal film, a single-layer film containing gold, or a gold-containing film It is desirable that the film is formed of any one of a laminated film with another metal film, a single-layer film containing copper, or a laminated film of a copper-containing film and another metal film. That is, in general, it is preferably formed of a substance mainly composed of a low-resistance metal material.
前記の従来技術で示した高電圧動作に関して考察すると、 まず静電 気力によって上部電極が下部電極方向に引き付けられるためには、 静 電気力は上部電極が連接されているパネの復元力よりも大きくならな ければならない。 Considering the high voltage operation shown in the above prior art, first, the electrostatic force is greater than the restoring force of the panel to which the upper electrode is connected in order for the upper electrode to be attracted toward the lower electrode by electrostatic force. Must be.
しかし、 前記構造のように下部電極上に誘電体膜を介してフローテ イングメタルを設けたものでは、 その領域における下部電極からの静 電気力はフローティングメタルに強く働きかける (フローティングメ タルも上部電極と同じ電位 :即ち、 0 V ) ように作用する。 However, in the case where a floating metal is provided on the lower electrode via a dielectric film as in the above structure, the electrostatic force from the lower electrode in that region strongly acts on the floating metal (the floating metal is also connected to the upper electrode). Same potential: ie 0 V).
そして、 直流電圧を印可し続けることによって、 フローティングメ タルにも徐々に電荷が蓄積されていくため、 フローティングメタルと フローティングメタル上に位置する上部電極との間の電位差が生じ始 める。 そして、 その間の電位差が増大していくのに従って、 その間で 発生する静電気力も増大していき、 上部電極はフローティングメタル に引き付けられるようになる。 As the DC voltage is continuously applied, electric charges are gradually accumulated in the floating metal, so that a potential difference between the floating metal and the upper electrode located on the floating metal starts to occur. And as the potential difference between them increases, the electrostatic force generated between them increases, and the upper electrode is attracted to the floating metal.
この時、 フローティングメタルとフローティングメタル上に位置す る上部電極との間で発生する静電気力が、 フローティングメタルに電 荷が蓄積されて上部電極を引き付けることが可能となるまでに、 電圧 印加を開始した時から若干の時間差が生じる。 At this time, voltage application starts until the electrostatic force generated between the floating metal and the upper electrode located on the floating metal accumulates the charge on the floating metal and can attract the upper electrode. There will be a slight time difference from
このため、 電圧印加直後のフローティングメタルと上部電極との間 の広い対向領域では、 極めて弱い静電気力しか生じていない。 12 例えば、 1 秒以下の短い時間で電圧切り替え操作を行って上部電極 を上下動させるためには、 即ち弱い静電気力を発生する広いェリアを 含めた対向領域全体の静電気力が、 パネの復元力よりも大きくなるた めには、主にフローティングメタルが存在しない外周部の狭い領域(強 い静電気力発生) で引き付けるようにしなければならない。 この時、 前記フローティングメタル領域でも弱い静電気力は生じている。 その 結果前記フローティングメタルがない構造よリも高い電圧が必要とな り、 前記の従来構造を有する素子の動作に 2 0 Vもの高い電圧が必要 になってしまったものと考えられる。 For this reason, only a very weak electrostatic force is generated in the wide opposing region between the floating metal and the upper electrode immediately after voltage application. 12 For example, in order to move the upper electrode up and down by performing a voltage switching operation in a short time of 1 second or less, the electrostatic force of the entire opposing area including the wide area that generates weak electrostatic force In order to be larger than this, it must be attracted mainly in the narrow area of the outer periphery where there is no floating metal (generation of strong electrostatic force). At this time, a weak electrostatic force is also generated in the floating metal region. As a result, a voltage higher than that of the structure without the floating metal is required, and it is considered that a voltage as high as 20 V is required for the operation of the element having the conventional structure.
次に、 本願発明の係わる容量値の挙動に関する不可解な現象につい て考察する。 Next, the mysterious phenomenon related to the behavior of the capacitance value according to the present invention will be considered.
前記のように上部電極/下部電極間で 2 0 Vもの直流電圧を印加し て、 上部電極がフローティングメタルに直接接触するようになると、 今度は上部電極がフローティングメタルと同様に電荷を蓄積しはじめ る。 As described above, when a DC voltage of 20 V is applied between the upper electrode and the lower electrode, and the upper electrode comes into direct contact with the floating metal, the upper electrode starts to accumulate charges like the floating metal. The
前記のように直流電圧を印可し続けることによって、 上部電極とフ ローティングメタルは同電位となるため、 フローティングメタルから 上部電極へ生じていた静電気力は消滅する。 その結果、 上部電極を引 き付けていた静電気力はパネの復元力よりも小さくなって、 上部電極 がフローティングメタルから離れてしまい、 容量値が小さくなつた。 この時、 フローティングメタルは電気的には絶縁されているため、 蓄 積された電荷は、 自然放電でしか放出されない。 そして、 自然放電に は数十秒間を要する。 By continuing to apply the DC voltage as described above, the upper electrode and the floating metal have the same potential, and the electrostatic force generated from the floating metal to the upper electrode disappears. As a result, the electrostatic force that attracted the upper electrode was smaller than the restoring force of the panel, and the upper electrode moved away from the floating metal, resulting in a smaller capacitance value. At this time, since the floating metal is electrically insulated, the accumulated charge is released only by spontaneous discharge. And natural discharge takes tens of seconds.
フローティングメタルに電荷が蓄積された状態で、 印加電圧を急激 に 0 Vにした場合、 もともとアースに接地されて電位が 0 Vに戻った 上部電極と、 電荷が蓄積されたままのフローティングメタルとの間に 04011219 If the applied voltage is suddenly reduced to 0 V while the charge is stored in the floating metal, the upper electrode, which was originally grounded to ground and returned to 0 V, is connected to the floating metal that has been stored with charge. Between 04011219
13 は、 又、 大きな電位差が生じるため、 この間でバネの復元力よりも大 きい静電気力が発生して、 上部電極がフローティングメタルに引き付 けられて接触し、 一時的に容量値は回復する。 In addition, since a large potential difference is generated, an electrostatic force larger than the restoring force of the spring is generated during this time, and the upper electrode is attracted to the floating metal and comes into contact with it, and the capacitance value is temporarily recovered. .
しかし、 フローティングメタルに蓄積された電荷は上部電極を介し て速やかに放出されるため、 数秒の後にフローティングメタルの電位 は 0 Vに戻り、静電気力が消滅してパネの復元力によって両者は離れ、 容量値が初期値に戻った、 と考えられる。 However, since the electric charge accumulated in the floating metal is quickly released through the upper electrode, the potential of the floating metal returns to 0 V after a few seconds, the electrostatic force disappears, and the restoring force of the panel separates them. It is probable that the capacitance value has returned to the initial value.
以上の考察を確認するため、 先ず、 前記第 4 A図、 第 4 B図に例示 した例と同様の寸法 ·構造を有する容量型 M E M S素子を用いて、 対 向領域内におけるフローティングメタル領域と容量膜領域との面積比 を変えて作製し、 それぞれの動作電圧と前記現象の発生有無について 調べた。 In order to confirm the above consideration, first, using a capacitive MEMS element having the same dimensions and structure as the example illustrated in FIGS. 4A and 4B, the floating metal region and the capacitance in the opposite region It was fabricated by changing the area ratio with respect to the film region, and each operating voltage and the presence or absence of the above phenomenon were examined.
この実験で用いた容量型 M E M S素子の上部電極と下部電極との対 向領域の寸法は、 前記と同様 2 0 0マイクロメータ X 2 0 0マイクロ メータであり、 フローティングメタルの寸法をそれぞれ 1 0 0マイク 口メ一夕口(全体の 2 5 %)、 1 2 0マイクロメータ口(全体の 3 6 %)、 1 5 0マイクロメータ口 (全体の 5 6 %)、 1 7 0マイクロメータ α (全 体の 7 2 %) とした。 形成した位置は、 前記対向領域の中心とフロー ティングメタルの中心とをあわせるように形成した。 The size of the facing region between the upper electrode and the lower electrode of the capacitive MEMS element used in this experiment is 2 0 0 micrometer x 2 0 0 micrometer as described above, and the dimensions of the floating metal are 1 0 0 respectively. Microphone mouth (25% of the total), 120 micrometer port (36% of the total), 1550 micrometer port (56% of the total), 1700 micrometer α (total 7 2% of the body). The formed position was formed so that the center of the facing region and the center of the floating metal were aligned.
前記それぞれの素子を 5つずつ評価し、 その結果を表 1 に纏めた。 Each of the devices was evaluated five by one, and the results are summarized in Table 1.
表 1 table 1
サイズ 面積比率 動作電圧 容量値の変化 Size Area ratio Operating voltage Change in capacitance
(Ac mD) % ) Γ ) 発生個数 ( 5ケ)(Ac mD)%) Γ) Number of occurrences (5)
1 0 0 2 5 7. 2 0 1 0 0 2 5 7. 2 0
1 2 0 3 6 8. 1 0 1 2 0 3 6 8. 1 0
1 4 0 5 0 8. 7 0 1 4 0 5 0 8. 7 0
1 5 0 5 6 9. 0 1 1 5 0 5 6 9. 0 1
1 7 0 7 2 1 6. 4 5 表 1 より、 動作電圧に関しては、 フローティングメタルが小さくな れぱなるほど、 動作電圧も小さくなつている。 フローティングメタル が 1 5 0マイクロメータ□ (全体の 5 6 %) の素子では、 フローテイン グメタルが無い場合の動作電圧 (= 6 V、 前記従来技術に記載) の約 1 . 5倍の 9 Vで動作することがわかった。 又、 1 4 1 マイクロメ一 タ^ (全体の 5 0 %) の素子では、 8. 7 V動作する。 1 7 0 7 2 1 6. 4 5 From Table 1, regarding the operating voltage, the smaller the floating metal, the lower the operating voltage. With an element with a floating metal of 1550 micrometers □ (5 6% of the total), the operating voltage without floating metal (= 6 V, approximately 1.5 times that of the prior art) is 9 V. I found it to work. The 14 1 micrometer (50% of the total) element operates at 8.7 V.
次に、 直流電圧を印加したまま放置することによって発生する不可 解な容量値の挙動 (変化) については、 全体の対向面積に占めるフロ 一ティングメタルの面積比率依存性が明確に現れている。 フローティ ングメタルの寸法が対向面積全体の約 5 6 %となる 1 5 0マイクロメ 一夕 ^を境に比率が大きい場合には、すべて不可解な容量変化が発生し ており、 逆にそれよリも小さい場合にはすべて発生しない結果となつ た。 Next, regarding the inexplicable behavior (change) of the capacitance value that occurs when the DC voltage is left as it is applied, the area ratio dependence of the floating metal in the total facing area clearly appears. The size of the floating metal is about 56% of the total facing area. 1 5 0 Micrometer Overnight When the ratio is large at the border ^, all mysterious capacity changes have occurred, and conversely it is smaller. In all cases, the results did not occur.
1 5 0マイクロメータ□のフローティングメタルがある素子では、 1 個 (/ 5個) だけ容量が変化する挙動を見せ、 一方、 〗 4 〗 マイクロ メータ□のフローティングメタルがある素子では、不可解な容量変化が 発生しない。 従って、 実際に適用できるフローティングメタルの面積 19 The element with 1 50 micrometer □ floating metal shows the behavior of changing the capacitance by 1 (/ 5), while the element with〗 4〗 micrometer □ floating metal has a mysterious capacitance change. Does not occur. Therefore, the area of floating metal that can actually be applied 19
15 比率は、 対向領域全体の 5 0 %以下が望ましいということが言える。 応用として、 第 5図に示すような構造の素子を作成し、 評価した。 第 5図の構造は、 前記第 4 A図の構成とほぼ同様であるが、 フローテ ィングメタル 6が、 対向領域内に形成している前記フローティングメ タル 6から対向領域外の誘電体膜 5上にも連続した一連のパターンと して形成されている。 この時、 垂直方向から見た前記対向領域内にお けるフローティングメタルの面積比率は、 対向領域全体の約 4 5 %で め 。 15 It can be said that the ratio is preferably 50% or less of the entire opposite area. As an application, an element with the structure shown in Fig. 5 was created and evaluated. The structure of FIG. 5 is substantially the same as the structure of FIG. 4A, except that the floating metal 6 is formed on the dielectric film 5 outside the opposing region from the floating metal 6 formed in the opposing region. It is also formed as a continuous series of patterns. At this time, the area ratio of the floating metal in the facing region viewed from the vertical direction is about 45% of the entire facing region.
結果は、 動作電圧が 9 . 8 Vであり、 電圧印加放置による不可解な 容量値の挙動も示さなかった。 更に、 容量値が約 4 5 p Fという初期 値 ( 0 . 5 p F ) の約 9 0倍もの値を示した。 As a result, the operating voltage was 9.8 V, and it did not show a mysterious capacitance value behavior due to the voltage application. Furthermore, the capacitance value was about 45 pF, which was about 90 times the initial value (0.5 pF).
これは、 上部電極 1 2がフローティングメタル 6に電気的に接触す ることによって、 下部電極 1 上の誘電体膜 5上に形成された広大な面 積を有するフローティングメタル 6と、 対向する下部電極 1 との間の 対向面積が容量値に反映されたものであると推定できる。 本構造のよ うなフローティングメタルの配置は、 スィツチのオン/オフ容量比を 拡大するための一つの優れた手法であると言える。 This is because when the upper electrode 12 is in electrical contact with the floating metal 6, the floating metal 6 having a large area formed on the dielectric film 5 on the lower electrode 1 is opposed to the opposing lower electrode. It can be estimated that the facing area between and 1 is reflected in the capacitance value. Floating metal placement like this structure is an excellent way to increase the on / off capacitance ratio of the switch.
以上の応用実験の結果からも、 対向領域におけるフローティングメ タルの面積比率を、 前記規定の範囲内 ( 5 0 %以下) にすることによ つて、 前記従来技術で発生した不良を回避できることが判明した。 更 に、 本構造のようなフローティングメタルのパターン配置は、 上部ノ 下部電極間に働く静電気力に対して悪影響をもたらすことはなく、 ス ィツチのオン Zオフ容量比を拡大するための一つの優れた手法である と言える。 即ち、 対向領域におけるフローティングメタルの面積比率 を 5 0 %以下にすれば、 フローティングメタルに電荷が蓄積された場 合でも、 静電気力 >パネの復元力の関係を維持できる。 04 011219 From the results of the above applied experiments, it has been found that the defects caused in the conventional technology can be avoided by setting the area ratio of the floating metal in the facing region within the specified range (50% or less). did. In addition, the floating metal pattern layout like this structure does not adversely affect the electrostatic force acting between the upper and lower electrodes, and is one excellent way to increase the switch on-off capacitance ratio. It can be said that this is a technique. In other words, if the area ratio of the floating metal in the opposite region is 50% or less, the relationship of electrostatic force> panel restoring force can be maintained even when charge is accumulated in the floating metal. 04 011219
16 尚、 以上述べた実験では、 得られた結果を比較しやすくするため、 すべて同一構造、 同一寸法のシャン卜型の容量型 M E M S素子を用い ているが、 パネやメンブレンの寸法や形状、 素子自体の.構造を変えた 容量型 M E M S素子を用いて、 フローティングメタルの面積比率を変 えて実験した場合でもほぼ同様の傾向を示す結果が得られた。 16 In the experiments described above, in order to make it easy to compare the obtained results, all the same structure and the same size of the shunt-type capacitive MEMS element are used. Even when an experiment was conducted using a capacitive MEMS element with a different structure, and changing the area ratio of the floating metal, the same results were obtained.
しかしながら、 前記推論が正しければ、 フローティングメタル中の 電荷は常に蓄積されたままであるため、連続して動作を繰り返す場合、 素子の動作が不安定になる可能性は否めない。 However, if the reasoning is correct, the charge in the floating metal always remains accumulated, so there is a possibility that the operation of the element becomes unstable when the operation is repeated continuously.
そこで、 前記第 5図に示した素子のフローティングメタル 6とァー ス 2との間に、 電気抵抗値が 1 k Ω以上の抵抗パターン 7を配置 (実測 では 3 . 7 k Ω ) した第 6図に示すような構造の容量型 M E M S素子 を作製した。 そして、 これまでの例と同じように、 上部 Z下部電極間 に直流電圧を印加して、 動作電圧及び動作電圧印加状態での放置によ る容量値の変化の有無を評価した。 尚、 前記抵抗体の抵抗値の決定方 法であるが、 前記の容量型 M E M S素子は、 主に高周波信号用のスィ ツチとして用いるものであリ、 高周波信号の性質として比較的高抵抗 を有する物質や、 インピーダンスにして高抵抗となるィンダクタを通 過することはできないため、 本実験では一例として前記〗 1 Ω以上の 金属抵抗体を用いた。 Therefore, a resistor pattern 7 having an electrical resistance value of 1 kΩ or more (3.7 kΩ in actual measurement) is arranged between the floating metal 6 and the case 2 of the element shown in FIG. A capacitive MEMS device with the structure shown in the figure was fabricated. In the same way as in the previous examples, a DC voltage was applied between the upper and lower Z electrodes, and the presence or absence of changes in the capacitance value due to leaving the operating voltage and the operating voltage applied was evaluated. In addition, although it is a method for determining the resistance value of the resistor, the capacitive MEMS element is mainly used as a switch for a high-frequency signal, and has a relatively high resistance as a property of the high-frequency signal. Since it is not possible to pass through a substance or an inductor that has high impedance as an impedance, in this experiment, the metal resistor of 1 Ω or more was used as an example.
前記抵抗体の存在は、 フローティングメタルに蓄積されたと考えら れる電荷を速やかに放出するための方法の一つであり、 一例として本 構造では、 フローティングメタルの接続先をアースとしたものである。 又、 これによつて、 フローティングメタルは直流的にはショートにな るが、 高周波的にはフロート状態のままである。 その結果、 動作電圧 自体は 1 5 Vにまで高電圧化してしまったものの、 電圧印加したまま の放置状態で、 前記不可解な容量値の挙動は見られなかった。 更に、 9 The existence of the resistor is one of the methods for quickly releasing the electric charge that is considered to be accumulated in the floating metal. As an example, in this structure, the connection destination of the floating metal is grounded. As a result, the floating metal is short-circuited in terms of direct current, but remains floating in terms of high-frequency. As a result, although the operating voltage itself was increased to 15 V, the inexplicable behavior of the capacitance value was not observed when the voltage was left applied. Furthermore, 9
17 印加電圧を 0 Vに戻しても、 容量値は初期の値に戻ったままで変化し ないことが確認できた。 17 It was confirmed that even when the applied voltage was returned to 0 V, the capacitance value remained at the initial value and did not change.
前記結果に関して、 まず動作電圧の上昇に関しては、 前記構造の場 合、 アースに接続されている上部電極と、 抵抗体を介して接続したフ ローテイングメタルは、 直流的には常に同電位であるので、 フローテ ィングメタル/上部電極間には静電気力が発生せず、 フローティング メタル以外の誘電体膜露出領域下の下部電極と、 これと対向する領域 の上部電極との間の狭い対向領域のみで引き付けあっているためであ ると推定できる。 Regarding the above results, regarding the increase in operating voltage, in the case of the above structure, the upper electrode connected to the ground and the floating metal connected via the resistor are always at the same potential in terms of DC. Therefore, no electrostatic force is generated between the floating metal and the upper electrode, and only in the narrow facing area between the lower electrode under the dielectric film exposure area other than the floating metal and the upper electrode in the area facing it. It can be estimated that this is because they are attracting each other.
そして、 電圧印加による放置状態での容量値の変化が起こらないの は、 電荷の蓄積が起こらない前記狭い領域のみで引き付けあっている ためであり、 0 Vに戻して上部電極がフローティングメタルに引き付 けられないのも、 フローティングメタルとアースとを抵抗体を介して 接続することによって、 フローティングメタルに溜まった電荷が速や かに放出されたためと推定できる。 The reason why the capacitance value does not change in the neglected state due to voltage application is that it is attracted only in the narrow region where charge accumulation does not occur, and the upper electrode is pulled to the floating metal by returning to 0 V. The reason why it cannot be attached is presumed that the charge accumulated in the floating metal was released quickly by connecting the floating metal and ground via a resistor.
以上の詳細実験及び諸考察により、 フローティングメタルとアース (又は電圧端子)との間に抵抗素子を接続することにより、 フローティ ングメタルの電荷蓄積を防止できることが判明した。 From the above detailed experiments and considerations, it was found that the charge accumulation of the floating metal can be prevented by connecting a resistance element between the floating metal and the ground (or voltage terminal).
しかし、 前記のように抵抗素子の抵抗値に依存して、 スィッチの才 ン /オフ ( O n / O f f ) 切換時間と損失は劣化する。 抵抗素子を用 いてフローティングメタルからアースに電荷を逃がす場合、 フローテ ィングメタルに残る電荷量変化は、 時間の指数関数に逆比例する。 However, depending on the resistance value of the resistance element as described above, the switching time / loss (On / Offf) switching time and loss of the switch deteriorate. When a resistive element is used to release charge from floating metal to ground, the amount of charge remaining on the floating metal is inversely proportional to the exponential function of time.
電荷量が 1 / e ( eは 2 . 7 1 8 2 8 )となる時間定数 d tは、 フロ —ティングメタルとアースとの容量 C f と、 用いる抵抗素子の抵抗値 R f の積 C f · R f で表される。 時間定数 d tは、 必要なオンオフ切 換時間 d t 0 f f より小さくする必要があるから、 d t 0 f f >> d t である必要がある。 GHz帯で動作する低損失スィツチの場合、 C f は 5 p F〜2 0 p F、 d t o f f < 0. 1 m s e cとする必要があるため、 結局、 R f < 5 R〜 2 0 M Ωである必要がある。 The time constant dt at which the amount of charge is 1 / e (e is 2.7 1 8 2 8) is the product of the capacitance C f of the floating metal and the ground C f, and the resistance value R f of the resistive element used C f · Represented by R f. Since the time constant dt must be smaller than the required on / off switching time dt 0 ff, dt 0 ff >> dt Need to be. In the case of a low-loss switch operating in the GHz band, C f needs to be 5 p F to 20 p F and dtoff <0.1 msec, so that R f <5 R to 20 MΩ There is a need.
スィツチの損失を設計する場合、スィツチに接続される電子部品(し, フィルタ等)の Q値とのバランスを考慮する必要がある。 し、 フィルタ の Q値は 2 0〜2 0 0 0程度であリ、 特に高 Qフィルタの場合、 スィ ツチにも高い性能が要求される。 When designing the switch loss, it is necessary to consider the balance with the Q value of the electronic components (and filters, etc.) connected to the switch. However, the Q value of the filter is about 20 to 200, and especially in the case of a high Q filter, the switch is required to have high performance.
代表的な誘電体、 S AWフィルタは、 Q値が 8 0 0以上、 直列抵抗 1 Ω以下であるため、 結局、 R f >8 0 0 Q (= 1 Ω Χ 8 0 0 )である 必要がある。 A typical dielectric, S AW filter, has a Q value of 800 or more and a series resistance of 1 Ω or less. Therefore, R f> 8 0 0 Q (= 1 Ω Χ 8 0 0) is there.
前記はフローティングメタルとの接続先がアースの場合で説明した が、 電圧端子の場合でも全く同様の効果がある。 又、 抵抗素子の変わ リにィンダクタを用いる場合、 R f を動作させる周波数帯でのィンピ —ダンスに置き換えることで、 同様の効果がある。 In the above description, the floating metal is connected to the ground. However, the same effect can be obtained when the voltage terminal is used. In addition, when an inductor is used to change the resistance element, the same effect can be obtained by replacing it with impedance in the frequency band in which R f is operated.
次に、 前記抵抗体接続構造によるスィッチの低電圧動作化を目指し て、 対向領域におけるフローティングメタルの面積比率を調節し、 更 に前記対向領域外にもフローティングメタルを配した構造の容量型 M E M S素子を作製して、 動作電圧の評価を行った。 この例を、 第 2 A 図、 第 2 B図に示す。 第 2 A図は平面図、 第 2 B図は線 B B, での断 面図である。 本例は、 第 6図の例とフローティングメタル 6の形状、 面積比率が異なる。従って、その他の詳細説明は省略する。本例では、 フローティングメタル 6の面積比率は、 対向領域全体の〗 5 %となる よう設計した。 簡単に言えば、 対向領域におけるフローティングメタ ル 6の面積を著しく小さくして、 なお且つ対向領域以外の誘電体膜 5 上にもフローティングメタル 6を延長して広く形成した。 更に、 フロ 一ティングメタル 6を 2 k Ω程度の抵抗素子を介してアース 2に短絡 させた構造である。 Next, aiming at low voltage operation of the switch by the resistor connection structure, the area ratio of the floating metal in the opposing region is adjusted, and the capacitive MEMS element having a structure in which the floating metal is arranged outside the opposing region. And the operating voltage was evaluated. Examples of this are shown in FIGS. 2A and 2B. Fig. 2A is a plan view and Fig. 2B is a cross-sectional view along line BB. This example differs from the example in Fig. 6 in the shape and area ratio of the floating metal 6. Therefore, other detailed explanation is omitted. In this example, the area ratio of the floating metal 6 was designed to be 5% of the entire facing area. In short, the area of the floating metal 6 in the opposing region is remarkably reduced, and the floating metal 6 is extended and formed on the dielectric film 5 other than the opposing region. Furthermore, floating metal 6 is short-circuited to ground 2 through a resistance element of about 2 kΩ. It is the structure made to do.
その結果、 動作電圧が 6 . 2 Vとなる結果が得られた。 この電圧値 は、 フローティングメタルを設けていない時とほぼ同等の値であり、 この時に得られる容量値が 3 2 p Fという初期値の約 6 0倍の容量値 を得た。 As a result, the operating voltage was 6.2 V. This voltage value is almost the same value as when no floating metal was provided, and the capacitance value obtained at this time was 3 2 p F, which was approximately 60 times the initial value.
以上のことから、 従来技術で発生した容量型 M E M S素子の課題を 解決するためには、 下記事項の少なくとも一者を用いて達成すること が出来る。 勿論、 その両者を組み合わせて用いることも出来る。 From the above, in order to solve the problem of the capacitive MEM S element generated in the prior art, it can be achieved by using at least one of the following items. Of course, both can be used in combination.
( 1 ) 前記従来のフローティングメタルを有する構造において、 対向 領域内におけるフローティングメタルの面積比率を、 対向領域全体の (1) In the structure having the conventional floating metal, the area ratio of the floating metal in the opposing region
5 0 %以下にする。 5 Set to 0% or less.
( 2 ) フローティングメタル自体を、 高周波信号に対して抵抗となる 物質を介して、 所望の電位を有する物質と直流的に接続させる。 (2) The floating metal itself is connected in direct current to a substance having a desired potential via a substance that becomes a resistance to a high-frequency signal.
好ましくは、 対向領域内におけるフローティングメタルの面積比率 を著しく小さくする、 例えば全体の 1 5 %前後にすれば、 フローティ ングメタルが無い構造とほぼ同等の動作電圧で動作する容量型 M E M Preferably, if the area ratio of the floating metal in the opposing region is significantly reduced, for example, around 15% of the total, the capacitive M E M that operates at an operating voltage almost equivalent to the structure without the floating metal
S素子を作製することが出来る。 S element can be manufactured.
更には、 フローティングメタルの形成領域を、 対向領域以外の下部 電極上の誘電体膜上にも拡大しても、 フローティングメタルは、 前記 の対向領域内における形成パターンの面積比率に関する制約さえ守れ ば、 対向領域以外の領域にも広く形成しても良い。 それは、 フローテ ィングメタルの形成領域が、 対向領域内で生じる静電気力には何ら影 響を及ぼさない為である。 これにより動作時の容量値ならびにオン オフ容量比を大きくできる。 Furthermore, even if the formation region of the floating metal is expanded on the dielectric film on the lower electrode other than the opposing region, the floating metal can be used as long as the restrictions on the area ratio of the formation pattern in the opposing region are observed. You may form widely also in area | regions other than an opposing area | region. This is because the floating metal formation region has no effect on the electrostatic force generated in the opposing region. As a result, the capacitance value during operation and the on / off capacitance ratio can be increased.
又、 前記対向領域内におけるフローティングメタルの形状は、 特に 限定するものではなく、 如何なる形状で設けても良い。 19 Further, the shape of the floating metal in the facing region is not particularly limited, and may be provided in any shape. 19
20 前記高周波信号に対して抵抗となる物質とは、 例えば 1 以上で 1 M Ω以下の電気抵抗値を有する高抵抗体、 または 1 Ι Ω以上で 1 M Ω以下のインピーダンスを示すインダクタのことを指し、 所望の電位 を有する物質とは、 素子の構造にもよるが例えば接地線、 上部電極、 下部電極、 制御電極等を指す。 20 The substance that becomes a resistance to the high-frequency signal is, for example, a high-resistance body having an electrical resistance value of 1 to 1 MΩ or an inductor that exhibits an impedance of 1 to 1 MΩ. The substance having a desired potential refers to, for example, a ground wire, an upper electrode, a lower electrode, a control electrode, etc., depending on the structure of the element.
更に、 前記アンカ、 パネ、 及び上部電極は一体構造を成してメンブ レンとなり、 且つ連続した同一の低抵抗な金属体によって形成される ことが望ましい。 Further, it is desirable that the anchor, the panel, and the upper electrode form an integral structure to form a membrane and be formed of a continuous and same low-resistance metal body.
この時、 前記金属体は金、 アルミニウム、 銅の何れかの低抵抗な単 一金属膜、 若しくは前記金属種と他の金属との積層膜であることが望 ましい。 At this time, the metal body is preferably a single metal film having a low resistance of gold, aluminum, or copper, or a laminated film of the metal species and another metal.
また前記誘電体膜上に形成された前記低抵抗金属膜についても、 低 抵抗な金属材料からなることが望ましく、 特に上部電極との接触抵抗 を著しく低減できる材料が好ましい。 詳しくは、 金、 アルミニウム、 銅等の何れか単一金属膜、 若しくは前記金属種と他の金属との積層膜 であることが望ましい。 The low-resistance metal film formed on the dielectric film is also preferably made of a low-resistance metal material, and in particular, a material that can significantly reduce the contact resistance with the upper electrode is preferable. Specifically, it is desirable to be a single metal film such as gold, aluminum, or copper, or a laminated film of the above metal species and another metal.
更に、 前記低抵抗金属膜からなるフローティングメタル表面は、 平 坦面である場合以外に、 定常時 (電圧を印加しない時) において上部 電極と接触しなければ、 フローティングメタルと同一材料、 もしくは 他の低抵抗金属材料からなる上方向への突起を一箇所、 もしくは複数 箇所設けても構わない。 Further, the surface of the floating metal made of the low-resistance metal film is the same material as the floating metal, or other materials unless the surface of the floating metal is in contact with the upper electrode at a constant time (when no voltage is applied), except for a flat surface. One or a plurality of upward projections made of a low-resistance metal material may be provided.
これとは逆に、 前記条件を満たすならば上部電極下面に下方向に向 かう突起を一箇所、 もしくは複数箇所設けても同様の効果が得られる ことはいうまでもない。 On the contrary, if the above condition is satisfied, it goes without saying that the same effect can be obtained even if one or a plurality of protrusions directed downward are provided on the lower surface of the upper electrode.
以上、 詳述したように、 本発明によれば、 高周波信号に対して極め て良好かつ安定したスイッチング特性とァイソレーション特性が得ら れる。 更には、 本発明によれば、 高信頼で低電圧で動作する容量型 M E M S素子、 並びに本発明の容量型 M E M S素子を搭載した高性能な 高周波装置を提供できる。 As described above in detail, according to the present invention, extremely good and stable switching characteristics and isolation characteristics can be obtained for high-frequency signals. It is. Furthermore, according to the present invention, it is possible to provide a capacitive MEMS element that operates at a low voltage with high reliability, and a high-performance high-frequency device equipped with the capacitive MEMS element of the present invention.
本発明の容量型 M E M S素子では、 例えば高周波スィツチとして機 能させる場合のスィッチオフ時 (電圧印加時) の容量値も、 対向領域 以外の下部電極上に位置する誘電体膜上にフローティングメタルを延 長して形成することによって大きくできる上に、 フローティングメタ ル全体の面積から、 ほぼ計算値通りの容量値を容易に実現できること から、 スィッチ素子の設計も極めて容易になる。 In the capacitive MEMS element of the present invention, for example, the capacitance value at the time of switching off (when applying voltage) when functioning as a high-frequency switch is also used to extend the floating metal on the dielectric film located on the lower electrode other than the opposing region. In addition to being able to be made large by forming it long, the capacitance value almost as calculated can be easily realized from the area of the entire floating metal, so the design of the switch element becomes extremely easy.
更に、 前記の通り、 フローティングメタルの形成領域を対向領域以 外のェリアまで拡大できること、 上部電極は一箇所でもフローティン グメタルに接触すればよいこと、 などから、 上部電極はこれまでより も大幅に小さくできる。 これによつて、 金属体によって構成される上 部電極を含むメンプレンの、 残留内部応力による湾曲 ·変形を著しく 抑制できる可能性がある。 Furthermore, as described above, the floating metal formation area can be expanded to areas other than the opposing area, and the upper electrode only needs to be in contact with the floating metal at one location. Can be small. As a result, the bending / deformation due to the residual internal stress of the membrane including the upper electrode made of a metal body may be remarkably suppressed.
上部電極と接触する低抵抗金属膜からなるフローティングメタルも、 抵抗値が低い A u、 A I 、 C u等を主体とした金属膜を用いることで、 接触抵抗や直列抵抗を低減できることから、 極めて低損失なまま高周 波信号を伝達することができる。 Floating metal made of a low-resistance metal film in contact with the upper electrode is also extremely low because the contact resistance and series resistance can be reduced by using a metal film mainly composed of Au, AI, and Cu with low resistance. High frequency signals can be transmitted without loss.
本発明の容量型 M E M S素子の構造 ·性質からして、 高周波スイツ チとしての用途以外に、 本素子を一個、 または複数個を並列 · 直列に 接続 ' 配置することによって、 S P n Tスィッチや、 広い範囲の容量 値を可変できる可変容量装置にも応用できる。 Due to the structure and properties of the capacitive MEMS element of the present invention, in addition to its use as a high-frequency switch, one or more of these elements can be connected in parallel and in series, so that an SP n T switch, It can also be applied to variable capacitance devices that can vary a wide range of capacitance values.
更に、 本発明の容量型 M E M S素子は、 作製プロセス上の観点から 見ると極めて僅かなプロセス増加で済むため、 製造コストの増加も小 さく抑えることができる。 本発明の容量型 M E M S素子は一般的な半導体作製プロセスで容易 に作製できることから、 F E Tやバイポーラ卜ランジス夕等の半導体 能動デバイスや、 他の受動デバイスと同一基板上に形成してワンチッ プ化することが可能となるため、 これまでよりも小型化されたモジュ —ル装置を容易に作製できる。 Furthermore, since the capacitive MEMS element of the present invention requires a very slight increase in process from the viewpoint of the manufacturing process, an increase in manufacturing cost can be suppressed to a small extent. Since the capacitive MEMS element of the present invention can be easily manufactured by a general semiconductor manufacturing process, it is formed on the same substrate as a semiconductor active device such as an FET or a bipolar transistor and other passive devices. Therefore, it is possible to easily manufacture a module device that is smaller than before.
<実施の諸形態 > <Embodiments>
以下、 本発明に係る容量型 M E M S素子を図面に示した幾つかの好 ましい実施形態を参照して、 更に詳細に説明する。 Hereinafter, the capacitive M E M S element according to the present invention will be described in more detail with reference to some preferred embodiments shown in the drawings.
第 1 A図、 第 1 B図に本発明の第一の実施形態を模式図で示す。 第 1 A図は素子の平面図、 第 1 B図はその線 B B ' での断面図である。 絶縁基板 3上に素子の下部電極としての機能も有する信号線路 1 が 形成され、 その周辺にはアース 2が形成されている。 絶縁基板 3は、 例えばガラス基板、 化合物半導体基板、 高抵抗シリコン基板、 圧電体 基板などの絶縁材料で形成されている。 絶縁基板 3はまた、 酸化ゲイ 素に代表される絶縁膜で表面を覆った半絶縁体基板、 又は導電体基板 でも良い。 1A and 1B schematically show a first embodiment of the present invention. FIG. 1A is a plan view of the element, and FIG. 1B is a cross-sectional view along the line B B '. A signal line 1 that also functions as a lower electrode of the element is formed on an insulating substrate 3, and a ground 2 is formed around it. The insulating substrate 3 is formed of an insulating material such as a glass substrate, a compound semiconductor substrate, a high-resistance silicon substrate, or a piezoelectric substrate. The insulating substrate 3 may be a semi-insulating substrate whose surface is covered with an insulating film typified by silicon oxide, or a conductive substrate.
信号線路 1 は、 所定の距離に設置されたアース 2と合せて、 第 1 B 図の表裏方向に伸びるコプレーナ型高周波信号線路として機能してい る。 The signal line 1 functions as a coplanar type high-frequency signal line extending in the front and back direction of Fig. 1B, together with the ground 2 installed at a predetermined distance.
アース 2から信号線路 1 を跨ぐように形成されたメンプレン 8は、 アース 2に接続された 4箇所のアンカ 1 0と、 アンカ 1 0に接続され たミアンダ (曲折構造) を有する 4本のバネ 1 1 、 及び上部電極 1 2 がー体構造を成している。 The membrane 8 formed so as to straddle the signal line 1 from the ground 2 is composed of four springs 1 having four anchors 10 connected to the ground 2 and meanders (bending structure) connected to the anchor 10. 1 and the upper electrode 1 2 form a body structure.
信号線路〗 上の一部及び絶縁基板 3上の一部は、膜厚が 0 . 2マイク ロメ一夕のアルミナ膜からなる誘電体膜 5で覆われておリ、 信号線路 1 上に位置する誘電体膜 5の表面には、 T i Z A u 2層構造からなる 低抵抗金属膜からなるフローティングメタル 6が形成されている。 前記信号線路 1 と上部電極 8との対向領域内における前記フローテ イングメタル 6の面積比率は、 前記対向領域全体の 1 5 %とし、 前記 対向領域外の前記信号線路 1 上に位置する前記誘電体膜 5上にも、 フ ローテイングメタル 6を延長して広く形成している。 フローティング メタル 6は、 電気抵抗値が 1 5 k Ωとなる抵抗素子 7を介してアースA part on the signal line 及 び and a part on the insulating substrate 3 are covered with a dielectric film 5 made of an alumina film having a film thickness of 0.2 micrometer and located on the signal line 1. The surface of the dielectric film 5 has a T i ZA u two-layer structure. A floating metal 6 made of a low resistance metal film is formed. The area ratio of the floating metal 6 in the opposing region between the signal line 1 and the upper electrode 8 is 15% of the entire opposing region, and the dielectric located on the signal line 1 outside the opposing region On the film 5, the floating metal 6 is extended and formed widely. Floating metal 6 is grounded through resistance element 7 with an electrical resistance of 15 kΩ.
2に接続されている。 Connected to 2.
アース 2は高周波的に接地されていることに加えて、 直流的にも接 地 (直流電位 0 V ) されている。 従って、 上部電極 1 2は、 バネ 1 1 とアンカ 1 0を介して接地されている。 しかし、 フローティングメタ ル 6は、 抵抗素子 7を介してアース 2に接続されているため、 直流的 にのみ接地されている。 In addition to being grounded at high frequency, Earth 2 is also grounded (DC potential 0 V) in DC. Therefore, the upper electrode 12 is grounded via the spring 11 and the anchor 10. However, since the floating metal 6 is connected to the ground 2 through the resistance element 7, it is grounded only in a direct current manner.
上部電極 1 2と誘電体膜 5との間の空間の距離は約 1 . 2マイクロ メータである。 The distance of the space between the upper electrode 12 and the dielectric film 5 is about 1.2 micrometers.
メンプレン 8には、 膜厚が 2 . 5マイクロメータの A u (金) を用い ており、 信号線路 1 と接地線 2には、 下層 T i (膜厚 = 0 . 0 5マイ クロメータ) との上層 A u (金、 膜厚 0 . 5マイクロメータ) の積層 膜を用いている。 The membrane 8 is made of Au (gold) with a film thickness of 2.5 micrometers, and the signal line 1 and the ground line 2 are connected to the lower layer T i (film thickness = 0.05 micrometer). The upper layer A u (gold, film thickness 0.5 micrometer) is used.
中空に浮いたメンブレン 8を形成するための犠牲層にはポリイミ ド 膜を用いている。 犠牲層除去を容易にするため、 図示していないが上 部電極 1 2には 1 0マイクロメータ 0の貫通穴が、 2 0マイクロメータ 間隔で複数箇所設けられている。 A polyimide film is used as a sacrificial layer for forming the membrane 8 that floats in the air. In order to facilitate the removal of the sacrificial layer, although not shown, the upper electrode 12 is provided with a plurality of through holes of 10 micrometers 0 at intervals of 20 micrometers.
前記構造の M E M S素子の動作電圧 (上部電極が低抵抗金属膜に接 触する電圧)は 6 . 3 Vで、その時の容量値は約 4 8 p Fが得られた。 これは 0 Vの時の容量値が約 0 . 5 p Fと比較して、 約 1 0 0倍近い 値である。 この値は、 フローティングメタル 6と信号線路〗 との対向 面積から計算して求めた値と、 ほぼ同じ容量値が得られた。 第 7 A図、 第 7 B図に本発明の第 2の実施形態を模式図で示す。 本 例は、 金属体からなる片持ち梁を用いた構造の容量型 M E M S素子に 本発明を適用した例である。 第 7 A図は素子の平面図、 第 7 B図は、 その線 B B ' での断面図である。 The operating voltage (voltage at which the upper electrode contacts the low-resistance metal film) of the MEMS element having the above structure was 6.3 V, and the capacitance value at that time was about 48 pF. This is a value that is about 100 times closer to 0 V compared to about 0.5 p F. This value is the opposite of floating metal 6 and signal line〗 A capacitance value almost the same as the value calculated from the area was obtained. FIG. 7A and FIG. 7B schematically show the second embodiment of the present invention. In this example, the present invention is applied to a capacitive MEMS element having a structure using a cantilever made of a metal body. FIG. 7A is a plan view of the element, and FIG. 7B is a sectional view taken along the line BB ′.
酸化ケィ素に表面を覆われた S ί基板 Ί 5上に、 素子の下部電極と しての機能も有する信号線路 1 3が形成され、 その周辺にはアース Ί 4が形成されている。 A signal line 13 having a function as a lower electrode of the element is formed on a glass substrate 5 whose surface is covered with silicon oxide, and a ground wire 4 is formed around the signal line 13.
アース〗 4から信号線路 1 3上の一部を覆うように形成された片持 ち梁 1 6は、 アース 1 4に接続されたアンカ 1 7と、 アンカ 1 7に接 続されたパネ 1 8、 及び上部電極 1 9がー体構造を成している。 尚、 上部電極 1 9の面積は 2 0マイクロメータ Χ 5 0マイクロメータであ る。 The cantilever beam 1 6 formed so as to cover a part of the signal line 1 3 from the ground pole 4 is composed of an anchor 1 7 connected to the ground 1 4 and a panel 1 8 connected to the anchor 1 7. The upper electrode 19 has a body structure. The area of the upper electrode 19 is 20 micrometers to 50 micrometers.
信号線路 1 3上の一部及び S i基板 1 5上の一部は、膜厚が 0 . 1 5 マイクロメータの窒化ケィ素膜からなる誘電体膜 2 0で覆われておリ、 信号線路上に位置する誘電体膜 2 0の表面には、 A I からなるフロー ティングメタル 2 1 が形成されている。 Part of the signal line 1 3 and part of the Si substrate 15 are covered with a dielectric film 20 made of a silicon nitride film having a thickness of 0.15 micrometers. A floating metal 21 made of AI is formed on the surface of the dielectric film 20 located above.
この時、 信号線路 1 3上と上部電極〗 9との対向領域内におけるフ ローテイングメタル 2 1 の面積比率は、 前記対向領域全体の 1 0 %と し、 前記対向領域外の前記信号線路 1 3上に位置する前記誘電体膜 2 0上にも、 フローティングメタル 2 1 を延長して広く形成している。 フローティングメタル 2 1 は、 電気抵抗値が 5 0 0 k Ωとなる抵抗素 子 2 2を介してアース 1 4に接続されている。 At this time, the area ratio of the floating metal 21 in the opposing region between the signal line 13 and the upper electrode 9 is 10% of the entire opposing region, and the signal line 1 outside the opposing region is Also on the dielectric film 20 located on 3, the floating metal 2 1 is extended and widely formed. The floating metal 2 1 is connected to the ground 14 through a resistance element 2 2 having an electric resistance value of 500 kΩ.
アース 1 4は高周波的に接地されていることに加えて、 直流的にも 接地 (直流電位 0 V ) されていることから、 アース 1 4に接続されて いる上部電極 1 9も接地されている。 しかし、 フローティングメタル P T/JP2004/011219 In addition to being grounded at high frequency, ground 14 is also grounded (DC potential 0 V), so the upper electrode 19 connected to ground 14 is also grounded. . But floating metal PT / JP2004 / 011219
25 twenty five
2 1 は、 抵抗素子 2 2を介してアース 7に接続されているため、 直流 的にのみ接地されている。 上部電極 1 9と誘電体膜 2 0との間の空間 の距離は約 0 . 8マイクロメータである。 Since 2 1 is connected to ground 7 through resistance element 2 2, it is grounded only in a direct current manner. The distance of the space between the upper electrode 19 and the dielectric film 20 is about 0.8 micrometers.
片持ち梁 1 6全体は、 膜厚が 2 . 0マイクロメータの A I (アルミ 二ゥ厶) からなリ、 信号線路 1 3とアース 1 4についても、 A I (ァ ルミ二ゥ厶、 膜厚 0 . 4マイクロメータ) 単膜を用いている。 The cantilever 16 as a whole is made of AI (aluminum) with a thickness of 2.0 micrometers, and the signal line 1 3 and ground 14 are also AI (aluminum, thickness 0). 4 micrometer) A single membrane is used.
アース 1 4に接続され中空に浮いた上部電極 1 9を有する片持ち梁 1 6を形成するための犠牲層には、 ホ卜レジスト膜を用いており、 犠 牲層除去を容易にするため、 図示していないが上部電極 1 9には 2マ イク口メータ口の貫通穴が、 5マイクロメータ間隔で複数箇所設けられ ている。 The sacrificial layer used to form the cantilever 16 having the upper electrode 19 that is connected to the earth 14 and floated in the hollow is made of a photoresist film. In order to facilitate the removal of the sacrificial layer, Although not shown, the upper electrode 19 is provided with a plurality of through-holes of a 2-micrometer meter opening at intervals of 5 micrometers.
前記構造の M E M S素子の動作電圧 (上部電極が低抵抗金属膜に接 触する電圧)は 1 . 5 Vで、その時の容量値は約 2 4 p Fが得られた。 これは 0 Vの時の容量値が約 0 . 2 p Fと比較して約 1 2 0倍の値で ある。 The operating voltage (voltage at which the upper electrode contacts the low-resistance metal film) of the M E M S element having the above structure was 1.5 V, and the capacitance value at that time was about 24 pF. This is a value of about 120 times the capacitance value at 0 V compared with about 0.2 pF.
前記第 2の実施形態における上部電極 1 9の面積は、 前記第一の実 施形態のときと比較して著しく小さいことから、 素子全体の大きさも 前記第 1 の実施形態よリも小さい。 Since the area of the upper electrode 19 in the second embodiment is significantly smaller than that in the first embodiment, the overall size of the device is also smaller than that in the first embodiment.
ところが、 動作電圧は 1 . 5 Vと低電圧化された上、 得られた容量 値も第 1 の実施形態とほぼ同等の値が得られている。 このように、 本 発明の構造を適用することにより、 従来よリも小型で且つ優れたスィ ツチング特性を有する高周波用の容量型 M E M S素子を作製すること ができる。 However, the operating voltage was lowered to 1.5 V, and the obtained capacitance value was almost the same as that of the first embodiment. Thus, by applying the structure of the present invention, it is possible to manufacture a high-capacity capacitive MEMS element having a smaller size and superior switching characteristics.
本発明の第 3の実施形態として、 信号線路とアースとは別に、 単独 で制御端子を設けた容量型 M E M S素子の例を示す。 この例は第 8図 の平面図に示される。 ガラス基板 6 0上に信号線路 6 1 が形成され、 その周辺にはアース 6 2が形成されており、 アース 6 2領域内の一部に、 アース 6 2とは 電気的に接続しない制御端子 6 3が形成されている。 As a third embodiment of the present invention, an example of a capacitive MEMS element in which a control terminal is provided separately from a signal line and ground will be described. An example of this is shown in the plan view of Figure 8. A signal line 6 1 is formed on a glass substrate 60, and a ground 6 2 is formed around the signal line 61. A control terminal 6 that is not electrically connected to the ground 6 2 in part of the ground 6 2 region. 3 is formed.
メンブレン 6 4は、 制御端子 6 3に接続されたアンカ 6 5と、 アン 力 6 5に接続されたミアンダ (曲折構造) を有するパネ 6 6、 及びァ ース 6 2との間で静電気力を発生させるための領域 6 7— 1 と、 フロ —ティングメタル 7 0と接触する領域 6 7 - 2とが個別に存在するか たちで形成された上部電極 6 7がー体構造を成している。 Membrane 64 has an electrostatic force between anchor 65 connected to control terminal 63, panel 6 6 having meander (bent structure) connected to anchor 65, and ground 62. The upper electrode 6 7 formed by the existence of the region 6 7-1 for generating and the region 6 7-2 in contact with the floating metal 70 forms a body structure. .
尚、 アンカ 6 5は 4箇所形成されているが、 制御端子 6 3に接続さ れたアンカは 1箇所のみであり、 その他のアンカはすべてガラス基板 6 0上に接して形成されている。 The anchors 65 are formed at four locations, but only one anchor is connected to the control terminal 63, and all other anchors are formed on the glass substrate 60.
信号線路 6 1 上の一部とガラス基板 6 0上の一部、 及びアース 6 2 上の一部は、 酸化夕ンタルからなる膜厚が 2 5 0ナノメータの誘電体 膜 6 9で覆われた構造となっており、 信号線路 6 1 上に位置する誘電 体膜 6 9上にはフローティングメタル 7 0が形成されている。 フロー ティングメタル 7 0は、 1 G H z程度の高周波信号に対して 1 5 0 k Ω程度のインピーダンス特性を示すインダク夕素子 7 1 を介して信号 線路 6 1 に接続されている。 尚、 前記信号線路 6 1 、 アース 6 2、 制 御端子 6 3、 メンプレン 6 4、 フローティングメタル 7 0は、 すべて 銅によって構成されている。 Part of the signal line 6 1, part of the glass substrate 60, and part of the ground 6 2 were covered with a dielectric film 6 9 made of oxide oxide and having a thickness of 25 50 nanometers. A floating metal 70 is formed on the dielectric film 69 located on the signal line 61. The floating metal 70 is connected to the signal line 61 through an inductor element 71 having an impedance characteristic of about 150 kΩ for a high frequency signal of about 1 GHz. The signal line 6 1, the earth 6 2, the control terminal 6 3, the membrane 6 4, and the floating metal 70 are all made of copper.
前記構造では、 上部電極 6 7と信号線路 6 1 との対向領域内には誘 電体膜 6 9が露出した領域は僅かに存在するだけであり、 フローティ ングメタル 7 0が占める面積比率は約 9 0 %である。 しかし、 メンブ レン 6 4との間の静電気力は主にアース 6 2との間で発生するため、 動作上何ら問題はない。 In the above structure, there are only a few regions where the dielectric film 69 is exposed in the opposing region between the upper electrode 67 and the signal line 61, and the area ratio occupied by the floating metal 70 is about 9%. 0%. However, since the electrostatic force between the membrane 6 4 and the earth 6 2 is mainly generated, there is no problem in operation.
前記構造は、 上部電極 6 7が接触することによるフローティングメ タル 7 0への電荷蓄積を防止するために、 インダクタ素子 7 1 を設け たものである。 The structure described above is based on the floating mem Inductor element 7 1 is provided in order to prevent charge accumulation in Tal 70.
信号線路上の誘電体膜上の殆どの領域にフローティングメタルを形 成できるため、 制御端子への電圧印加によってメンプレンがフローテ イングメタルに接触した時に得られる容量値を、 著しく大きくできる 特徴がある。 Since floating metal can be formed in almost all regions on the dielectric film on the signal line, the capacitance value obtained when the membrane contacts the floating metal by applying voltage to the control terminal has the feature that it can be remarkably increased.
以上、 シャン卜接続型の素子を例に説明したが、 本発明はシリーズ 接続型でも同様の効果がある。 As described above, the Shank connection type element has been described as an example, but the present invention has the same effect even in the series connection type.
第 9 A図、 第 9 B図、 第 9 C図に、 本発明の第 4の実施形態を模式 図で示す。 第 9 A図は素子の平面図、 第 9 B國は、 その線 B B ' での 断面図である。 同図はシーソー構造のメンプレンを備えた容量型 M E M S素子である。 第 9 C図は、 メンブレンの構造を説明する概略斜視 図である。 FIG. 9A, FIG. 9B, and FIG. 9C schematically show the fourth embodiment of the present invention. Fig. 9A is a plan view of the device, and Fig. 9B is a cross-sectional view along line B B '. This figure shows a capacitive M E M S element with a seesaw structure membrane. FIG. 9C is a schematic perspective view illustrating the structure of the membrane.
ガラス基板 2 8上に、 膜厚が 5 0 0 n mの C u (銅) からなる入力 信号線路 2 4が形成され、 その両側には出力信号線路 2 5 (左側)、 及 び 2 6 (右側) が形成されている。 そしてその周辺にはアース 2 7が 形成されている。 An input signal line 24 made of Cu (copper) with a film thickness of 500 nm is formed on a glass substrate 28, and output signal lines 2 5 (left side) and 2 6 (right side) are formed on both sides thereof. ) Is formed. Around that area, a ground 27 is formed.
ガラス基板 2 8上に形成された入力信号線路 2 4に接続された A u からなるメンブレン 2 9は、 2箇所のアンカ 3 0と、 前記両アンカ 3 0を中空で接続するねじれバネである第一のバネ 3 1 と、 第一のバネ 3 1 から左右両側に延びる第二のバネ 3 2と、 第二のバネ 3 2から左 右両側に接続 ·配置された上部電極 3 3 (同図左側)、 及び 3 4 (同図 右側) によって構成されている。 A membrane 29 made of A u connected to an input signal line 24 formed on a glass substrate 28 is a first torsion spring that connects two anchors 30 and the two anchors 30 in a hollow state. One spring 3 1, a second spring 3 2 extending from the first spring 3 1 to the left and right sides, and a second spring 3 2 connected to the left and right sides ), And 3 4 (right side of the figure).
ここで、 入力信号線路 2 4は左右の上部電極 3 3及び 3 4に接続さ れており、 両上部電極下に位置するガラス基板 2 8上には、 下から下 部電極である C uからなる出力信号線路 2 5 (同図左側) 並びに 2 6 (同図右側) と、 窒化ケィ素膜からなる誘電体膜 3 5と、 下から T i / A uの積層膜からなるフローティングメタル 3 6 (左側)、 3 7 (右 側) とが積層されており、 両上部電極に対して距離 = 1 . 0マイクロ メータの空間を設けて左右それぞれに形成されている。 Here, the input signal line 24 is connected to the left and right upper electrodes 33 and 34, and on the glass substrate 28 located below the upper electrodes, from the lower electrode Cu to the lower electrode. Output signal lines 2 5 (left side of the figure) and 2 6 (Right side of the figure), dielectric film 35 made of nitride nitride film, and floating metal 3 6 (left side) and 3 7 (right side) made of Ti / Au laminated film from below The upper electrode is formed on the left and right sides with a space of distance = 1.0 micrometer with respect to the upper electrodes.
この時、 左右それぞれの出力信号線路 2 5並びに 2 6と、 左右それ ぞれの上部電極 3 3、 3 4との対向領域内における、 左右それぞれの フローティングメタル 3 6、 3 7の面積比率は、 両者とも前記対向領 域全体の 3 5 %であり、 前記対向領域外の前記出力信号線路 2 5、 2 6上に位置する前記誘電体膜 3 5上にも、 フローティングメタル 3 6、 3 7をそれぞれ延長して広く形成している。 At this time, the area ratio of the left and right floating metals 3 6 and 3 7 in the area facing the left and right output signal lines 25 and 26 and the left and right upper electrodes 3 3 and 3 4 is Both of them are 35% of the entire opposing region, and floating metal 3 6 and 3 7 are also formed on the dielectric film 35 located on the output signal lines 25 and 26 outside the opposing region. Each is extended and formed widely.
フローティングメタル 3 6、 3 7は、 1 G H z〜 5 G H z程度の高 周波信号に対して 3 0 O k Q程度のインピーダンスを示すインダクタ 素子 3 8、 3 9を介してアース 2 7に接続されている。 Floating metals 3 6 and 3 7 are connected to ground 2 7 through inductor elements 3 8 and 3 9 that exhibit an impedance of about 30 O k Q for high-frequency signals of about 1 GHz to 5 GHz. ing.
前記構造の容量型 M E M S素子は、 入力信号線路 2 4と左右に配置 された出力信号線路 2 5、 2 6のどちらかとの間で直流電圧を印加す ることにより動作する。 The capacitive MEMS element having the above structure operates by applying a DC voltage between the input signal line 24 and either one of the output signal lines 25 and 26 arranged on the left and right.
例えば、 左側の出力信号線路 2 5との間で電圧を印加すると、 左の 上部電極 3 3が線路 2 5に引き付けられて左側のフローティングメタ ル 3 6に接触することにより、 キャパシタ構造を形成する。 この時入 力信号線路 2 4に入力された高周波信号は、 このキャパシ夕を介して 左側の出力信号線路 2 5から出力される。 この時反対側の上部電極 3 4は、 上にはね上がるため、 出力信号線路 2 6と上部電極 3 4のアイ ソレーションが増す。 For example, when a voltage is applied to the left output signal line 25, the upper electrode 3 3 on the left is attracted to the line 25 and comes into contact with the floating metal 36 on the left, thereby forming a capacitor structure. . At this time, the high-frequency signal input to the input signal line 24 is output from the left output signal line 25 through this capacitor. At this time, the upper electrode 34 on the opposite side rises upward, so that the isolation between the output signal line 26 and the upper electrode 34 increases.
逆に、 左側での電圧印加を止め、 右側の出力信号線路 2 6との間で 電圧を印加することにより、 左側の上部電極 3 3は低抵抗金属膜 3 6 から離れてもとの位置に戻る。 そして、 右側の上部電極 3 4が右側の 出力信号線路 2 6に引き付けられて、 右側のフローティングメタル 3 7と接触することにより、 今度は高周波信号が右側の出力信号線路 2 6から出力されるものである。 この時、 反対側の上部電極 3 3は、 上 にはね上がるため、 出力信号線路 2 5と上部電極 3 3のアイソレーシ ヨンが増す。 Conversely, by stopping the voltage application on the left side and applying a voltage to the output signal line 26 on the right side, the upper electrode 3 3 on the left side can be moved away from the low resistance metal film 36. Return. And the upper electrode 3 4 on the right side By being attracted to the output signal line 26 and coming into contact with the floating metal 37 on the right side, a high frequency signal is now output from the output signal line 26 on the right side. At this time, since the upper electrode 33 on the opposite side springs up, the isolation between the output signal line 25 and the upper electrode 33 increases.
前記実施形態によれば、 基本発明の容量型 M E M S素子は、 一般に 一つの信号線路に対して 2つの経路を選択的に切リ替えることができ る S P D Tスィツチと呼ばれる構造である。 本例は本発明の効果を反 映して、 低損失かつアイソレーシヨン特性に優れた高周波信号用のプ ッシュプル型 1 入力 2出力切替スィッチ等を提供できる。 According to the above embodiment, the capacitive M E M S element of the basic invention generally has a structure called S P D T switch that can selectively switch between two paths for one signal line. This example reflects the effect of the present invention, and can provide a push-pull type 1-input 2-output switching switch for high-frequency signals having low loss and excellent isolation characteristics.
前記本発明の容量型 M E M S素子では、 素子内部にインダクタ素子 や抵抗素子を設けた場合について述べたが、 この他、 素子外の外部に 形成した抵抗素子ゃィンダクタ素子にフローティングメタルを接続し ても同様の効果が得られる。 In the capacitive MEMS element of the present invention, the case where an inductor element and a resistance element are provided inside the element has been described. Alternatively, a floating metal may be connected to a resistance element or inductor element formed outside the element. Similar effects can be obtained.
第 1 0 A図、 第 1 0 B図に、 本発明の第 5の実施形態を模式図で示 す。 第 1 0 A図は素子の平面図、 第 1 0 B図は、 その線 B B ' での断 面図である。 本例は、 前記第 1 の実施形態で述べたものとほぼ同一構 造のメンブレンを有しているが、 シリーズ接続型を有するオンノ才フ スィッチに本発明を適用した例である。 シリーズ接続型とは、 信号線 路を入力側と出力側とに分断して、 入力側と出力側との間に電圧を印 加して、 メンブレンが低抵抗金属膜と接触した時に高周波信号が出力 側へ流れる機構のものである。 A fifth embodiment of the present invention is schematically shown in FIG. 10A and FIG. 10B. FIG. 10A is a plan view of the element, and FIG. 10B is a cross-sectional view along the line B B '. The present example is an example in which the present invention is applied to an ONONIS switch having a series connection type, although it has a membrane having substantially the same structure as that described in the first embodiment. In the series connection type, the signal line is divided into the input side and the output side, a voltage is applied between the input side and the output side, and the high frequency signal is generated when the membrane contacts the low resistance metal film. It has a mechanism that flows to the output side.
酸化ケィ素で表面を覆われた S i 基板 4 3上に、 A I の入力信号線 路 4 0が形成され、 該線路 4 0のコの字形領域の内側には、 所定の間 隔を有して A I からなる出力用信号線路 4 1 が形成されている。 そし て、 その周辺にはアース 4 2が形成されている。 入力信号線路 4 0のコの字形領域部に接続され出力信号線路 4 1 を 跨ぐように形成されたメンプレン 4 4は、 4箇所のアンカ 4 5と、 ァ ンカ 4 5に接続されたミアンダ(曲折構造)を有する 4本のパネ 4 6、 及び上部電極 4 7がー体構造を成している。 出力信号線路 4 1 上の一 部及び S i 基板 4 3上の一部は、 酸化タンタル膜からなる誘電体膜 4 8で覆われており、 出力信号線路 4 1 上に位置する誘電体膜 4 8の表 面には、 A uからなる開口部を有するフローティングメタル 4 9が形 成されている。 上部電極 4 7の下面には A uからなる突起 5 0が下方 に向かって複数箇所形成されている。 An AI input signal line 40 is formed on the Si substrate 43 whose surface is covered with silicon oxide, and has a predetermined interval inside the U-shaped region of the line 40. Thus, an output signal line 4 1 made of AI is formed. And there is a ground 42 around it. The membrane 4 4 connected to the U-shaped region of the input signal line 40 and straddling the output signal line 4 1 is composed of four anchors 4 5 and meanders (folds) connected to the anchors 4 5. The four panels 46 6 having the structure) and the upper electrode 47 have a body structure. Part of the output signal line 41 and part of the Si substrate 43 are covered with a dielectric film 48 made of a tantalum oxide film, and the dielectric film 4 located on the output signal line 41 On the surface of 8, a floating metal 49 having an opening made of Au is formed. On the lower surface of the upper electrode 47, a plurality of protrusions 50 made of Au are formed downward.
この時、 出力信号線路 4 1 と上部電極 4 7との対向領域におけるフ ローテイングメタル 4 9の面積比率は、 前記対向領域全体の 1 5 %で あり、 前記対向領域外の前記出力信号線路 4 1 上に位置する前記誘電 体膜 4 8上にも、 対向領域から延長されたフローティングメタル 4 9 を広く形成している At this time, the area ratio of the floating metal 49 in the opposing region of the output signal line 4 1 and the upper electrode 47 is 15% of the entire opposing region, and the output signal line 4 outside the opposing region is 1 Floating metal 49 extending from the opposing region is also widely formed on the dielectric film 48 located above
上部電極 4 7とフローティングメタル 4 9との間の空間の距離は約 1 . 0マイクロメータであり、 上部電極 4 7下面に設けた突起 5 0は 約 0 . 3マイクロメ一夕の高さを有するため、 前記突起 5 0の先端か らフローティングメタル 4 9までの距離は 0 . 7マイクロメータとな つている。 The distance of the space between the upper electrode 47 and the floating metal 49 is about 1.0 micrometer, and the protrusion 50 provided on the lower surface of the upper electrode 47 has a height of about 0.3 micrometer. Therefore, the distance from the tip of the protrusion 50 to the floating metal 49 is 0.7 micrometers.
メンブレン 4 4には、 膜厚が 1 . 5マイクロメ一夕のメツキによる C u (銅) を用いており、 入力信号線路 4 0と出力信号線路 4 1 、 及 びアース 4 2には、 A I (膜厚が 0 . 6マイクロメータ) の単膜を用 いている。 The membrane 4 4 is made of Cu (copper) with a thickness of 1.5 μm, and the input signal line 40, the output signal line 4 1, and the ground 4 2 have AI ( A single film with a thickness of 0.6 micrometers) is used.
中空に浮いたメンブレンを形成するための犠牲層には感光性を有す るポリイミ ド膜を用いており、 犠牲層除去は専用の剥離液を用いたゥ エツ 卜処理と、最終工程として炭酸ガスによる急速乾燥処理を施した。 19 A photosensitive polyimide film is used for the sacrificial layer to form a membrane that floats in the hollow. The sacrificial layer is removed by wet stripping using a special stripper and carbon dioxide as the final step. A quick drying process was applied. 19
31 前記構造の M E M S素子は、 入力信号線路 4 0と出力信号線路 4 1 との間で電圧を印加することによリ、 入力信号線路 4 0に接続されて いる上部電極 4 7が出力用信号線路 4 1 に引き付けられて低抵抗金属 膜 4 9に接触することによりキャパシタ構造を形成する。 この時、 入 力信号線路 4 0に入力された高周波信号が、 このキャパシタを介して 出力信号線路 4 1 に流れるものである。 31 In the MEMS element having the above structure, the upper electrode 4 7 connected to the input signal line 40 is connected to the output signal line by applying a voltage between the input signal line 40 and the output signal line 41. A capacitor structure is formed by being attracted to the line 4 1 and in contact with the low-resistance metal film 49. At this time, the high-frequency signal input to the input signal line 40 flows to the output signal line 41 through this capacitor.
前記実施形態では、 フローティングメタルに蓄積される電荷,を放出 するための抵抗素子等は設けていないが、 対向領域におけるフローテ イングメタルの面積比率が 1 5 %と十分に小さいため、 素子動作に何 ら支障を来たすことなく正常にスィッチとして動作する。 In the above embodiment, a resistance element or the like for discharging the charge accumulated in the floating metal is not provided. However, since the area ratio of the floating metal in the opposite region is as small as 15%, what is necessary for the element operation? It operates normally as a switch without causing any trouble.
前記実施形態によれば、 入力信号のロス (損失) が極めて小さく通 過特性が良好な高周波信号用の容量型 M E M S素子を提供できる。 According to the embodiment, it is possible to provide a capacitive M E M S element for a high-frequency signal having a very small loss (loss) of an input signal and good pass characteristics.
第 6の実施形態である高周波装置を説明する。 第 1 1 A図は、 本発 明の容量型 M E S素子を搭載した高周波装置として、 高周波信号の オン/オフスィツチに前記第 1 の実施形態で説明した本発明の容量型 M E M S素子 (第 1 A図、 第 Ί B図に図示される) を適用した時の、 本 M E M S素子と制御回路の等価回路図である。 M E M S素子の信号 線路 1 及び上部電極 1 2が回路的に示される。 第 1 2 A図及び第 1 2 B図は、 本例におけるおのおのメンブレムのアツプ ' ダウンの状態を 示す M E M S素子の断面図である。 断面図における各部位は第 1 の実 施形態における符号と同じ符号で示される。 A high frequency device according to a sixth embodiment will be described. FIG. 11A shows a capacitive MEMS element according to the present invention described in the first embodiment as a high-frequency device equipped with a capacitive MES element according to the present invention. FIG. 7 is an equivalent circuit diagram of the MEMS element and the control circuit when applying (shown in FIG. B). A signal line 1 and an upper electrode 12 of the M E M S element are shown in a circuit form. FIGS. 12A and 12B are cross-sectional views of the MEMS element showing the up-down state of each membrane in this example. Each part in the cross-sectional view is indicated by the same reference numeral as that in the first embodiment.
M E M S素子の上部電極 1 2は、 信号線路 1 に並列に接続された本 発明の高周波スィッチ 5 2として機能する。 符号 5 3、 5 4はそれぞ れ、 信号線路 1への入力端子、 出力端子である。 下部電極である信号線 路 1 は直流的に浮いており、 信号線路 1 に高周波に対して高いインピ 一ダンスを呈するインダクタンス L及び抵抗 Rを介して制御端子 5 5 が接続されている。 即ち、 制御端子 5 5に制御用の直流電圧を与える と、 インダクタンス L及び抵抗 Rを経て信号線路 1 に同直流電圧が印 加される。 The upper electrode 12 of the MEMS element functions as the high-frequency switch 52 of the present invention connected in parallel to the signal line 1. Reference numerals 5 3 and 5 4 denote an input terminal and an output terminal for the signal line 1, respectively. The signal line 1, which is the lower electrode, floats in a DC manner, and the control terminal 5 5 is connected to the signal line 1 through an inductance L and a resistance R that exhibit high impedance to high frequencies. Is connected. That is, when a control DC voltage is applied to the control terminal 55, the DC voltage is applied to the signal line 1 via the inductance L and the resistance R.
信号線路 1 に直流電圧を印加していない(直流電位 0 V )のときは、 第 1 2 A図に示すように、 上部電極 1 2はパネ 1 1 で機械的に保持さ れている。 従って、 上部電極 1 2は信号線路 1 から十分離れているた め、 上部電極 1 2と信号線路 1 間の容量値は非常に小さい (メンブレ ンアップ、 容量値が約 0 . 5 p F )。 この時、 信号線路 1 に流れる高周 波信号は、 その入力端子 5 3から出力端子 5 4に低損失に伝わる (ス イッチオン状態)。 When no DC voltage is applied to the signal line 1 (DC potential 0 V), the upper electrode 12 is mechanically held by the panel 11 as shown in FIG. 12A. Therefore, since the upper electrode 12 is sufficiently away from the signal line 1, the capacitance value between the upper electrode 12 and the signal line 1 is very small (membrane up, capacitance value is about 0.5 pF). At this time, the high-frequency signal flowing in the signal line 1 is transmitted from the input terminal 53 to the output terminal 54 with low loss (switch-on state).
信号線路 1 に直流電圧を印加した場合、 上部電極 1 2と信号線路 1 との間に静電気力が発生する。 パネの復元力よりも静電気力が強い場 合、 第 1 2 B図に示すように上部電極 1 2は誘電体膜 5上に形成され たフローティングメタル 6に張り付くように接触する (メンプレンダ ゥン、 容量値 =約 4 8 p F ) (スィッチオフ状態)。 When a DC voltage is applied to the signal line 1, an electrostatic force is generated between the upper electrode 12 and the signal line 1. When the electrostatic force is stronger than the restoring force of the panel, the upper electrode 1 2 is in contact with the floating metal 6 formed on the dielectric film 5 as shown in Fig. 1 2 B (Membrane, Capacitance value = approx. 48 p F) (switch-off state).
このスィッチオフ状態のとき、 上部電極 1 2がフローティングメタ ル 6と電気的に接触するため、 上部電極 1 2を介して接続されたフロ 一ティングメタル 6と誘電体膜 5と信号線路 1 からなるキャパシ夕を 構成する。 これにより高周波では信号線路 1 は接地されたのと同等と なる。 従って、 入力端子 5 3から信号線路 1 に流れる高周波信号は、 その大部分が、 上部電極 1 2と接するフローティングメタル 6が誘電 体膜 5に接している部分で反射されるため、 出力端子 5 4にはほとん ど到達しない。 In this switch-off state, the upper electrode 12 is in electrical contact with the floating metal 6, and therefore consists of the floating metal 6, the dielectric film 5 and the signal line 1 connected via the upper electrode 12. It constitutes a capacity evening. As a result, at high frequencies, signal line 1 is equivalent to being grounded. Therefore, most of the high-frequency signal flowing from the input terminal 5 3 to the signal line 1 is reflected at the portion where the floating metal 6 in contact with the upper electrode 12 2 is in contact with the dielectric film 5. Almost no reach.
上部電極 1 2と信号線路 1 との間の静電気力は、 領域 1 4によって 保持し続けられるため、 電圧印加を止めない限り前記キャパシ夕構造 を維持し続ける。 P2004/011219 Since the electrostatic force between the upper electrode 12 and the signal line 1 is continuously held by the region 14, the capacitance structure is maintained unless the voltage application is stopped. P2004 / 011219
33 第 7の実施形態である高周波装置を説明する。 第 1 1 B図は、 前記 第 5の実施形態で説明した本発明のシリーズ接続型を有する容量型 M E M S素子 (第 1 O A図、 第 1 0 B図に図示される) を前記と同様の スィッチに適用した時の、 M E M S素子と制御回路の等価回路図を示 したものである。 入力信号線路 4 0及び出力信号線路 4 1 が回路的に 示される。 符号 7 3、 7 4、 及び 7 5は、 各々入力端子、 出力端子及 び制御端子を示す。 33 A high-frequency device according to the seventh embodiment will be described. FIG. 11B shows a capacitive MEMS element having the series connection type according to the present invention described in the fifth embodiment (shown in FIG. 1 OA and FIG. 10B) similar to the above switch. The equivalent circuit diagram of the MEMS element and the control circuit when applied to is shown. An input signal line 40 and an output signal line 41 are shown in circuit form. Reference numerals 7 3, 7 4, and 7 5 indicate an input terminal, an output terminal, and a control terminal, respectively.
入力信号線路 4 0に接続された上部電極 4 7は、 出力信号線路 4 1 に直列に接続された本発明の高周波スィツチ 7 2として機能する。 こ こで、 出力信号線路 4 1 は高周波に対して高いインピーダンスを呈す るインダクタンス L及び抵抗 Rを介して制御端子 7 5が接続されてい る。 即ち、 制御端子 7 5に制御用の直流電圧を与えると、 インダクタ ンス L及び抵抗 Rを経て出力信号線路 4 1 に同直流電圧が印加される。 出力信号線路 4 1 に直流電圧を印加していない (直流電位 0 V ) の とき、 上部電極 4 7は出力信号線路 4 1 から十分離れているため、 入 力された信号は出力信号線路 4 1 に到達しない。 (メンプレンアップ) 出力信号線路 4 1 に直流電圧を印加した場合、 上部電極 4 7と出力 信号線路 4 1 との間に静電気力が発生する。 この時上部電極 4 7が引 き付けられてフローティングメタル 4 9と接触する (メンプレンダウ ン) ことにより、 上部電極 4 7を介して接続されたフローティングメ タル 4 9と誘電体膜 4 8と出力信号線路 4 1 からなるキャパシタを構 成する。 これにより入力された信号は出力信号線路 4 1 に到達できる ようになる。 The upper electrode 47 connected to the input signal line 40 functions as the high-frequency switch 72 of the present invention connected in series to the output signal line 41. Here, the output signal line 41 is connected to the control terminal 75 via an inductance L and a resistance R that exhibit high impedance to high frequencies. That is, when a control DC voltage is applied to the control terminal 75, the DC voltage is applied to the output signal line 4 1 via the inductance L and the resistance R. When no DC voltage is applied to the output signal line 4 1 (DC potential 0 V), the upper electrode 4 7 is sufficiently away from the output signal line 4 1, so the input signal is the output signal line 4 1 Not reach. (Membrane up) When a DC voltage is applied to the output signal line 41, an electrostatic force is generated between the upper electrode 47 and the output signal line 41. At this time, the upper electrode 4 7 is attracted and comes into contact with the floating metal 4 9 (membrane), so that the floating metal 4 9 and the dielectric film 4 8 connected via the upper electrode 4 7 and the output signal are connected. A capacitor consisting of line 4 1 is constructed. As a result, the input signal can reach the output signal line 4 1.
本実施形態によれば、 本発明の容量型 M E M S素子を搭載した高周 波スィッチは、 高周波信号に対して極めて良好なスイッチング特性を 得ることができる 第 8の実施形態である高周波装置を説明する。 本発明の容量型 M E M S素子を搭載した高周波装置として、 一つの入力信号を 2つの経路 に切リ替えることができるスィッチに、 前記第 4の実施形態で説明し た本発明の容量型 M E M S素子 (第 9 A図、 第 9 B図に図示される) を適用した例である。 第 1 3図に、 本 M E M S素子と制御回路の等価 回路図を示す。 第 1 3図の符号は第 9 A図、 第 9 B図と同一部位は同 —符号が用いられる。 符号 2 4は入力信号線路、 符号 2 5、 2 6はそ れぞれ、 左側の出力信号線路、 右側の出力信号線路を示す。 符号 2 9 はメンブレム、 3 3、 3 4は、 左側の上部電極、 右側の上部電極、 5 6は入力端子、 5 7、 5 8は出力端子、 5 9は制御端子である。 According to this embodiment, the high frequency switch equipped with the capacitive MEMS element of the present invention can obtain extremely good switching characteristics for high frequency signals. A high-frequency device according to the eighth embodiment will be described. As a high-frequency device mounted with the capacitive MEMS element of the present invention, the capacitive MEMS element of the present invention described in the fourth embodiment (switching that can switch one input signal to two paths) ( This is an example of applying Fig. 9A and Fig. 9B). Figure 13 shows an equivalent circuit diagram of the MEMS element and control circuit. The same reference numerals in FIG. 13 are used for the same parts as those in FIGS. 9A and 9B. Reference numeral 24 denotes an input signal line, and reference numerals 25 and 26 denote a left output signal line and a right output signal line, respectively. Reference numeral 2 9 is a membrane, 3 3 and 3 4 are left upper electrodes, right upper electrodes, 5 6 are input terminals, 5 7 and 5 8 are output terminals, and 5 9 is a control terminal.
本実施形態では、 メンブレン 2 9は接地に接続されるのではなく入 力用信号線路 2 4を介して入力端子 5 6に接続されている。 そして、 メンブレン 2 9の左側の上部電極 3 3が出力用信号線路 2 5に高周波 的に接続してその出力端子 5 7に接続するか、 又は右側の上部電極 3 4が出力用信号線路 2 6に高周波的に接続してその出力端子 5 8に接 続するかの動作が行なわれる。 In the present embodiment, the membrane 29 is not connected to the ground but is connected to the input terminal 56 via the input signal line 24. Then, the upper electrode 33 on the left side of the membrane 29 is connected to the output signal line 25 at a high frequency and connected to the output terminal 57, or the upper electrode 34 on the right side is connected to the output signal line 26. Is connected to the output terminal 58 at a high frequency.
出力端子 5 7は、 高周波信号を遮断する抵抗 R 1 及びィンダクタン ス L 1 を介して直流的に 3 Vに、 一方、 出力端子 5 8は、 高周波信号 を遮断する抵抗 R 2及びインダク夕ンス L 2を介して直流的に接地さ れている。 容量 C 1 は、 直流 3 Vの端子を高周波的に接地するために 用いられる。 メンプレン 2 9は、 容量 C 2によって直流的に浮いてお リ、 制御端子 5 9に高周波信号を遮断する抵抗 R 3及びインダクタン ス L 3を介して制御電圧が印加される。 そのため、 制御端子 5 9に 5 Vを印加した場合、 高周波的に入力端子 5 6は出力端子 5 8に接続さ れ、制御端子 5 9に 0 Vを印加した場合、出力端子 5 7に接続される。 以上の第 8の実施形態では、 適用した容量型 M E M S素子の特徴で 2004/011219 The output terminal 5 7 is DC 3 V via a resistor R 1 and an inductance L 1 that block high-frequency signals, while the output terminal 5 8 is a resistor R 2 and an inductance L that blocks high-frequency signals. DC grounded via 2 Capacitance C 1 is used to ground the DC 3 V terminal at high frequency. The membrane 29 is floated in a DC manner by the capacitor C 2, and a control voltage is applied to the control terminal 59 via a resistor R 3 and an inductance L 3 that cut off a high-frequency signal. Therefore, when 5 V is applied to the control terminal 5 9, the input terminal 5 6 is connected to the output terminal 5 8 in terms of high frequency, and when 0 V is applied to the control terminal 5 9, it is connected to the output terminal 5 7. The In the above eighth embodiment, the feature of the applied capacitive MEMS element is 2004/011219
35 あるオフ状態でのアイソレーション特性に優れることから、 低損失か つオフラインへの信号の回り込みが著しく低減された 1 入力 2出力切 り替えスィツチをプッシュプル型の一個の容量型 M E M S素子で実現 することができる。 35 A single push-pull type capacitive MEMS device realizes a 1-input 2-output switching switch with low loss and significantly reduced off-line signal wrapping due to excellent off-state isolation characteristics can do.
第 1 4図は、 第 9の実施形態を説明するブロック図である。 FIG. 14 is a block diagram for explaining the ninth embodiment.
本発明の容量型 M E M S素子を搭載した高周波装置の例で、 携帯電話 等に用いられる高周波フィルタモジュールである。 This is an example of a high-frequency device equipped with a capacitive M EMS element of the present invention, which is a high-frequency filter module used for a mobile phone or the like.
第 1 4図では、 基板 9 1 に、 高周波フィルタ 9 4が配置され、 これ にアンテナ 9 6、 及び反対側に受信系への接続部 9 2、 及び送信系へ の接続部 9 3が接続される。 この場合、 少なくとも高周波フィルタ 9 4の前段、 後段、 もしくは前段と後段両方に、 スィッチが配される。 このスィッチとして、 本発明の第 7の実施形態で示した形態を基本と したスィッチ、 もしくは第 6の実施形態で示した形態を基本としたス ィツチを搭載している形態が用いられる。 In FIG. 14, a high frequency filter 94 is disposed on a substrate 9 1, and an antenna 96, and a connection part 9 2 to a reception system and a connection part 93 to a transmission system are connected to the opposite side. The In this case, a switch is arranged at least in the front stage, the rear stage, or both the front and rear stages of the high frequency filter 94. As this switch, a switch based on the form shown in the seventh embodiment of the present invention or a form mounted with a switch based on the form shown in the sixth embodiment is used.
複数のフィル夕 9 4と前記本発明の容量型 M E M S素子 9 5を搭載 することにより、 本発明の良好なスィツチング特性を得ることが出来 る。 このことを反映して、 アンテナから受信される複数の周波数帯域 の信号を、 低損失かつ低雑音のまま所望の接続経路に切り替えて入力 する、 逆に、 複数の周波数帯域の信号を低損失かつ低雑音のまま出力 することが可能となる。 更には、 出力信号の入力信号側への回り込み も著しく低減できる長所がある。 By mounting the plurality of fills 94 and the capacitive M EMS element 95 of the present invention, the good switching characteristics of the present invention can be obtained. Reflecting this, signals of multiple frequency bands received from the antenna are switched and input to the desired connection path with low loss and low noise. Conversely, signals of multiple frequency bands are low loss and It is possible to output with low noise. Furthermore, there is an advantage that the wraparound of the output signal to the input signal side can be significantly reduced.
前記高周波フィルタと本発明の容量型 M E M S素子は、 本発明の容 量型 M E M S素子が基板材料を選ばないこと、 一般的な半導体製造技 術で作製できること等から、 フィル夕と同じ基板材料上に作製して、 他の受動素子と共にワンチップ化できる利点がある。 The high-frequency filter and the capacitive MEMS element of the present invention are formed on the same substrate material as that of the filter, because the capacitive MEMS element of the present invention can be manufactured by any general semiconductor manufacturing technology. There is an advantage that it can be manufactured and made into one chip together with other passive elements.
更には、 本発明の第 6の実施形態や第 7の実施形態で示した等価回 P2004/011219 Further, the equivalent circuit shown in the sixth embodiment and the seventh embodiment of the present invention. P2004 / 011219
36 路図において、 制御端子から制御信号を送信する S i - M O S F E T 等の能動素子からなるロジック I Cなどとも、 前記と同じ理由により 同一基板上に作製してワンチップ化することが可能である。 In the 36-line diagram, logic IC composed of active elements such as Si-MOFS FE T that transmits a control signal from the control terminal can be fabricated on the same substrate and made into one chip for the same reason as described above.
即ち、 本発明の容量型 M E M S素子は、 能動素子や他の受動素子と 共に、 一般的な半導体製造技術を用いて同一基板上に作製することが できる。 That is, the capacitive M EMS element of the present invention can be manufactured on the same substrate using a general semiconductor manufacturing technique together with an active element and other passive elements.
このことから、 これまで実装基板上にそれぞれを個別に素子を搭載 していた時よりも、 大幅に小型化された高周波装置を提供することが 可能となる。 This makes it possible to provide a high-frequency device that is significantly smaller than when each element has been individually mounted on a mounting board.
本発明の容量型 M E M S素子の構造 ·性質からして、 前記のような スィッチとしての用途以外に、 本素子を一個、 または複数個を並列 - 直列に接続 ·配置することによって、 S P n Tスィッチや広い範囲の 容量値を可変できる可変容量装置にも応用できることはいうまでもな い。 Due to the structure and properties of the capacitive MEMS element of the present invention, in addition to the use as a switch as described above, one or a plurality of this element can be connected and arranged in parallel and in series to provide an SP n T switch. Needless to say, the present invention can also be applied to variable capacity devices capable of changing the capacitance values in a wide range.
第 1 5図に本発明の M E M S素子の製造方法の例示する。 FIG. 15 shows an example of the method for manufacturing the M E M S element of the present invention.
ここでは、 例として前記第 1 図に示した第 1 の実施形態である容量 型 M E M S素子の製造方法を示す。 他の形態もこれに準じて製造する ことが出来る。 Here, as an example, a manufacturing method of the capacitive M EMS element according to the first embodiment shown in FIG. 1 will be described. Other forms can be manufactured in accordance with this.
絶縁基板 3上に、 ホ卜リソグラフィ技術を用いて、 信号線路 1 とァ ース 2の反転パターンからなるリフトオフ用 2層レジストパターンを 形成する。 この後、 電子ビーム蒸着法を用いて、 第 1 層に膜厚 0 . 0 5マイクロメータの T i を、 第 2層に膜厚が 0 . 5マイクロメータの A u (金) を被着する。 そして、 周知のリフ卜オフ法を用いて不要な 金属膜及びレジス卜を除去して、 信号線路 1 パターンとアース 2バタ ーンを形成する (第 1 5図の ( a ) )。 On the insulating substrate 3, a lift-off two-layer resist pattern composed of an inverted pattern of the signal line 1 and the ground 2 is formed by using a photolithography technique. After this, using electron beam evaporation, deposit 0.05 μm of Ti on the first layer and 0.5 μm of Au (gold) on the second layer. . Then, unnecessary metal films and resists are removed using a known lift-off method to form a signal line 1 pattern and a ground 2 pattern ((a) in FIG. 15).
続いて、 膜厚が 0 . 2マイクロメータのアルミナ膜をスパッタ法に P T/JP2004/011219 Subsequently, an alumina film having a thickness of 0.2 micrometers is applied to the sputtering method. PT / JP2004 / 011219
37 より被着した後、 周知の木卜リソグラフィ技術を用いてパターン形成 を行う。 この後、 マスクされていない領域のアルミナ膜をエッチング により除去して、所望の領域のみに誘電体膜 5パターンを形成する(第 1 5図の ( b ) )。 37 After deposition, pattern formation is performed using the well-known Kiso lithography technology. Thereafter, the alumina film in the unmasked region is removed by etching, and the dielectric film 5 pattern is formed only in the desired region ((b) in FIG. 15).
次に、 周知のホトリソグラフィ技術を用いて、 信号線路上の所望の 領域のみが開口されたリフトオフ用の 2層レジス卜パターンを形成す る。 この後、 電子ビーム蒸着法を用いて第 1 層に膜厚 0 . 0 5マイク 口メータの T i を、 第 2層に膜厚が 0 . 2マイクロメータの A u (金) を被着する。 そして、 周知のリフ卜オフ法を用いて不要な金属膜及び レジス卜を除去して、 所望の形状を有するフローティングメタル 6の パターンを形成する (第 1 5図の ( c ) )。 Next, using a well-known photolithography technique, a two-layer resist pattern for lift-off in which only a desired region on the signal line is opened is formed. After this, use electron beam evaporation to deposit a 0.05-micrometer-thickness meter T i on the first layer and a 0.2-micrometer thick Au (gold) on the second layer. . Then, unnecessary metal films and resists are removed by using a known lift-off method to form a pattern of the floating metal 6 having a desired shape ((c) in FIG. 15).
次に、 周知のホ卜リソグラフィ技術を用いて、 絶縁基板 3上の所望 の領域のみが開口されたリフ 卜オフ用の 2層レジス卜パターンを形成 する。 この後、 電子ビーム蒸着法を用いて高抵抗膜を被着する。 そし て、 周知のリフ トオフ法を用いて不要な金属膜及びレジス卜を除去し て、 所望の形状を有する抵抗素子 7パターンを形成する (第 1 5図の ( d ) )。 Next, using a well-known photolithography technique, a two-layer resist pattern for lift-off in which only a desired region on the insulating substrate 3 is opened is formed. Thereafter, a high resistance film is deposited using an electron beam evaporation method. Then, by using a known lift-off method, unnecessary metal film and resist film are removed to form a resistance element 7 pattern having a desired shape ((d) in FIG. 15).
次に、絶縁基板 3全面にポリイミ ド膜を回転塗布により形成した後、 周知のホ卜リソグラフィ技術とエッチング技術を用いて、 所望の領域 のみが開口されたポリイミ ド膜からなる犠牲層パターン 5 1 を形成す る。 ポリイミ ド膜の膜厚は、 高温べ一クによるキュア後の膜厚が 1 . 2マイクロメータとなるよう調整した (第 1 5図の ( e ) )。 Next, after forming a polyimide film on the entire surface of the insulating substrate 3 by spin coating, a sacrificial layer pattern made of a polyimide film in which only a desired region is opened by using a well-known photolithography technique and an etching technique 5 1 Form. The film thickness of the polyimide film was adjusted so that the film thickness after curing with high temperature baking was 1.2 micrometers ((e) in Fig. 15).
次に、 絶縁基板 3上全面に、 周知の電子ビーム蒸着法を用い、 膜厚 が 2 . 5マイクロメータの A u膜を被着する。 この後、 周知のホトリ ソグラフィ技術と A r +イオンミリング法を用いてメンブレン 8を形 成する。 (第 1 5図の ( f ) )。 P T/JP2004/011219 Next, an Au film having a thickness of 2.5 micrometers is deposited on the entire surface of the insulating substrate 3 by using a well-known electron beam evaporation method. After this, the membrane 8 is formed using the well-known photolithography technique and Ar + ion milling method. ((F) in Fig. 15). PT / JP2004 / 011219
38 最後に、 ケミカルドライエッチングにより犠牲層 5 1 を除去するこ とによって、 本発明の容量型 M E M S素子が完成する (第 1 5図の ( g ) )。 38 Finally, the sacrificial layer 51 is removed by chemical dry etching to complete the capacitive MEMS element of the present invention ((g) in FIG. 15).
尚、 抵抗素子ゃィンダク夕を同一基板上に作製するのが困難な場合 には、 フローティングメタルから引き出し線路パターンを形成してお き、 素子の実装段階で外部の抵抗素子、 又は、 インダクタ素子に接続 しても良い。 If it is difficult to fabricate the resistive element on the same substrate, a lead line pattern is formed from the floating metal, and the external resistive element or inductor element is formed at the element mounting stage. May be connected.
前記の製造方法の例では、 各種金属膜の被着に電子ビーム蒸着法を 用いた例を示したが、 この他スパッ夕法等を用いることによって、 金 属膜の表面平坦性が向上し、 ウェハ内の素子の偏差を小さくできる。 又、前記の例では、 A uを主体とした金属膜を用いた例を示したが、 この他 A I や C u等を用いることによって、 材料コス卜を低減できる 効果がある。 In the example of the manufacturing method described above, an example in which the electron beam evaporation method is used for depositing various metal films has been shown. However, by using a sputtering method or the like, the surface flatness of the metal film is improved, Deviation of elements in the wafer can be reduced. In the above example, an example using a metal film mainly composed of A u is shown. However, the use of AI, Cu, or the like has an effect of reducing material costs.
前記のメンプレンの加工にはイオンミリング法を用いた例について 示したが、 この他ケミカルドライエッチング法や、 ウエッ トエツチン グ法、 リフトオフ法等、 使用する金属材料に最も適した加工方法を用 いても良いことは言うまでもない。 Although an example using the ion milling method has been shown for the processing of the above-mentioned membrane, a processing method most suitable for the metal material to be used, such as a chemical dry etching method, a wet etching method, and a lift-off method, can be used. It goes without saying that it is good.
前記の製造方法の例では、 メンブレンの膜厚は 2 . 5マイクロメ一 夕であつたが、 前記実施形態で示しているように、 膜厚はそれぞれの 金属材料で湾曲が発生しない程度が好ましく、 被着方法によっても最 適膜厚は変わるため、 特に限定されるものではない。 In the example of the manufacturing method described above, the film thickness of the membrane was 2.5 μm. However, as shown in the embodiment, it is preferable that the film thickness does not cause bending in each metal material, The optimum film thickness varies depending on the deposition method and is not particularly limited.
メンプレンには電子ビーム蒸着による厚膜の A uを用いて作製した 例を示したが、 この他、 薄膜形成した A u上に電解 A uメツキ等を用 いて厚膜の A uを形成しても良い。 In the case of the membrane, an example of using thick Au by electron beam evaporation was shown, but in addition to this, a thick Au film was formed on the thin Au film using electrolytic Au plating. Also good.
ホ卜レジスト等によるパターニングによって、 所望の領域のみにメ ツキを施す電解 A uメツキ法を用いた方が、材料コス卜を低減できる。 前記 A Uを用いたメンプレンを作製する上で、 前記製造方法では直 接 A uのみを被着形成した例を示したが、 隣接層との接着層としてチ タンの他、 クロム、 モリブデン等を数 n m〜数十 n m程度設けること により、 密着性を高めることができる。 The material cost can be reduced by using the electrolytic Au plating method in which only a desired region is patterned by patterning with a photoresist or the like. In producing the membrane using the AU, in the manufacturing method, an example was shown in which only Au was deposited directly. However, in addition to titanium, several chromium, molybdenum, etc. were used as an adhesive layer with the adjacent layer. Adhesion can be improved by providing about nm to several tens of nm.
前記本発明の主要な構成要素であるフローティングメタルのパター ニングには多層レジス卜技術によるパターニングとリフトオフ法を用 いて形成した例について示したが、 この他 A I 等の他の方法を用いる 場合には、 ケミカルドライエッチングゃゥエツ 卜エッチング法などを 用いても良いことは言うまでもない。 The floating metal patterning, which is the main component of the present invention, has been described with respect to an example of patterning using the multilayer resist technique and the lift-off method. However, when other methods such as AI are used, Needless to say, chemical dry etching, etching, etc. may be used.
誘電体膜にはスパッタ法によるアルミナ膜を用いた例を示したが、 被着方法についてはこの他 C V D法等、 通常の半導体製造工程で一般 的に用いられる他の手法を用いても良い。 Although an example in which an alumina film formed by sputtering is used as the dielectric film has been shown, other methods generally used in the normal semiconductor manufacturing process, such as a CVD method, may be used for the deposition method.
誘電体膜材料に関しては、 アルミナ膜のほか酸化ケィ素膜、 窒化ケ ィ素膜、 酸化タンタル等の、 少なくとも絶縁性に優れ誘電率を有する 固体材料ならば、 如何なる材料でも適用できる。 又、 単膜ではなくこ れら誘電体材料の積層膜を用いても良い。 誘電率が大きければ大きい ほど、 素子の小型化も容易になり、 メンブレンが下がった状態の電気 特性を良くすることができる。 As for the dielectric film material, any material can be applied as long as it is a solid material having at least an insulating property and a dielectric constant, such as an alumina film, a silicon oxide film, a silicon nitride film, and tantalum oxide. Further, a laminated film of these dielectric materials may be used instead of a single film. The larger the dielectric constant, the easier the device can be miniaturized and the better the electrical characteristics when the membrane is lowered.
前記犠牲層 5 1 には標準的なポリイミ ド膜を用いた例を示したが、 感光性を有するポリイミ ド膜を用いると、 ホ卜レジストを塗布する手 間が省けるので、 プロセスの簡略化に繋がる利点がある。 また、 耐熱 性等の問題が生じなければ通常のホ卜レジス卜のみを犠牲層に用いて も良い。 Although an example of using a standard polyimide film for the sacrificial layer 51 has been shown, if a photosensitive polyimide film is used, the process of applying a photoresist can be saved, thus simplifying the process. There is an advantage of being connected. In addition, if no problem such as heat resistance occurs, only a normal polyurethane may be used for the sacrificial layer.
以上の製造方法により作製した本発明の容量型 M E M S素子は、 構 造上の従来の素子との違いは、 対向領域におけるフローティングメタ ルの面積比率を限定することと、 フローティングメタルから高周波信 P T/JP2004/011219 The capacitive MEMS element of the present invention manufactured by the above manufacturing method is different from the conventional element in structure in that the area ratio of the floating metal in the opposing region is limited and the high-frequency signal is transmitted from the floating metal. PT / JP2004 / 011219
40 号に対して抵抗となる物質を介して、 所望の電位を有する物質に直流 的に接続させることである。前記作製プロセスで見る限リ、本発明は、 少ないプロセス増加で、 素子特性に多大な効果を与えることは明らか である。 即ち、 前記本発明の容量型 M E M S素子を前記製造方法に則 つて作製すれば、 高周波信号に対して極めて良好なスイッチング特性 を有する容量型 M E M S素子を低価格で提供することができる。 It is to be connected in direct current to a substance having a desired potential through a substance that becomes resistance to No. 40. As far as the fabrication process is concerned, it is clear that the present invention has a great effect on the device characteristics with a small increase in the number of processes. That is, if the capacitive M E M S element of the present invention is manufactured according to the manufacturing method, a capacitive M E M S element having extremely good switching characteristics for a high frequency signal can be provided at a low price.
以下に、 本願発明の主な実施の形態を列挙する。 The main embodiments of the present invention are listed below.
( 1 ) 少なくとも (1) at least
基板と、 A substrate,
前記基板上に形成されたアンカと、 An anchor formed on the substrate;
前記アンカに連接したパネと、 A panel connected to the anchor;
前記パネに連接し、 前記パネに弾性変形を与えて前記基板の上方で 運動をする上部電極と、 An upper electrode connected to the panel and elastically deforming the panel to move above the substrate;
前記上部電極の下方に位置し、 少なぐとも該上部電極の一部と対向 する領域を有し、 前記基板上に形成された下部電極と、 A lower electrode formed on the substrate, which is located below the upper electrode and has at least a region facing a part of the upper electrode;
前記下部電極が形成された前記基板上で、 基板の垂直方向から見て 少なくとも前記上部電極より広い領域を覆うように、 前記下部電極上 の一部及び前記基板上の一部に形成された誘電体膜と、 On the substrate on which the lower electrode is formed, a dielectric formed on a part of the lower electrode and a part of the substrate so as to cover at least a region wider than the upper electrode when viewed from the vertical direction of the substrate. Body membranes,
前記下部電極上に位置する前記誘電体膜の一部に接して、 少なくと も前記上部電極の一部と対向する形で形成された低抵抗金属膜とを具 備し、 A low-resistance metal film formed in contact with a part of the dielectric film located on the lower electrode and at least facing a part of the upper electrode;
前記上部電極と前記下部電極との間に直流電圧が印加された時、 対 向する前記上部電極と前記下部電極との間で生じる静電気力によって、 前記上部電極が下方に引き付けられ、 前記上部電極の一部が前記低抵 抗金属膜の一部と接触して、 前記上部電極と前記低抵抗金属膜とが電 気的に接続することにより、 前記低抵抗金属膜を介して接続された前 2004/011219 When a DC voltage is applied between the upper electrode and the lower electrode, the upper electrode is attracted downward by the electrostatic force generated between the upper electrode and the lower electrode facing each other, and the upper electrode Part of the low resistance metal film is in contact with a part of the low resistance metal film, and the upper electrode and the low resistance metal film are electrically connected to each other before being connected via the low resistance metal film. 2004/011219
41 記上部電極と、 前記誘電体膜と、 前記下部電極とからなるキャパシ夕 構造が形成されてなる容量型 M E M S素子において、 41 In a capacitive MEM S element in which a capacitor structure comprising the upper electrode, the dielectric film, and the lower electrode is formed.
前記基板の垂直方向から見て、 前記上部電極と前記下部電極とが対 向する領域内の前記下部電極上には、 前記誘電体膜と前記低抵抗金属 膜とが積層された領域と、 前記誘電体膜のみが形成された領域とが混 在し、 前記上部電極と前記下部電極とが対向する領域内の前記誘電体 膜と前記低抵抗金属膜とが積層された領域の面積は、 前記領域内にお いて誘電体膜が露出した領域の面積と比較して、 等しいか、 小さいこ とを特徴とする容量型 M E M S素子。 A region in which the dielectric film and the low-resistance metal film are stacked on the lower electrode in a region where the upper electrode and the lower electrode face each other when viewed from the vertical direction of the substrate; The area where only the dielectric film is formed is mixed, and the area of the area where the dielectric film and the low-resistance metal film are stacked in the area where the upper electrode and the lower electrode face each other is as follows. A capacitive MEMS element characterized by being equal to or smaller than the area of the region where the dielectric film is exposed in the region.
( 2 ) 少なくとも (2) at least
基板と、 A substrate,
前記基板上に形成されたアンカと、 An anchor formed on the substrate;
前記アンカに連接したパネと、 A panel connected to the anchor;
前記パネに連接し、 前記パネに弾性変形を与えて前記基板の上方で 運動をする上部電極と、 An upper electrode connected to the panel and elastically deforming the panel to move above the substrate;
前記上部電極の下方に位置し、 少なくとも該上部電極の一部と対向 する領域を有し、 前記基板上に形成された下部電極と、 A lower electrode formed on the substrate, having a region located below the upper electrode and facing at least a portion of the upper electrode;
前記下部電極が形成された前記基板上で、 基板の垂直方向から見て 少なくとも前記上部電極より広い領域を覆うように、 前記下部電極上 の一部及び前記基板上の一部に形成された誘電体膜と、 On the substrate on which the lower electrode is formed, a dielectric formed on a part of the lower electrode and a part of the substrate so as to cover at least a region wider than the upper electrode when viewed from the vertical direction of the substrate. Body membranes,
前記下部電極上に位置する前記誘電体膜の一部に接して、 少なくと も前記上部電極の一部と対向する形で形成された低抵抗金属膜とを具 備し、 A low-resistance metal film formed in contact with a part of the dielectric film located on the lower electrode and at least facing a part of the upper electrode;
前記上部電極と前記下部電極との間に直流電圧が印加された時、 対 向する前記上部電極と前記下部電極との間で生じる静電気力によって、 前記上部電極が下方に引き付けられ、 前記上部電極の一部が前記低抵 抗金属膜の一部と接触して、 前記上部電極と前記低抵抗金属膜とが電 気的に接続することにより、 前記低抵抗金属膜を介して接続された前 記上部電極と、 前記誘電体膜と、 前記下部電極とからなるキャパシ夕 構造が形成されてなる容量型 M E M S素子において、 When a DC voltage is applied between the upper electrode and the lower electrode, the upper electrode is attracted downward by the electrostatic force generated between the upper electrode and the lower electrode facing each other, and the upper electrode Part of the low The upper electrode connected via the low-resistance metal film by electrically connecting the upper electrode and the low-resistance metal film in contact with a part of the anti-metal film, and the dielectric In a capacitive MEMS element in which a capacitor structure composed of a body film and the lower electrode is formed,
前記低抵抗金属膜は、高周波信号に対して抵抗となる物質を介して、 所望の電位を有する物質と直流的に接続されていることを特徴とする 容量型 M E M S素子。 The capacitive M E M S element, wherein the low-resistance metal film is connected to a substance having a desired potential in a direct current manner through a substance that is resistant to a high-frequency signal.
( 3 ) 前記高周波信号に対して抵抗となる物質は、 少なくとも 1 k Ω以 上で 1 Μ Ω未満の電気抵抗値を示す物質であることを特徴とする前記 項目 ( 2 ) に記載の容量型 M E M S素子。 (3) The capacitive type according to item (2), wherein the substance that is resistant to the high-frequency signal is a substance that exhibits an electrical resistance value of at least 1 kΩ or more and less than 1 Ω. MEMS element.
(4 ) 前記高周波信号に対して抵抗となる物質は、 高周波信号に対し て少なくとも 1 k Ω以上で 1 M Ω未満のィンピーダンスを示すィンダ クタであることを特徴とする前記項目 ( 2 ) に記載の容量型 M E M S 素子。 (4) In the above item (2), the substance that becomes a resistance to the high-frequency signal is an inductor that exhibits an impedance of at least 1 kΩ and less than 1 MΩ with respect to the high-frequency signal. The capacitive MEMS element described.
( 5) 前記所望の電位を有する物質は、 前記上部電極であることを特 徴とする前記項目 ( 2 ) に記載の容量型 M E M S素子。 (5) The capacitive MEMS element according to item (2), wherein the substance having the desired potential is the upper electrode.
( 6 ) 前記所望の電位を有する物質は、 前記下部電極であることを特 徵とする前記項目 ( 2 ) に記載の容量型 M E M S素子。 (6) The capacitive MEMMS device according to item (2), wherein the substance having the desired potential is the lower electrode.
( 7 ) 前記所望の電位を有する物質は、 接地領域 (アース) であるこ とを特徴とする前記項目 ( 2) に記載の容量型 M E M S素子。 (7) The capacitive M E M S element according to item (2), wherein the substance having the desired potential is a ground region (earth).
(8) 前記所望の電位を有する物質は、 直流電圧を印加して前記上部 電極の上下動を制御する制御電極であることを特徴とする前記項目 (8) The item described above, wherein the substance having the desired potential is a control electrode that controls a vertical movement of the upper electrode by applying a DC voltage.
(2 ) に記載の容量型 M E M S素子。 Capacitance type M E M S element according to (2).
( 9 ) 請求項 1 記載の前記誘電体膜のみが形成された領域は、 前記低 抵抗金属膜中において所定の形状を有する開口部によって設けられて いることを特徴とする前記項目 ( 1 ) に記載の容量型 M E M S素子。 2004/011219 (9) In the item (1), the region where only the dielectric film according to claim 1 is formed is provided by an opening having a predetermined shape in the low-resistance metal film. The capacitive MEMS element described. 2004/011219
43 43
( 1 0 ) 前記パネと前記アンカと前記上部電極とが一体構造を成し、 且つ連続した金属体によって形成されていることを特徴とする前記項 目 ( 1 )、 ( 2 ) に記載の容量型 M E M S素子。 (10) The capacitor according to (1), (2) above, wherein the panel, the anchor, and the upper electrode form an integral structure and are formed of a continuous metal body. Type MEMS element.
( 1 1 ) 前記金属体は少なくともアルミニウムを含む単層膜、 もしく はアルミニウム含有膜と他の金属膜との積層膜からなることを特徴と する前記項目 ( 8) に記載の容量型 M E M S素子。 (11) The capacitive MEMS element according to the item (8), wherein the metal body is a single-layer film containing at least aluminum, or a laminated film of an aluminum-containing film and another metal film. .
( 1 2 ) 前記金属体は少なくとも金を含む単層膜、 もしくは金含有膜 と他の金属膜との積層膜からなることを特徴とする前記項目 ( 8) に 記載の容量型 M E M S素子。 (12) The capacitive MEMMS element according to the item (8), wherein the metal body is formed of a single layer film containing at least gold or a laminated film of a gold-containing film and another metal film.
( 1 3 ) 前記金属体は少なくとも銅を含む単層膜、 もしくは銅含有膜 と他の金属膜との積層膜からなることを特徴とする前記項目 (8 ) に 記載の容量型 M E M S素子。 (13) The capacitive MEMMS device according to the item (8), wherein the metal body is formed of a single layer film containing at least copper or a laminated film of a copper-containing film and another metal film.
( 1 4)前記低抵抗金属膜は、少なくともアルミニウムを含む単層膜、 もしくはアルミニウム含有膜と他の金属膜との積層膜からなることを 特徴とする前記項目 ( 1 )、 (2) に記載の容量型 M E M S素子。 (14) The item (1), (2), wherein the low-resistance metal film is composed of a single-layer film containing at least aluminum or a laminated film of an aluminum-containing film and another metal film. Capacitive MEMS element.
( 1 5 ) 前記低抵抗金属膜は少なくとも金を含む単層膜、 もしくは金 含有膜と他の金属膜との積層膜からなることを特徴とする前記項目 (15) The item described above, wherein the low-resistance metal film comprises a single-layer film containing at least gold, or a laminated film of a gold-containing film and another metal film.
( 1 )、 ( 2 ) に記載の容量型 M E M S素子。 (1), Capacitance type M E M S element given in (2).
( 1 6 ) 前記低抵抗金属膜は少なくとも銅を含む単層膜、 もしくは銅 含有膜と他の金属膜との積層膜からなることを特徴とする前記項目 ( 1 )、 ( 2 ) に記載の容量型 M E M S素子。 (16) The low-resistance metal film is a single-layer film containing at least copper, or a laminated film of a copper-containing film and another metal film, The item (1), (2) Capacitive MEMS element.
( 1 7 ) 前記低抵抗金属膜は、 上部電極と下部電極との間に電圧印加 をしないとき、 高周波信号に対して接続されないフローティングメタ ルであることを特徴とする前記項目 ( 1 ) から ( 1 4 ) に記載の容量 型 M E M S素子。 (17) From the item (1), the low-resistance metal film is a floating metal that is not connected to a high-frequency signal when no voltage is applied between the upper electrode and the lower electrode. 1 4) Capacitive MEMS device as described in 4).
( 1 8 ) 前記項目 ( 1 ) から ( 1 5 ) に記載の容量型 M E M S素子が、 11219 (18) The capacitive MEMS device described in the items (1) to (15) is 11219
44 高周波信号のオン/オフスィツチに搭載されていることを特徴とする 高周波装置。 44 A high-frequency device that is mounted on an on / off switch for high-frequency signals.
( 1 9 ) 前記項目 ( 1 ) から ( 1 5 ) に記載の容量型 M E M S素子が、 高周波信号の出力切リ替えスィッチに搭載されていることを特徴とす る高周波装置。 (19) A high-frequency device characterized in that the capacitive MEMS element described in the items (1) to (15) is mounted on a high-frequency signal output switching switch.
( 2 0 ) 前記項目 ( 1 ) から ( 1 5 ) に記載の容量型 M E M S素子が、 携帯電話用の高周波フィルタモジュールに搭載されていることを特徴 とする高周波装置。 (20) A high-frequency device, wherein the capacitive MEMS element described in the items (1) to (15) is mounted on a high-frequency filter module for a mobile phone.
( 2 2 ) 前記項目 ( 1 ) から ( 1 5 ) に記載の容量型 M E M S素子が、 同一基板上において能動素子と共に搭載されていることを特徴とする 高周波装置。 (2 2) A high-frequency device, wherein the capacitive M E M S element described in the items (1) to (15) is mounted together with an active element on the same substrate.
( 2 3 ) 前記項目 ( 1 ) から ( 1 5 ) に記載の容量型 M E M S素子が、 同一基板上において他の受動素子と共に搭載されていることを特徴と する高离波装置。 (2 3) A high-frequency device characterized in that the capacitive M E M S element described in the items (1) to (15) is mounted together with other passive elements on the same substrate.
( 2 4 ) 少なくとも (2 4) At least
基板と、 A substrate,
前記基板上に形成されたアンカと、 An anchor formed on the substrate;
前記アンカに連接したパネと、 A panel connected to the anchor;
前記パネに連接し、 前記パネに弾性変形を与えて前記基板の上方で 運動をする上部電極と、 An upper electrode connected to the panel and elastically deforming the panel to move above the substrate;
前記上部電極の下方に位置し、 少なくとも該上部電極の一部と対向 する領域を有し、 前記基板上に形成された下部電極と、 A lower electrode formed on the substrate, having a region located below the upper electrode and facing at least a portion of the upper electrode;
前記下部電極が形成された前記基板上で、 基板の垂直方向から見て 少なくとも前記上部電極より広い領域を覆うように、 前記下部電極上 の一部及び前記基板上の一部に形成された誘電体膜と、 On the substrate on which the lower electrode is formed, a dielectric formed on a part of the lower electrode and a part of the substrate so as to cover at least a region wider than the upper electrode when viewed from the vertical direction of the substrate. Body membranes,
前記下部電極上に位置する前記誘電体膜の一部に接して、 少なくと P T/JP2004/011219 In contact with a part of the dielectric film located on the lower electrode, at least PT / JP2004 / 011219
45 も前記上部電極の一部と対向する形で形成された低抵抗金属膜とを具 備し、 45 also includes a low-resistance metal film formed to face a part of the upper electrode,
前記基板の垂直方向から見て、 前記上部電極と前記下部電極とが対 向する領域内の前記下部電極上には、 前記誘電体膜と前記低抵抗金属 膜とが積層された領域と、 前記誘電体膜のみが形成された領域とが混 在し、 前記上部電極と前記下部電極とが対向する領域内の前記誘電体 膜と前記低抵抗金属膜とが積層された領域の面積は、 前記領域内の誘 電体膜のみが形成された領域の面積と比較して、 等しいか、 小さいこ とを特徴とする容量型 M E M S素子の製造方法であって、 A region in which the dielectric film and the low-resistance metal film are stacked on the lower electrode in a region where the upper electrode and the lower electrode face each other when viewed from the vertical direction of the substrate; The area where only the dielectric film is formed is mixed, and the area of the area where the dielectric film and the low-resistance metal film are stacked in the area where the upper electrode and the lower electrode face each other is as follows. A method for manufacturing a capacitive MEMS element, characterized in that it is equal to or smaller than the area of the region where only the dielectric film in the region is formed,
前記基板上に金属膜からなる前記下部電極パターンを形成する工程 と、 Forming the lower electrode pattern made of a metal film on the substrate;
前記下部電極を形成した前記基板上に、 前記下部電極上面を含む前 記基板上の所望の位置に誘電体膜からなるパターンを形成する工程と、 前記基板上の前記下部電極と前記誘電体膜とが積層された領域の所 望の位置に、 所望の形状を有する前記低抵抗金属膜からなるパターン を形成する工程と、 Forming a pattern made of a dielectric film at a desired position on the substrate including the upper surface of the lower electrode on the substrate on which the lower electrode is formed; and the lower electrode and the dielectric film on the substrate Forming a pattern made of the low-resistance metal film having a desired shape at a desired position in a region where the layers are stacked;
前記下部電極と前記誘電体膜と前記低抵抗金属膜を形成した前記基 板上に、 所望の形状を有する犠牲膜からなるパターンを形成する工程 と、 Forming a pattern of a sacrificial film having a desired shape on the substrate on which the lower electrode, the dielectric film, and the low-resistance metal film are formed;
前記犠牲膜パターン上を含む前記基板上の所望の位置に、 金属膜を 被着 ·加工することによって、 前記アンカと前記パネと前記上部電極 とを一体構造で形成する工程と、 Forming an anchor, the panel, and the upper electrode in an integrated structure by depositing and processing a metal film at a desired position on the substrate including the sacrificial film pattern;
前記犠牲膜を除去する工程を具備することを特徴とする容量型 M E Capacitive type M E comprising a step of removing the sacrificial film
M S素子の製造方法。 . Manufacturing method of MS element. .
( 2 5 ) 前記基板上の所望の位置に、 所望の電気抵抗値を示す物質か らなるパターンを形成する工程を具備することを特徵とする前記項目 P2004/011219 (25) The above item, characterized by comprising a step of forming a pattern made of a substance exhibiting a desired electric resistance value at a desired position on the substrate. P2004 / 011219
46 46
( 2 0 ) に記載の容量型 M E M S素子の製造方法。 (20) The method for producing a capacitive M E M S element according to (20).
( 2 6 ) 前記基板上の所望の位置に、 所望のインピーダンスを有する ィンダクタを形成する工程を具備することを特徴とする前記項目 ( 2 0 ) に記載の容量型 M E M S素子の製造方法。 (2 6) The method for producing a capacitive M E M S element according to item (2), further comprising a step of forming an inductor having a desired impedance at a desired position on the substrate.
図面に係わる主な諸符号は次の通りである。 The main symbols related to the drawings are as follows.
1 …信号線路、 2…アース、 3…絶縁基板、 5…誘電体膜、 6…フロ —ティングメタル、 7…抵抗素子、 8…メンプレン、 1 0…アンカ、 1 1 …パネ、 1 2…上部電極、 〗 3…信号線路、 1 4…アース、 1 5 •■• S i 基板、 1 6…片持ち梁、 1 7…アンカ、 1 8…パネ、 1 9…上 部電極、 2 0…誘電体膜、 2 1 …フローティングメタル、 2 2…抵抗 素子、 2 4…入力信号線路、 2 5…左側の出力信号線路、 2 6…右側 の出力信号線路、 2 7…アース、 2 8…ガラス基板、 2 9…メンブレ ン、 3 0…アンカ、 3 1 …第一のバネ、 3 2…第二のバネ、 3 3…左 側の上部電極、 3 4…右側の上部電極、 3 5…誘電体膜、 3 6…左側 のフローティングメタル、 3 7…左側のフローティングメタル、 3 8 …左側のインダクタ素子、 3 9…右側のインダクタ素子、 4 0…入力 信号線路、 4 1 …出力信号線路、 4 2…アース、 4 3 S i基板、 4 4…メンプレン、 4 5…アンカ、 4 6…パネ、 4 7…上部電極、 4 8 …誘電体膜、 4 9…フローティングメタル、 5 0…突起、 5 1 …犠牲 層、 5 2…高周波スィッチ、 5 3…入力端子、 5 4…出力端子、 5 5 …制御端子、 5 6…入力端子、 5 7…左側の出力端子、 5 8…右側の 出力端子、 5 9…制御端子、 6 0…ガラス基板、 6 1 …信号線路、 6 2…アース、 6 3…制御端子、 6 4…メンプレン、 6 5…アンカ、 6 6…パネ、 6 7— 1 …アース 6 2との間で静電気力を発生させるため の領域、 6 7 — 2…フローティングメタルと接触する領域、 6 7…上 部電極、 6 9…誘電体膜、 7 0…フローティングメタル、 7 1 …イン ダクタ素子、 7 2…高周波スィッチ、 7 3…入力端子、 7 4…出力端 子、 7 5…制御端子、 9 1 …基板、 9 2…受信系、 9 3…送信系、 9 4…高周波フィルタ、 9 5…本発明の容量型 M E M S素子、 9 6…ァ ンテナ 産業上の利用可能性 1 ... Signal line, 2 ... Ground, 3 ... Insulating substrate, 5 ... Dielectric film, 6 ... Floating metal, 7 ... Resistance element, 8 ... Memprene, 1 0 ... Anchor, 1 1 ... Panel, 1 2 ... Top Electrode,〗 3 ... Signal line, 1 4 ... Earth, 1 5 • ■ • Si substrate, 1 6 ... Cantilever, 1 7 ... Anchor, 1 8 ... Panel, 1 9 ... Top electrode, 2 0 ... Dielectric Body film, 2 1 ... Floating metal, 2 2 ... Resistive element, 2 4 ... Input signal line, 2 5 ... Output signal line on the left side, 2 6 ... Output signal line on the right side, 2 7 ... Ground, 2 8 ... Glass substrate 2 9 ... Membrane, 3 0 ... Anchor, 3 1 ... First spring, 3 2 ... Second spring, 3 3 ... Left upper electrode, 3 4 ... Right upper electrode, 3 5 ... Dielectric Membrane, 3 6… Left side floating metal, 3 7… Left side floating metal, 3 8… Left inductor element, 3 9… Right inductor element, 4 0… Input signal line, 4 1… Force signal line, 4 2 ... Earth, 4 3 Si substrate, 4 4 ... Membrane, 4 5 ... Anchor, 4 6 ... Panel, 4 7 ... Upper electrode, 4 8 ... Dielectric film, 4 9 ... Floating metal, 5 0 ... protrusion, 5 1 ... sacrificial layer, 5 2 ... high frequency switch, 5 3 ... input terminal, 5 4 ... output terminal, 5 5 ... control terminal, 5 6 ... input terminal, 5 7 ... left output terminal, 5 8 ... right output terminal, 5 9 ... control terminal, 6 0 ... glass substrate, 6 1 ... signal line, 6 2 ... ground, 6 3 ... control terminal, 6 4 ... mamprene, 6 5 ... anchor, 6 6 ... panel, 6 7— 1… Area for generating electrostatic force with earth 6 2, 6 7 — 2… Area in contact with floating metal, 6 7… Upper electrode, 6 9… Dielectric film, 7 0… Floating metal, 7 1 ... in Ductor element, 7 2 ... High frequency switch, 7 3 ... Input terminal, 7 4 ... Output terminal, 7 5 ... Control terminal, 9 1 ... Board, 9 2 ... Receiving system, 9 3 ... Transmission system, 9 4 ... High frequency filter 9 5 ... Capacitive MEMS element of the present invention, 9 6 ... Antenna Industrial applicability
本発明の素子は、電気信号のスィツチ素子として用いることが出来る。 特に、 高周波信号に有用であり、 同素子を用いた高周波装置を提供す ることが出来る。 又、 こうした素子を製造する方法を供することが出 来る。 The element of the present invention can be used as an electric signal switching element. In particular, it is useful for high-frequency signals, and a high-frequency device using the element can be provided. It is also possible to provide a method for manufacturing such an element.
Claims
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/589,758 US20070278075A1 (en) | 2004-07-29 | 2004-07-29 | Capacitance Type Mems Device, Manufacturing Method Thereof, And High Frequency Device |
| PCT/JP2004/011219 WO2006011239A1 (en) | 2004-07-29 | 2004-07-29 | Capacitive mems device and process for fabricating same, and high-frequency device |
| CNA2004800420676A CN1922755A (en) | 2004-07-29 | 2004-07-29 | Capacitive MEMS element, manufacturing method thereof, and high-frequency device |
| JP2006527763A JPWO2006011239A1 (en) | 2004-07-29 | 2004-07-29 | Capacitive MEMS element, manufacturing method thereof, and high-frequency device |
| DE112004002746T DE112004002746T5 (en) | 2004-07-29 | 2004-07-29 | Capacitive MEMS device, process for its manufacture, and high frequency device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2004/011219 WO2006011239A1 (en) | 2004-07-29 | 2004-07-29 | Capacitive mems device and process for fabricating same, and high-frequency device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2006011239A1 true WO2006011239A1 (en) | 2006-02-02 |
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ID=35785999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2004/011219 Ceased WO2006011239A1 (en) | 2004-07-29 | 2004-07-29 | Capacitive mems device and process for fabricating same, and high-frequency device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20070278075A1 (en) |
| JP (1) | JPWO2006011239A1 (en) |
| CN (1) | CN1922755A (en) |
| DE (1) | DE112004002746T5 (en) |
| WO (1) | WO2006011239A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20070278075A1 (en) | 2007-12-06 |
| JPWO2006011239A1 (en) | 2008-05-01 |
| CN1922755A (en) | 2007-02-28 |
| DE112004002746T5 (en) | 2008-03-06 |
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