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WO2006011189A1 - Ordinateur parallèle - Google Patents

Ordinateur parallèle Download PDF

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Publication number
WO2006011189A1
WO2006011189A1 PCT/JP2004/010610 JP2004010610W WO2006011189A1 WO 2006011189 A1 WO2006011189 A1 WO 2006011189A1 JP 2004010610 W JP2004010610 W JP 2004010610W WO 2006011189 A1 WO2006011189 A1 WO 2006011189A1
Authority
WO
WIPO (PCT)
Prior art keywords
subtask
processor
task
processors
attribute information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2004/010610
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English (en)
Japanese (ja)
Inventor
Atsuo Ozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2004/010610 priority Critical patent/WO2006011189A1/fr
Priority to JP2006527723A priority patent/JP4082439B2/ja
Publication of WO2006011189A1 publication Critical patent/WO2006011189A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5017—Task decomposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a parallel computer in which a single task is divided into a plurality of execution units, and each execution unit is processed in parallel by a plurality of processors, and the processing capability of the entire parallel computer is maintained. On the other hand, it relates to a technology for saving power consumption.
  • the present invention relates to a technique for saving power consumption of the entire parallel computer while satisfying a restriction on processing completion time imposed on each task.
  • Portable information devices such as mobile phones and notebook computers are required to be lightweight.
  • these devices often incorporate large-capacity batteries to drive processors with a high operating frequency for a long time.
  • the large capacity and the heavy weight of the battery are a major problem in reducing the weight of portable information devices.
  • a technology is known that changes the operating frequency of the processor according to the type and content of processing to extend the duration while reducing the capacity of the battery and reducing its weight! . This is based on the principle that the power consumption can be saved by operating the processor at a low operating frequency! /.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2002-99432
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2002-215599
  • Patent Document 2 is based on the processing completion time of other processors, and is not based on the time constraint of the processing itself. Therefore, the method disclosed in Patent Document 2 cannot be applied to a system that has time constraints on processing.
  • Patent Document 1 is based on a system in which a single processor power is also configured.
  • the method depends on the minimum processing unit between tasks. It is clear that it cannot be applied without satisfying the condition that there is no relationship or that the influence of the dependency relationship can be ignored.
  • the present invention was made to solve such a problem, and provides a computer that completes a single task by parallel processing within a requested processing time while reducing power consumption.
  • a parallel computer is a parallel computer that divides a task into a plurality of processing units and executes the divided processing units in parallel.
  • a subtask attribute information file that holds attribute information of the subtask divided by the task dividing means
  • a plurality of processors configured to control power consumption from the outside and executing subtasks divided by the task dividing means
  • the subtask divided by the task dividing means is distributed to the plurality of processors to instruct execution of the subtask and the plurality of processors.
  • the concept of subtask includes a partial instruction code sequence formed by dividing a part of an instruction code sequence constituting a task, but it goes without saying. Instead of dividing the instruction code itself that constitutes the task, the data that is the processing target of the task that is not divided is divided into a plurality of processing units.
  • the power consumption of each processor is controlled while distributing the subtask to a plurality of processors based on the attribute information of the subtask divided into the task powers. As a result, the power consumption can be reduced while satisfying the task execution time constraints.
  • FIG. 1 is a block diagram showing a configuration of a parallel computer according to Embodiment 1 of the present invention
  • FIG. 2 is a diagram showing the characteristics of the processor of the parallel computer according to Embodiment 1 of the present invention.
  • FIG. 3 is a flowchart of the parallel computer according to Embodiment 1 of the present invention.
  • FIG. 4 is a diagram for explaining a method for selecting an execution method according to the first embodiment of the present invention.
  • FIG. 5 A diagram showing the relationship of boundary values to be considered when selecting various execution methods.
  • FIG. 6 is a diagram showing the relationship between the number of processors and power consumption.
  • FIG. 1 is a block diagram showing a configuration of a parallel computer according to Embodiment 1 of the present invention.
  • a task input terminal 10 is an input terminal for inputting a task to be processed by the parallel computer.
  • a task is a central processing unit (Central Processing Unit)
  • the unit of work in the interior refers to a predetermined processing unit composed of a combination of computer instruction codes, so that the power of the computer operator and system administrator can be easily and easily handled. From this point of view, the task size is often determined. However, no matter what processing unit is used to configure one task, the features of the present invention are not lost.
  • a task input terminal 10 is provided so that an external force can also input a task.
  • the computer may be configured to autonomously acquire tasks stored in an external storage device under the control of the operating system. Computer systems having such a configuration are very common and need not be explained again here.
  • the task dividing means 11 is a part that divides a single task input from the task input terminal 10 into a plurality of subtasks.
  • the subtask attribute information file 12 is a file for storing additional information about each subtask, and is a random access memory (RAM), a fixed disk device or other storage device or storage element, or a storage device. Data stored by the circuit. Note that only the subtask attribute information file 12 need not physically exist alone, for example, a program executable file for a task input from the task input terminal 10 (instruction code and static data are stored, It is also possible to adopt a configuration in which the program is stored in a binary program file) and handled as the subtask attribute information file 12.
  • RAM random access memory
  • the control processor 13 as the processor control means distributes the subtask divided by the task dividing means 11 to a plurality of processors having 14 N power while referring to the subtask attribute information file 12. Above, it is the part that instructs the processor to which the subtask is distributed to process the subtask.
  • the control processor 13 It has the feature of controlling the power consumption of the computing processors 14 1 1 14 N, and it aims to reduce power consumption while satisfying the task execution time constraints.
  • the task instruction code string is divided into instruction code strings having a smaller number of steps, and the data to be processed by the task is divided into smaller size data. It is conceivable that the configuration When sub-tasks are configured by dividing instruction code strings, they should be expressed as executing sub-tasks, and when sub-tasks are configured by dividing data, they should be expressed as processing sub-tasks. However, in order to simplify the notation here, we will use the expression that uniformly “processes subtasks”. However, the expression “process subtask” t includes the meaning of “execute subtask” t.
  • the arithmetic processor 14 1-1 14 N is an arithmetic device or a circuit for processing each subtask divided by the task dividing means 11. Furthermore, the computing processor 14 1 1 14 N can control the external power consumption. As a method of controlling power consumption, the arithmetic processor 14 1 1 14 N itself has an interface that directly changes the power consumption, and the power consumption is changed via this interface. In addition, if the instruction code of each subtask is decoded and executed based on the clock signal input from the external power! /, This clock signal can be changed. It is also possible to change the power consumption through.
  • FIG. 2 is a diagram showing an example of the characteristics of the processor for operation 14-1 and the processor 14N.
  • the arithmetic processor 14 1 one processor 14 N can select at least three operation states of “high-speed operation state”, “standard operation state”, and “idle state”.
  • the processor 14—one processor 14 N operates at a voltage of 1.8 V and consumes 0.5 W of power with an operating frequency of 380 MHz.
  • the arithmetic processor 14-1 processor 14N operates at an operating frequency of 152MHz and a voltage of 1.OV, and its power consumption is 0.053W.
  • the operating frequency is 33 MHz
  • the voltage is 1. OV
  • the power consumption is 0, 0115W.
  • an electronic circuit generally has a higher operating frequency. It is known that the power consumption per unit time increases as the number of times increases. The relationship between power consumption P, operating frequency F, and power supply voltage V is given by equation (1) when leakage power is ignored. Where t is the signal transition rate and C is the capacitance.
  • the arithmetic processor 14 1-1 14 N has, for example, a configuration that does not change three operation states including a “high-speed operation state”, a “standard operation state”, and an “idle state”.
  • the processor that can be used in the present invention is not limited to such an example.
  • a practical sales processor Since the clock speed can vary depending on the temperature of the environment in which the computer is placed, a practical sales processor has a margin for the variation of the external clock. Such a sales processor operates faster when the external clock is increased, and operates slower as the external clock is decreased. Therefore, unlike the processor shown in the above example, it actively supports multiple operating states, and even when using a sales processor, it can proactively provide a margin for external clock fluctuations. This makes it possible to use the features of the present invention. Recently, processors that can reduce power consumption have been widely used in mopile applications and are well known in the art, so we will not go into further detail here.
  • the arithmetic processors 14 1 1 14 N should not be construed as being limited to each being, for example, an independent LSI component.
  • a vector processor is a single arithmetic device, but can execute a plurality of operations in parallel.
  • the configuration of the computer shown in Fig. 1 includes such a configuration.
  • the control processor 13 and the arithmetic processor 14 1 1 14 N can be replaced with a completed computer such as a personal computer or a workstation. That is, the present invention can also be applied to a parallel computing system in which a plurality of computers are combined.
  • the task dividing means 11 may be configured as an independent control circuit or control device, or may be configured as a computer program executed by the control processor 13.
  • control processor 13 is configured to fetch the processor in a general processor architecture. If the task and subtask are regarded as a machine language instruction code and microcode in the processor, the entire system shown in Fig. 1 can be regarded as a single processor. . In this case, array processing by vector operation is regarded as a task, and processing of each element of the array is regarded as a plurality of subtasks. Furthermore, the task decomposition means 11 would be a compiler (language processor) that supports vector processing instructions called vectory compilers, and a decoder that decodes vector operation instructions into microcode. . Such compiler technology is already known.
  • the relationship between processes and threads may be considered to correspond to the relationship between tasks and subtasks.
  • the relationship between tasks and subtasks is flexibly defined based on the system design. In this way, the configuration in Figure 1 can be applied at various levels.
  • FIG. 3 is a flowchart showing the operation of this parallel computer.
  • the task dividing means 11 divides the task into subtasks (step S101).
  • the control processor 13 acquires a task processing time limit T (step S102).
  • the processing time limit T is a value predetermined by the system.
  • T is determined from the purpose of the user or the system. If the system is intended to perform signal processing of input signals (for example, some observations) that occur every fixed time (sampling time), the sampling time, which is the period for acquiring these signals, is limited. It will correspond to time T.
  • the processing time limit T may be determined from the configuration of the parallel computer without the processing time limit being determined from the external specification. For example, when configuring a processor that completes most instructions within one clock with an external clock, the time limit corresponding to one external clock is the processing time limit T.
  • the control processor 13 calculates a task processing time tmin when the arithmetic processors 14 1 and 14 N are set to the high-speed operation state (step ST103).
  • the estimated process completion time of each subtask must be divided in advance. Required. Therefore, for example, the processing time in the high-speed operation state and the standard state of each subtask by any of the processors 14 1 to 14 N is measured in advance and stored in the subtask attribute information file. Then, the control processor 13 obtains the processing time of the subtask according to the type of the subtask, and calculates the processing time tmin of the task.
  • the processing time of the subtask is measured only for one of the high-speed operation state and the standard operation state! /, Or only one of them, and the operation frequency of the measured processing time and the other operation state are measured.
  • the other processing time may be approximated by multiplying the ratio with the operating frequency.
  • step ST104 Yes
  • the processor capacity for computing 14 1 1 14 N exceeds the processing capacity of the subtask to be processed. Since there is enough processing capacity, the process moves to the power saving process after step ST105.
  • Step ST106 Execution method 1
  • step ST111 The processing after step ST111 will be described later.
  • step ST105 the control processor 13 sets any one of the arithmetic processors 14-1 to 14N to the standard operation state, and performs all subtasks only for the processor set to the standard operation state.
  • tstd is calculated based on the processing time of the subtask as in the calculation of tmin in step ST103. If this tstd force is exceeded (ST107: Yes), processing by any one of the processors 14 1 1 14 N must satisfy the request to complete the task within the processing time limit T. Since this is not possible, the process proceeds to parallel processing using a plurality of processors after step ST1 09.
  • processor 14 1 Set the status (step ST108). Power! Then, the other processors excluding the arithmetic processor 14-1, that is, the arithmetic processors 14 2-14 N are set in an idle state.
  • Step ST109 select one of the following processing methods (execution method 3 and execution method 4) based on the nature of the subtask and the nature of each processor (operation frequency, power consumption): Based on the processing method, calculate the number of processors n and the operating frequency used for subtask processing. (Step ST109).
  • Arithmetic processor 14 Selects one of the 14 N computing processors, sets the operating frequency of the selected computing processor to the operating frequency ⁇ 8 of the high-speed operating state, and uses this computing processor to Perform subtasks. Arithmetic processors other than the selected arithmetic processor are set in an idle state.
  • Arithmetic Processor 14 1 Selects n computing processors out of 14N, and selects the selected n processors (2 ⁇ n) with the operating frequency of the selected computing processor as the operating frequency O in the standard operating state. It is executed by a processor for ⁇ N). Arithmetic processors other than the selected n arithmetic processors are set in an idle state.
  • FIG. 4 shows a time chart example of execution method 3 and execution method 4 within the processing constraint time (T). Since the difference between the two is the part within the bold frame, the power consumption for this part is Compare competence.
  • the processing constraint time (T) can be expressed as equation (2) because the processing time of execution method 4 is longer than that of execution method 3.
  • ⁇ is the execution time when one piece of processing data is processed by one processor at the operating frequency ⁇ . ⁇ indicates the number of processors.
  • T (n-1) -TC + T a / ⁇ (2)
  • Equation (3) shows the power consumption C2 [W's] by execution method 3 in this case.
  • the first term of Equation (3) is the power consumption required to process data at the operating frequency ⁇
  • the remaining second term is the idle processor (Fig. 4: processor for computation).
  • This figure shows the amount of power consumed by the processor 1 (14) and the processor ( Figure 4: processor 14 1) during the idle period after data processing.
  • k ⁇ Z j8.
  • C2 Pj8 -k-Ta + k- ⁇ ⁇ ⁇ ⁇ (n-1)
  • equation (4) shows the power consumption C3 [W's] by execution method 4 in this case.
  • the first term in equation (4) is the sum of the power consumption required for communication processing and the power consumption in all idle states, and the second term represents the power consumption required for data processing. It is a thing.
  • C3 (n-1) -Pa -Tc + (1 / ⁇ ) ⁇ ⁇ ⁇ ⁇
  • Equation (5) can be derived from equations (3) and (4).
  • p represents the ratio of communication processing time to data processing (TcZT a).
  • FIG. 5 shows the value of p with respect to the number of arithmetic processors ( n ⁇ 2) when the values in FIG. 2 are given to the parameters on the right side of equation (5).
  • Execution methods 3 and 4 and superiority and inferiority of 1 and 4 can be obtained by analyzing the target task and finding the optimal number of processors and the p value in that case for power saving in execution method 4. This can be determined from FIG.
  • Fig. 6 shows the ratio (E3ZE4) of the power consumption to execution method 4 when execution method 3 is selected / executed with respect to an appropriate p ( ⁇ 0.05). If p ⁇ 0.05, the effect of parallel processing is always obtained when the number of processors is in the range of 2-20. From this result (Fig. 6), it can be confirmed that when the value of is constant, this ratio decreases as the number of processors increases. Conversely, if p decreases, this ratio increases. Therefore, if / 0 becomes smaller as the number of arithmetic processors increases, the rate of reduction of this ratio will be smaller during that state.
  • step S 109 the execution method 3 or the execution method 4 is selected from the relationship of the expression (5) for the control processor 13.
  • C5 (m-l)-[2-Pj8 + (m-2) -Py] -k-Tc + Pj8 -Tj8
  • Equation (6) the first and second terms in Equation (6) are the power consumption of the processor to which the process is assigned, and the third and fourth terms are the idle processor and the process. It shows the power consumption of a processor that is in an idle state because it has been allocated but is in a wait state after processing is complete.
  • C5-C3 Tc- ⁇ 2-k- (m— 1) ( ⁇ - ⁇ ) ⁇ 2 ⁇ ( ⁇ — 1) ⁇ ( ⁇ - ⁇ ) ⁇
  • control processor 13 distributes the subtasks to the arithmetic processors 14 1 to 14 based on the execution method determined in step S109, and instructs the execution of the subtasks (step ST110).
  • the task is divided into subtasks, and any one of the execution methods 1 and 4 is executed based on the subtask dependency. Since the task is selected and executed in parallel, the total power consumption of multiple processors can be reduced while satisfying the task processing constraint time.
  • control processor 13 is a dedicated processor for distributing subtasks.
  • the load of the control processor 13 may be lower than that of the processor 14-1 to 14N. So the processor 14 1 1 14 N functions Configure it for use!
  • the present invention can be widely applied to a computer processing system for parallel operations such as a parallel computer system having a plurality of computers in a cluster configuration or a parallel processing processor having a plurality of operation instruction processing units.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
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Abstract

Il est possible de traiter en parallèle une tâche pendant le temps limite de traitement de la tâche tout en réduisant la consommation d’énergie. Un ordinateur parallèle divise une tâche en une pluralité d’unités de traitement et exécute les unités de traitement divisées en parallèle. L’ordinateur parallèle comprend : des moyens de division de tâche (11) pour diviser une tâche en une pluralité d’unités de traitement qui peuvent être exécutées dans des processeurs séparés et sortir les unités de traitement divisées sous forme de sous-tâches ; un fichier d’information d’attributs de sous-tâches (12) pour détenir de l’information d’attributs sur les sous-tâches divisées par les moyens de division de tâche (11) ; des processeurs (14-1 à 14-N) configurés de sorte que la quantité de consommation d’énergie est commandée à partir de l’extérieur et en train d’exécuter les sous-tâches divisées par les moyens de division de tâche (11) ; et des moyens de commande de processeurs (13) pour répartir les sous-tâches divisées par les moyens de division de tâche (11), vers les processeurs (14-1 à 14-N) en fonction de l’information d’attributs de sous-tâches détenue dans le fichier d’information d’attributs de sous-tâches (12), donner des instructions sur l’exécution des sous-tâches, et commander la quantité de consommation d’énergie des processeurs (14-1 à 14-N).
PCT/JP2004/010610 2004-07-26 2004-07-26 Ordinateur parallèle Ceased WO2006011189A1 (fr)

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JP2006527723A JP4082439B2 (ja) 2004-07-26 2004-07-26 並列計算機

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