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WO2006010991A1 - Oscillateur a reseau et generateur d'horloge polyphasee - Google Patents

Oscillateur a reseau et generateur d'horloge polyphasee Download PDF

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Publication number
WO2006010991A1
WO2006010991A1 PCT/IB2004/002410 IB2004002410W WO2006010991A1 WO 2006010991 A1 WO2006010991 A1 WO 2006010991A1 IB 2004002410 W IB2004002410 W IB 2004002410W WO 2006010991 A1 WO2006010991 A1 WO 2006010991A1
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Prior art keywords
load
voltage
transistor
transistors
buffer stage
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Inventor
Igor Anatolievich Abrosimov
Sergey Mikhailovich Dedov
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator

Definitions

  • the present invention relates generally to array oscillator circuits for providing a plurality of phases which have stable phase relationships.
  • the present invention is particularly applicable to the generation of poly ⁇ phase clocks for receivers of very high speed interfaces which employ an over- sampling technique, or multiplexing, and for high speed logic.
  • the single inverter is replaced by a series of inverters, such that there is sufficient delay through the inverters to allow time for the output to slew from a logical low to a logical high, and high to low, depending on the state of the oscillation.
  • the ring oscillator comprises an inverter with feedback from the last stage to the first.
  • the inverter may be formed by one stage, or an odd number of inverting stages with any number of non-inverting stages, such that there is sufficient delay through the series inverters for the signal to swing from 0 to 1.
  • the inverter may be an inverting amplifier, NOR gate, or anything else that gives a 180 degrees phase shift with gain. Different gates or circuits can be used in the chain. The key point is that there is a 180 degrees phase shift from the input to the output of the chain.
  • the period of the oscillation is twice the delay through the chain and any filter components in the chain.
  • the inverter For example, if one inverter has a 150ps delay time and has a 100ps rise time and 100ps fall time, then simply coupling the output to the input of the inverter will produce a digital ring oscillator.
  • the speed of the oscillation can be varied by adding delay to the feedback or slowing down the inverter further.
  • an inverter has a 50ps delay and a 100ps rise and fall time, then if the output of this inverter is connected to the input, the peak to peak swing would not be a full logic 1 or 0. In this case, at least 3 identical inverters would have to be used, or one inverter and two non-inverting buffers.
  • a ring oscillator built out of a large number of inverting stages will have more than one mode.
  • jitter eventually causes clocks to coincide, such that the only long term stable state is a 180 degrees phase shift through the chain, and this is known as the fundamental mode.
  • High speed digital systems commonly use clocks derived from a Voltage Controlled Oscillator (VCO), which is often a ring oscillator locked using a Phase Locked Loop (PLL) to a reference clock such as from a crystal oscillator.
  • VCO Voltage Controlled Oscillator
  • PLL Phase Locked Loop
  • the frequency of the VCO is a function of the divide chain in the PLL and the crystal reference frequency.
  • the k of the PLL that is the ratio of the feedback to the ring oscillator frequency, depends on how the ring oscillator is controlled.
  • phase resolution can be achieved using a ring oscillator and any multi-tap delay element.
  • the distribution of the phases tends to be uneven because the delay through the gain stage or inverting stage is usually much larger than the spacing between the taps on the delay chain.
  • a further factor in the design of poly-phase clocks is the need for low jitter.
  • some standards such as the 10.3Gbps XFI bus from the XFP consortium, or SONET OC192, specify very low levels of jitter. This requires attention to minimise noise from any poly-phase clock.
  • One method of reducing the phase noise further is to globally lock the oscillator. In the most general sense, this is described in the paper "Phase Noise in Externally Injection-Locked Oscillator Arrays" by H-C Chang, X Cao, M. Vaughan, U. Mishra and R. York, in IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 11 , Nov 1997.
  • Multiple ring oscillators or registers can be used to generate a poly-phase clock, such as in US 5,268,656, and US 5,347,234, but these designs are limited to lower frequencies than are considered here and the phase relationship tends to be unstable.
  • any type of inverting buffer can be used in a ring oscillator.
  • Differential buffers are well known, and these are used in US 5,426,398. It is noted that the buffers in the implementation described in US 5,426,398 suffer from speed limits due to the use of P-type pull up transistors and common biasing.
  • array oscillator is used in US 5,717,362 and its continuation US 5,475,344 by Maneatis and Horowitz after first use in 1993 ISSCC paper describing a similar circuit. Both these patents contain discrepancies between text and figures, which makes it very hard to understand what is being described, and none of the circuits described in the patent were found by the inventors to work when simulated with SPICE. However, the fact that the inventions described in these patents are aimed at achieving the same technical effect as the present invention, makes these two patents worthy of detailed analysis.
  • Both US 5,717,362 and its continuation as US 5,475,344 refer to an array of differential or single ended inverting buffers with “substantially identical electrical characteristics". That is every stage has a 180 degrees phase shift at DC if the inputs to the stage are the same.
  • Each inverter stage comprises two inverters that are effectively connected in parallel, one being marked as a C (coupling) input and the other an S (series) input.
  • the output is the mean of the two inputs, and this has the effect that the output is half way in phase between the phase of the two inputs during dynamic operation of the oscillator.
  • the array is built from rows of these inverters "coupled together in a particular manner".
  • Figs. 3A and 3B refer to a fundamental mode, where there is a 180 degrees phase shift through each ring, but Fig. 3 clearly shows the second mode (2 x the fundamental, with an entire period existing within each ring).
  • the text relating to Fig. 2 also describes fundamental mode operation when it states "The delay through each buffer inverter is equivalent to the period of the reference signal divided by 2N". In fact, second mode operation is divided by N.
  • Fig. 8 On column 7 the inventors describe Fig. 8 and again state it is operating in fundamental mode: "The oscillation period for each ring R is equivalent to a buffer delay scaled by twice the number of bugger stages included therein".
  • Fig. 8 The oscillation period for each ring R is equivalent to a buffer delay scaled by twice the number of bugger stages included therein.
  • the inventors state "and if it is assumed the array is phase locked to a reference clock signal of period T, then the delay D of each buffer stage may be expressed as T/2N". The inventors then give various equations, all describing fundamental mode. The inventors then state "The period of oscillation T(C ) of each ring R within the array oscillator, as a function of coupling factor C, is equivalent to 2ND(C).” The coupling factor is 1 , therefore this is a fundamental mode oscillation. There are five stages in Fig. 4, so in fundamental mode each stage has a 36 degree phase shift (180 degrees divided by 5 is 36).
  • the coupling (c) inputs to each of the inverter stages do not have any stable phase relationship to the (s) inputs with the feedback shown in Fig. 4: for example, the feedback is not a constant S - 18 degrees as one would expect, nor is it S+18 degrees, nor S+36 degrees or S-36 degrees, nor S - 72 degrees or S + 72 degrees. This means the array does not work in fundamental mode as purported. Nor do any of the other array configurations described in either of these patents.
  • Fig.7 SPICE simulation of the array in Fig. 4 of US 5,475,344 (Fig. 3 herein), using library inverters (TSMC 0.18um CMOS 6 Layer Metal Process, CLKINVX8 inverters), is shown.
  • the array in Fig. 4 operates as a single ring oscillator with a period of 20 inverter delay. That is, it does not have any benefit at all over a single ring oscillator and operates in the same manner as the prior art but more slowly.
  • Fig. 10 herein which is an interpretation of the array oscillator of Fig.7 from US 5,475,344, the phase shift of every wire is marked on the drawing, as are all the feedback paths.
  • the simulation results are shown in Fig. 11.
  • the frequency of oscillation is around 2.3GHz (a period of 0.44ns).
  • the delay for a CLKI NVX8 inverter is around 120ps in a ring oscillator with loads the same as Fig. 4.
  • Fig. 10 uses feedback of N+1. N-1 is also useful. For even these improved schemes, the results are unpredictable. For these small arrays, there are two possible lengths of each ring in this range: 3 stages and 5 stages. Arrays with 2, 3, 4 and 5 rows were simulated.
  • phase resolution tabulated is normalised to one inverter delay.
  • the 2 x 5 array had the same problem as the 2 x 3 array, but the 3 x 5, 4 x 5 and 5 x 5 arrays worked, albeit in modes other than the fundamental.
  • the large phase offset between the two inputs to the inverter pair comprising each stage meant that the exact frequency varied over a wide range: from 1.36GHz to 1.72GHz.
  • ISSCC paper generally require a phase shift per stage of more than 180 degrees.
  • VCOs with negative feedback to reduce phase noise are known, such as in US 6,353,368. All VCOs use negative feedback, but in this case the biasing is arranged so as to have particular advantage with respect to phase noise.
  • Poly-phase clock VCOs are known, where phases are selected by a phase selector, such as in US 6,621 ,313, but again the maximum frequency is limited.
  • phase selector such as in US 6,621 ,3113
  • interlinked PLLs such as in US 6,657,466.
  • Object of the present invention It is therefore a primary object of the present invention to provide a polyphase clock generator which can operate at very high speed.
  • a particular form of the invention is suitable for use in the receivers of communication systems in Rapid IO ® , PCI Express, Infiniband ® , 10GbE, 10GFC, OC192, OC768 and other high speed communications standards.
  • each buffer stage comprises a set of load elements wherein at least one load element is formed of N-type MOSFET transistors; the load elements being connected to control voltages for controlling the amplitude of output signals, and connected through switch transistors to current source transistors controlled by current source biases for controlling the frequency of output signals.
  • an array oscillator which generates up to m * n phases from m interconnected ring oscillators of n stages each, the array oscillator comprising a plurality of ring oscillators, wherein each ring oscillator is as described above.
  • two sets of voltages including load control voltages and bias control voltages, are generated by the use of replica bias circuitry so that the load control voltages depend on bias voltages and are derived from these voltages.
  • Each set of voltages includes a static and dynamic voltages.
  • the array oscillator according to the invention comprises at least two, or any even number of ring oscillators, each ring oscillator having at least 2 stages, including one inverting and one non-inverting stage.
  • the array oscillator comprises 4 ring oscillators, each having one inverting stage and three non-inverting stages. Still one more example implementation of the array oscillator further comprises a supplemental circuit built of isolation buffers, for providing additional technical effect consisting in that the circuit prevents from affecting the array oscillator by a noise generated by external load devices connected to the array oscillator.
  • all stages of the array oscillator are formed from identical differential inverters.
  • non-inverting stage are formed by swapping two inverting inputs to the stage.
  • the stages are coupled to other ring oscillators in the array such that the phase shift through each stage is the same throughout the array, with all the feedback paths being of the same type except for one path which shall be of the opposite polarity to the others.
  • each stage is a buffer, inverter or gate, arranged in series such that each row has a phase shift which is 180 degrees or a multiple thereof from the longest feedback path within the row, normally the input to the row to the output of the row, and the gain from that input to output is more than 1.
  • the number of ring oscillators (n) is at least 2, and each ring oscillator has at least 2 stages.
  • inventive concept of the present invention is based on a combination of some basic features which can be varied to a certain extent to obtain various modifications of the invention within the scope of the appended claims.
  • This combination of features according to the present invention which provides the technical effect, i.e. results in achievement of a high speed array oscillator for use in communication systems, can be formulated as follows.
  • N-type MOSFET transistors are used as load elements for buffer stages.
  • the structure of these load elements, the number of transistors, their interconnection can be varied to result in many modifications and alterations of this feature as described in detail with reference to the following specification accompanied with figures.
  • the load elements can be as described in US application "Pull up for high speed structures" filed 26.05.04, or as described further with reference to Figs. 12, 13, 14, 15, as well as various modifications thereof as defined by the appended claims.
  • N-type MOSFET's requires generating a pair of control voltages, one for controlling the amplitude of output signals and another for controlling the frequency of output signals. Again, it is essential that the two voltages are interconnected so that the load voltages depend on bias control voltages and are derived from them. This feature is interconnected with the choice of the load elements, say, to control a load element formed of one N-type MOSFET transistor, a pair of control voltages as described above is sufficient; while, to control a load element formed of two transistors each, two pair of control voltages, including load static voltage VT, load dynamic voltage VT1 and bias static voltage VJ, bias dynamic voltage VJ1 , are required.
  • a current source shall be provided to enable the operation of the buffer stage. Again, one current source is sufficient for the operation of a buffer stage having load elements each formed of a single transistor, while two current sources are required for more complex loads elements having two transistors, and many variations of those.
  • replica bias circuits providing the above control voltages.
  • a prior art replica bias circuit can be used, though a modifications of replica bias circuits as described in the present invention are preferable. Again, these modifications would vary depending on the choice and structure of load elements, as will be described in detail below.
  • Still another essential feature of the invention is a pair of switch transistors. While one pair of switch transistors is enough to enable the operation of a buffer stage functioning in a ring oscillator, to built up an array oscillator, the buffer stage is needed which has two pairs of switch transistors.
  • a differential buffer stage see Fig.
  • the differential buffer stage for receiving differential signals at input signal ports (IN_P, IN_N) and providing complementary buffer stage outputs at output ports (O P, O_N), comprises:
  • each load element including at least one N-type MOSFET transistor (51, 52) for converting current into voltage; - a static current source (50) to which is applied a static current source bias
  • the buffer stage is controlled by two voltages, including load control voltage VT and bias control voltages VJ, where VT depends on VJ and is derived from this voltage by the use of a replica bias circuitry.
  • a replica bias circuitry for providing control voltages for the above buffer stage comprises (see Fig.18):
  • a transistor (107) having its gate connected to a supply voltage (VDD) and source connected to the output of the amplifier (106), for preventing overvoltages of the load transistor; and - a resistor (108) connected in series between an input voltage VIN and the gates of the load transistor (102);
  • VJ control voltage
  • VT load voltage
  • a differential buffer stage for the above array oscillator is configured (see Fig.12) to receive differential signals at input signal ports (IN_P1 , IN_N1) and input coupling ports (IN_P0, IN_N0) and to provide complementary buffer stage outputs at output ports (O_P, O_N) comprises:
  • first (21 , 22) and second (26, 27) load elements connected respectively to first, static, and second, dynamic, load voltages (VT, VT1) for controlling the amplitude of output signals (O_P, O_N), at least one load element including a set of N-type MOSFET transistors (21 , 22 and 26, 27), for converting current into voltage;
  • transistors (26,27) are connected in parallel with the drains of transistors (21 ,22), for dynamic modulation of the load of the differential stage;
  • VJ and VJ 1 a static current source (20) and a dynamic current source (29) to which are applied, respectively, a static and dynamic current source biases (VJ and VJ 1),
  • the buffer stage is controlled by two sets of voltages, including load control voltages VT 1 VTI and bias control voltages VJ, VJ1 , where VT(VTI) depends on VJ(VJI) and is derived from these voltages by the use of a replica bias circuitry.
  • the above differential buffer stage further comprises a low pass filter for load control voltages (VT and VT1), wherein the low pass filter can be formed by transistors or resistors.
  • current sources are formed by NMOS transistors.
  • the transistors connected to the same control voltage are equally sized to yield symmetrical current-voltage characteristics.
  • the replica bias circuitry for providing control voltages to the above buffer stage according to the invention includes two replicas for providing, respectively, amplitude control voltages VT, VT1 , for controlling an amplitude of the output signal and frequency control voltages VJ, VJ1 , for controlling the frequency of the output signal, each said replica circuit comprising:
  • an operational amplifier (86, 86') having one input connected to a reference voltage and another input connected to the source of the load transistor (82, 82');
  • bias control voltage (VJ, VJ 1) is supplied to the transistor current source (84, 84') to provide a current flowing in the said cascade of transistors (82, 84, or 82', 84'),
  • a load voltage (VT, VT1) is coupled to the gates of the said load transistor (82, 82') and is further coupled to resistors RO, R1 ; - thereby the difference between a voltage drop in the load transistor (82, 82') and the reference voltage is amplified by the operational amplifier (86, 86') to control a load voltage (VT 1 VT1) through a feedback formed by said cascade of transistors (82,84, 82',84') and resistors R2, R3.
  • the replica bias circuitry further comprises a transistor (103) for determining the operation point of the load transistor (102).
  • a voltage controlled oscillator comprising an array oscillator according to the second aspect of the invention, wherein the array is controlled by the use of a replica bias circuitry where changes in the bias cause changes in the delay through each stage.
  • a ring oscillator VCO generates 4*4 phases from 4 interconnected ring oscillators of 4 stage each, wherein each stage is a differential buffer stage according to the present invention as described with reference to Figures 12, 13, 14 and 15.
  • a phase locked loop is provided with very low phase noise comprising a phase detector, a charge pump, low pass filter, a static and dynamic replica bias circuitries, voltage controlled oscillator (VCO) and frequency divider, wherein the VCO is as provided according the above aspect of the invention.
  • VCO voltage controlled oscillator
  • the advantages of the present invention over the prior art is that it provides a high speed, predictable and stable oscillator with phase resolution of less than one stage delay.
  • Fig. 1 shows a ring oscillator with the maximum phase resolution being the delay through one stage, Fig.2 from US 5,475,344 and 5,717,362 (PRIOR ART);
  • Fig 2. is a 2 x 5 array oscillator of Fig. 4 from US 5,717,362 and 5,475,344
  • FIG. 3 Simulation of 2 x 5 array from Fig. 2 (Fig.4 of US 5,475,344);
  • Fig 4 shows inverter stage from US 5,475,344 (PRIOR ART);
  • Fig 5 shows 4 x 5 array configuration from Fig. 7 of US 5,717,362 and 5,475,344 (PRIOR ART);
  • Fig 6 SPICE simulation result of 4 x 5 array oscillator of Fig 5 (Fig.7 of US 5,717,362) with each inverter implemented using TSMC 0.18um CMOS library devices for 8 loads;
  • Fig 7 Simulation of 5 x 5 array from US 5,475,344;
  • Fig 8 Simulation of 5 x 7 array from US 5,475,344;
  • Fig 9 Array configuration interpreted from US 5,717,362 and 5,475,344;
  • Fig. 10 shows a differential buffer stage from Fig. 16 of US 5,717,362 and 5,475,344 used in array oscillators in the prior art
  • Fig. 11 shows a block diagram of an array oscillator of the present invention
  • Fig.12 is a high speed inverter stage of the present invention in its most general implementation
  • Fig. 13 and 14 shows other example implementations of a differential buffer stage used in array oscillators according to the present invention
  • Fig. 15 depicts a schematic representation of a preferred implementation of a differential buffer stage called "isolation buffer”.
  • Fig 16 shows a schematic representation of an array oscillator VCO with very low phase noise using differential buffer stages as shown in Figs. 12, 13 or 14;
  • Fig 16a shows a schematic representation of a supplemental circuit built up of buffer stages shown in Fig.15, for the array oscillator from Fig.16, which prevents noise from external load;
  • Fig 17 shows a PLL with very low phase noise with VCO as shown in Fig.15 above;
  • Fig 18 shows a replica bias circuitry of the present invention with very low phase noise, for providing control voltages for the buffer stage according to Fig. 15;
  • Fig 19 shows a replica bias circuitry of the present invention with very low phase noise, for providing control voltages for the buffer stages according to Figs. 12, 13, or 14;
  • Fig. 20 shows an example layout of an 4 x 4 array oscillator from Fig.11 according to the invention;
  • Fig. 21 shows simulation results of the array oscillator of Fig.11 according to the invention.
  • Fig. 11 is an example of an array of inter-coupled ring oscillators according to the present invention.
  • Each ring oscillator comprises an inverting stage and a series of non-inverting stages.
  • a first ring oscillator comprises inverting stage PO and a series of non-inverting stages P4, P8,
  • each stage should be assumed to be the same and formed from a differential inverter.
  • the two inverting inputs to the stage are swapped.
  • Each inversion of the signal is represented by a circle with white inside, as is the common practice for engineering drawings.
  • the suitable buffer stages are as disclosed by the inventors of the present application in earlier publication WO 03/100974 and its CIP application in US "Pull up for high speed structures", Serial No.10/853123, filed on 26.05.04 (with reference to Figs. 8 and 9 therein), the full specifications of these applications being incorporated herein by reference, or as described further in the present application with reference to Figs. 12, 13, 14, 15.
  • a differential buffer stage is shown wherein each buffer stage acts as two differential inverters/buffers in parallel.
  • a circuit in Fig.12 is a differential buffer stage comprising two pair of NMOS transistors 21 , 22 and 26, 27 for controlling the amplitude of an output signal, and a pair of transistors 23, 24 which operates as switch.
  • transistors 26, 27 are connected in parallel with drains of transistors 21 , 22.
  • Oscillation control voltage VT static is applied to transistors 21 , 22, while voltage VT1 (dynamic) is applied to transistors 26, 27.
  • the biased NMOS devices 21 , 22 and 26, 27 connected to the same control voltage, respectively, are equally sized in pairs, as required by circuitry symmetry, to yield respective symmetrical current- voltage characteristics.
  • Transistors 21 , 22 and 26, 27 provides the initial voltage level to start up such a generator.
  • Transistors 23, 24 operate as switches.
  • the buffer stage further includes two N-transistor current sources 20 (static) and 29 (dynamic) to which are applied current source biases VJ and VJ 1 , respectively.
  • a load control voltage VT is supplied to gates of transistors 21 , 22, and VT1 is supplied to sources of transistors 21 and 22 via transistors 26, 27.
  • the buffer stage is controlled by the use of two arrangements (see above VT,VT1 ,VJ 1 VJI). It is configured to receive differential signals at input signal ports
  • the operating current and output voltage in the circuit is controlled by load voltage level VT and bias control voltage VJ generated by a replica bias circuitry shown in Fig.18. This can be used, for example, to control a frequency generator, or the like.
  • the buffer operates as follows:
  • the input data is supplied to IN_PO and IN_NO. They are controlled by the voltage levels supplied to VT and VJ, as described above. As a result, a delay and amplitude of the input signal can be regulated by VT and VJ. Respectively, the use of such buffers in voltage controlled oscillators provides varying the frequency of the oscillator by changing voltage.
  • the advantage of the differential amplifier according to the invention over the prior art is that the strength of the stage during switching can be dynamically modulated by using resistors 26, 27.
  • Each one of transistors 21 , 12 itself has its gate capacitance which, in combination with transistors 26, 27, respectively, forms an equivalent RC network, which gives a delay when this time constant is close to the switching time that changes the current in the stage dynamically.
  • the strength of the stage is lower because the gate of the transistor is not charged to the final level.
  • a similar buffer stage is shown, where transistors 31, 32 and 36, 37 operate in the same way as transistors 21 , 22 and 26, 27 in Fig. 12, but with the use of additional transistors 381 , 382, 383, 384 acting as a low pass filter for load control voltage VT and VT1.
  • Additional voltages VR, VR1 control the strength of transistors 381 , 382 and 383, 384, respectively.
  • These voltages VR, VR1 serve to create a certain shift with respect to voltages VT, VT1. This shift is obtained by using a transistor, such as transistors 381 , 382 and 383, 384, as a diode transistor and supplying this transistor with a small current.
  • the embodiment shown in Fig. 13 is especially advantageous to provide circuits of reduced size, or, when resistors cannot be used due to their capacitance.
  • resistors RO, R1 , R2, R3 with their parasitic capacitance are used as a low pass filter for load control voltage VT and VT1.
  • Resistors RO, R1 are connected in series with the gates of transistors 41 , 42, while resistors R3, R2 are connected in series with the gates of transistors 46, 47.
  • resistors RO, R1 , R2, R3 dynamically modulate the strength of the respective transistors during switching.
  • the transistor itself has a gate capacitance.
  • these form an equivalent RC network, which gives a delay when this time constant is close to the switching time that changes the current in the pull-up dynamically.
  • the additional advantage of the above described circuits is that by switching inputs/outputs, it can be easily converted from buffer stages into inverters, when required.
  • Fig. 15 depicts a schematic representation of another implementation of differential buffer stage called "isolation buffer”. It is particularly suitable for use in a supplemental circuit shown in Fig.16a for a ring oscillator shown in Fig.16. It will preferably be implemented by using a circuit architecture roughly corresponding to approximately one-half of the buffer stage depicted in Fig. 12 (see also description of Fig.17 in 5,717,362).
  • the buffer of Fig. 15 is configured to receive a differential signal through an input differential stage having input transistors 53, 54. Complementary outputs are provided by the buffer at output ports O_N and O_P.
  • the buffer stage further includes an NMOS transistor current source 55 to which is applied the current source bias VJ.
  • the externally-supplied oscillation control voltage VT is applied to NMOS transistors 51 and 52.
  • circuit of Fig.15 can be used to built up a ring oscillator according to the invention, it can be further doubled to create a simplest example implementation of a differential buffer circuit suitable to built up array oscillators according to the invention.
  • a conventional replica bias circuitry can be used, e.g. as described in Fig.18 of US 5,717,362.
  • the problems with conventional replica circuitry is that the load voltage VT of a replica bias circuit shall exceed the supply voltage VDD for at least a threshold voltage of a transistor to which this voltage is applied. Otherwise, the pull up strength of the transistor significantly degrades at small voltage drops.
  • VT » VDD and in some cases, VT can be as high as 2VDD - VRef.
  • overvoltages on transistors deteriorate the transistor's parameters and cause their fast degradation.
  • a specially designed replica bias circuitry most suitable for the operation of the above buffer with NMOS transistors is provided according to the present invention.
  • Example embodiments of a replica bias circuitry according to the present invention are shown in Figs. 18 and 19.
  • a replica bias circuitry shown in Fig.18 represents in a most general form a circuitry for generating a load voltage VT based on supply voltage VDD and control voltage VJ.
  • VJ is externally supplied static bias providing oscillation control.
  • the circuitry comprises a cascade of transistors 102, 103, 104, where transistor 102 is a load transistor, transistor 103 is optional and serves for determining the operation point of the load transistor, and transistor 104 operates as a current source.
  • the operation point of a load element can be defined by a combination of two parameters ⁇ U/Iop, where lop is an operating current and ⁇ U is the full voltage drop on the element and characterises the strength of a load element, i.e. its differential impedance.
  • the replica bias circuitry of Fig.18 further comprises an operational amplifier 106 having one input connected to the reference voltage from a source 105 of a reference voltage, and another input connected to the source of transistor 102.
  • the output of the amplifier is connected to the source of transistor 107, having its gate connected to the supply voltage VDD.
  • a resistor 108 is connected in series between an input voltage VIN and the gates of the load transistor 102.
  • the replica bias circuitry operates as follows.
  • a control voltage VJ is supplied to transistor 104 to provide a current flowing in transistors 102, 103, 104.
  • the difference between a voltage drop in transistor 102 and the reference voltage is amplified by operational amplifier 106.
  • the output of the amplifier 106 through a negative feedback can be used to control the load voltage VT using a transistor 107 and resistor 108 and coupling the load voltage VT to the gate of transistor 102.
  • the current generated in transistor 107 depends on the voltage at the output of the amplifier 106 and, using resistor 108, we can adjust the load voltage VT accordingly.
  • the voltage drop on transistor 102 approximates the reference voltage.
  • Another example implementation of a replica bias circuitry with two replicas, static VT and dynamic VT1 is shown in Fig. 19.
  • the circuitry comprises two operational amplifiers (OpAmps) 86 and 86', each having a feedback loop formed of transistors 82, 83, 84 and 82', 83', 84', respectively.
  • VJ is externally supplied static bias.
  • VJ 1 and VT1 derived from it provide oscillation control.
  • VJ1 is a control voltage which provides a compliance of the VCO frequency to a required value.
  • VT 1 provides a required amplitude of the differential signal in VCO.
  • Reference current VR is supplied to OpAmps 86 and 86', so as to form VT1 via feedback loops using VT and VJ.
  • the replica bias circuitry of Fig.19 is specifically adapted to provide the required voltage levels VT and VT1 to control differential buffer stages made of MOS transistors, in particular, to generate VT which exceeds a supply voltage VDD.
  • VAA » VDD In conventional circuitries, to provide operation of pull ups, such as pull up 82, it is required that VAA » VDD. This typically causes overvoltages of transistors.
  • the above problem is solved by the replica bias circuitry shown in Figs.18a and 18b, which provide normal operation of a cascade of transistors, while no one voltage exceeds the admissible level.
  • the VAA requires small currents while the voltage can be twice as high as VDD.
  • VT is used to form an initial voltage level to start up a voltage generator, while VT1 is used for a more accurate adjustment of the thus obtained voltage level.
  • the generated VT can be also used to provide a required amplitude of a differential signal in VCO.
  • Reference current VIN is supplied to OpAmps 86, 86', so as to form VT1 via feedback loops using VT and VJ.
  • the key point of the present invention is that all the stages can be the same, or can be any combination of inverters and buffers, subject to each ring having a 180 degrees phase shift or even multiple thereof
  • each ring oscillator comprises 4 stages. Therefore, the phase difference between the input and output of each stage is 45 degrees (180 degrees divided by 4).
  • the C input can be assumed to be the same as the S input: that is, each stage acts like two differential inverters/buffers in parallel. This means the phase of the output of each stage will be the mean of the two inputs plus 45 degrees. There are many possible implementations of such a twin input stage.
  • Fig.16 is a schematic representation of a ring oscillator VCO, which depicts the exemplary array oscillator according to the invention.
  • the array oscillator generates 4 * 4 phases from 4 interconnected ring oscillators of 4 stage each.
  • Each stage is a differential buffer stage, such as described with reference to Figures 12, 13 or 14.
  • the output frequency of each ring of the array is nominally 1/2D, where D is the delay through one ring.
  • a ring oscillator to achieve the required frequency is first designed.
  • the preferred manner for this design is the use of one inverter stage followed by sufficient buffers to create the delay required.
  • the number of phases generated by the array is m rows x n stages per row, so once the ring is defined, the number of rings can be determined by dividing the number of phases required by the number of stages in each ring. In case a fractional number of rings is obtained, it shall be made round.
  • the feedback should preferably be from N+1 or N-1 , as this minimises power consumption, but any other phase can be selected, such that the input to each stage has the same phase relationship.
  • the phases of the two S and C inputs to each stage must overlap at least partially: that is they must be less than 180 degrees of each other (or 180/n where n is an even number). To achieve this requirement of the same phase relationship for each stage, it is necessary to invert one of the feedback signals: for example if 180+9 degrees is generated, to obtain 9 degrees it is necessary to invert the signal such as by swapping the two lines of a differential input.
  • a voltage controlled oscillator comprises an array oscillator controlled by the use of a bias arrangement where changes in the bias cause changes in the delay through each stage.
  • the array is preferably controlled by the use of two arrangements: VT,VT1 - load control voltage and VJ, VJ1 - bias control voltage.
  • VT(VTI) depends on VJ(VJI) and is derived (formed) from these voltages by the use of a replica bias circuitry as shown further in Fig. 19.
  • VJ is an externally supplied static (i.e., constant) current source bias which serves (together with VT): (i) to avoiding suppression of oscillation during the startup; and (ii) to narrowing oscillation control range and, thereby, providing smoother and faster regulation of oscillation.
  • VJ 1 is a dynamic current source bias; in other words, the changes in the bias (also in VT1) cause changes in the delay through each stage of the array oscillator.
  • the rings of the oscillators of the type shown in Fig. 11 and those described by the present invention (see the interconnections of this array oscillator in Fig.19), oscillate in a stable manner and generally do not require any initialisation, as they revert to fundamental mode automatically. Simulation results of the array oscillator shown in Fig.11 are presented in Fig.21. If initialisation is required, the rings can be made open by substituting a logic function such as an NOR gate for one or more stages in each ring and applying a reset signal to the extra input of the NOR. Other gates such as NAND 1 XOR can perform a similar function.
  • variable bias stages it is possible to use the present invention as a VCO by the use of variable bias stages, by the use of varicap diodes, or other delay modification mechanism.
  • the use of variable bias stages is preferred because a common biasing scheme will cause all stages to vary by the same amount.
  • a further improvement of the array oscillation shown in Fig.16 can be obtained by using a supplemental circuit shown in Fig.16a, which uses buffer stages shown in Fig.15, which prevents from affecting the array oscillator by the noise generated by external load devices connected to the array oscillator.
  • Fig. 17 shows a PLL with very low phase noise with VCO as described with reference to Fig.16 above.
  • RS and RD represents static and dynamic replica bias circuitry, respectively.
  • the phase lock loop comprises a phase detector 71 , a charge pump 72, low pass filter 73, a static and dynamic replica bias circuitries RS, RD, voltage controlled oscillator 76 and frequency divider 77.
  • the VCO shown in Fig.16 can be used in a phase locked loop (PLL) as shown in Fig. 17, whereby the frequency of the VCO 76 is set by the variable divider 77.
  • the output of the divider 77 is compared with a reference clock such as from a crystal oscillator, and this phase comparator 71 drives a charge pump 72, which in turn drives the bias control of the VCO 76.
  • the array oscillator VCO 76 will then generate multiple phases at a frequency set by the reference clock times the reciprocal of the divider 77.
  • PLL theory for implementing and analysing such structures is well known.
  • Figures 12 to 15 show differential buffer circuitry for some main elements of PLL.

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Abstract

D'une manière générale, la présente invention a trait à des circuits d'oscillateurs à réseau destinés à être utilisés sous la forme de générateurs de temps de propagation de phase. Plus particulièrement, la présente invention a trait à un nouvel oscillateur à réseau permettant de fournir une pluralité de phases qui présentent des relations de phase stables. La présente invention est particulièrement applicable à la génération d'horloges polyphasées pour des récepteurs à interfaces à grande vitesse qui utilisent une technique de suréchantillonnage, ou le multiplexage, et pour une logique à grande vitesse. L'oscillateur à réseau selon l'invention comporte au moins un oscillateur en anneau comprenant une pluralité d'au moins deux étages séparateurs interconnectés comprenant au moins un, ou un nombre entier impair quelconque d'étages d'inversion et une série d'étages de non inversion, dans lequel les étages séparateurs sont constitués de transistors MOS à effet de champ de type N.
PCT/IB2004/002410 2004-07-15 2004-07-15 Oscillateur a reseau et generateur d'horloge polyphasee Ceased WO2006010991A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003100974A2 (fr) * 2002-05-28 2003-12-04 Igor Anatolievich Abrosimov Excursion haute pour structures haute vitesse
WO2003100973A2 (fr) * 2002-05-28 2003-12-04 Igor Anatolievich Abrosimov Generateur de tension de reference pour elements logiques assurant un temps de propagation stable et predefini

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003100974A2 (fr) * 2002-05-28 2003-12-04 Igor Anatolievich Abrosimov Excursion haute pour structures haute vitesse
WO2003100973A2 (fr) * 2002-05-28 2003-12-04 Igor Anatolievich Abrosimov Generateur de tension de reference pour elements logiques assurant un temps de propagation stable et predefini

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