WO2006006424A1 - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

There is provided a FinFET having a low threshold value voltage formed at the upper corner of a semiconductor layer and suppressing a leak current attributed to a parasitic transistor. A manufacturing method of the FinFET is also provided. The field effect transistor includes a semiconductor region, a gate insulation film, a cap insulation film, a gate insulation film, a gate electrode arranged on the cap insulation film, and a source/drain region. A channel region is formed on the side surface of the semiconductor region. The field effect transistor is characterized in that at least a part of the side surface of the cap insulation film covered by the gate electrode in the side surface extension direction of the semiconductor region has a side surface-resistant etching region having an etching rate lower than SiO2 with respect to the wet etching using the HF solution.

Description

 Specification

 Field effect transistor and manufacturing method thereof

 Technical field

 The present invention relates to a fin-type field effect transistor in which electric field concentration from a gate electrode in an upper part of a semiconductor layer is reduced and leakage current is suppressed.

 Background art

 Conventionally, as disclosed in JP-A-64-8670 and JP-A-2002-118255, a double-gate fin-type field effect transistor (hereinafter referred to as a double-gate FinFET) Has been developed. The ideal form of a double-gate FinFET will be described using the plan view of FIG. 21 and the cross-sectional view of FIG. Figure 22 (a) is the A-A 'section in Figure 21, Figure 22 (b) is the BB section in Figure 21, 1 is the semiconductor substrate, 2 is the buried insulating layer, 3 is the semiconductor layer, 4 is the gate An insulating film, 5 is a gate electrode, 6 is a source / drain region, and 22 is a cap insulating film made of SiO. Wfin is the fin width and Hfin is the fin height. Fig 23

2

 The cap insulating film is composed of a first cap insulating film 8 made of SiO and a second cap insulating film 8 made of Si N.

 2 3 4

 This is the case of the two-layer structure of the cap insulating film 9. Fig. 23 (a) is an AA 'cross section in Fig. 21, and Fig. 23 (b) is a BB' cross section in Fig. 21.

 [0003] By applying an appropriate voltage to the gate electrode, a channel region is formed in a portion facing the gate electrode 5 on the side surface of the semiconductor layer 3, and current flows in the transistor.

 [0004] When a cap insulating film (8, 9, 22) is provided on the semiconductor layer 3, the capacitance between the gate electrode and the upper portion of the semiconductor is reduced, so that the electric field concentration on the upper corner 23 of the semiconductor layer is reduced. It is done. When the electric field concentration on the upper corner 23 of the semiconductor layer is relaxed, leakage current due to GIDL (gate-in-drain drain leakage) and parasitic current with a low threshold at the upper corner of the semiconductor layer are suppressed, and transistor performance is reduced. Will improve. Disclosure of the invention

 [0005] A problem of the conventional example will be described with reference to FIGS. Each drawing in Fig. 24 shows A in Fig. 22 (a).

 The position of the A ′ cross section, each drawing in FIG. 25 corresponds to the position of the A—A ′ cross section in FIG.

In order to form the transistor of FIG. 22, a cap insulating film 22 made of SiO and a semiconductor layer 3 are formed. Processed by etching into the form shown in Fig. 24 (a). After this step, prior to the step of forming the gate insulating film on the side surface of the semiconductor layer (semiconductor region), the side surface of the semiconductor layer is usually once oxidized (sacrificial oxidation) as a pretreatment of the gate insulating film forming step. The formed oxide film (sacrificial oxide film) is removed by wet etching using hydrofluoric acid or the like. The purpose of this is to form a high-quality gate insulating film by removing the interfacial force of the semiconductor layer forming the gate insulating film from the contaminated layer and the damaged layer. However, this wet etching also etches the cap insulating film at the same time, so that the cap insulating film 22 recedes as shown in FIG. 24 (b), and the upper corner of the semiconductor layer is exposed, or FIG. ), The cap insulating film 22 disappears completely, and the upper corner of the semiconductor layer is exposed. If the gate insulating film and gate electrode are formed with the upper corner of the semiconductor layer not covered with the cap insulating film and exposed, electric field concentration occurs at the upper corner of the semiconductor layer, causing leakage current due to GIDL and parasitic transistors To do.

In the case of the transistor of FIG. 23 as well, wet etching using hydrofluoric acid or the like as a sacrificial oxide film is performed as a pretreatment in the gate insulating film forming process after being processed into the form of FIG. The first cap insulating film 8 made of SiO recedes as shown in FIG.

 2

 As a result, the upper corner of the semiconductor layer is exposed or the first cap insulating film 8 is completely disappeared and the cap insulating film 9 is lifted off and dropped off as shown in FIG. Similar problems occur when corners are exposed.

 Accordingly, a structure and manufacturing method in which the upper corner of the semiconductor layer is covered with the cap insulating film even after the pretreatment of the gate insulating film forming step is desired.

 [0009] According to the present invention, the following field-effect transistor and a method for manufacturing the same can be provided.

 [0010] (1) A semiconductor region protruding upward with respect to a substrate plane, a cap insulating film provided on an upper surface of the semiconductor region, and the cap insulating film so as to straddle the semiconductor region and the cap insulating film An upper force of the gate electrode extending laterally of the semiconductor region, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region,

A source z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. A field effect transistor,

 Of the cap insulating film covered with the gate electrode, at least a part of the side surface in the direction of extension of the side surface of the semiconductor region that is in contact with the semiconductor region is subjected to wet etching using HF solution by SiO. The etching rate is low and the side etching resistant region is

 2

 A field effect transistor characterized by having.

 [0011] (2) The side surface etching resistant regions are provided to be opposed to each other on two side surfaces covered with the gate electrode of the cap insulating film, and the opposite side surface etching resistance in the cap insulating film is provided. 2. The field effect transistor according to 1 above, wherein a central region made of a material different from the side etching resistant region is provided at a position sandwiched between the regions.

 [0012] (3) The field effect transistor according to (2) above, wherein the central region is made of a material having a dielectric constant lower than that of the side etching resistant region.

 [0013] (4) The field effect type of the above-mentioned 2 or 3, wherein the central region also has SiO force.

 2

 Transistor.

 (5) The side etching resistant region is provided over the entire length of the side surface of the cap insulating film covered with the gate electrode in the direction connecting the opposing source Z drain regions. The field effect transistor according to any one of 1 to 4 above.

 [0015] (6) The above-mentioned side surface etching resistance region force Si N force

 3 4

 One of these field effect transistors.

(7) The side etching resistant region is made of a material containing silicon, nitrogen, and oxygen.

1 to 5 field effect transistor.

[0017] (8) The cap insulating film has an upper surface including an upper surface etching-resistant region having an etching rate lower than that of SiO with respect to wet etching using an HF solution at least partially.

 2

 The field effect transistor according to any one of 1 to 7 above, wherein

[0018] (9) The field effect transistor as described in 9 above, wherein the upper surface anti-etching region constitutes at least a part of an upper surface of the cap insulating film covered with the gate electrode.

(10) The upper surface etching resistant region is provided over the entire length of the upper surface of the cap insulating film covered with the gate electrode in the direction connecting the opposing source Z drain regions. 8. The field effect transistor as described in 8 above, wherein

[0020] (11) The upper surface etching resistant region force Si N force is also provided.

 3 4

 Any field effect transistor.

[0021] (12) The field effect transistor according to any one of 8 to 10, wherein the upper surface etching resistant region is made of a material containing silicon, nitrogen, and oxygen.

[0022] (13) The field effect transistor according to any one of 1 to 12, wherein the cap insulating film has a substantially rectangular parallelepiped shape.

[0023] (14) The field effect transistor as described in 7 or 12 above, wherein the nitrogen content in the material containing silicon, nitrogen and oxygen is 5 atomic% or more.

(15) Cap insulating film force For wet etching using HF solution, SiO

 2. The field effect transistor according to 1 above, wherein 2 has a material force with a low etching rate.

 [0025] (16) The electric field of item 15, wherein the cap insulating film has an overall force Si N force.

 3 4

 Effect transistor.

 (17) A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and the cap insulation so as to straddle the semiconductor region and the cap insulating film A gate electrode extending from the top of the film to the side of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;

 The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And

 The cap insulating film includes a SiO region provided on the semiconductor region,

 2

 Si N regions provided on the upper surface and both side surfaces of the SiO region;

 2 3 4

 A field-effect transistor characterized in that it also has power.

(18) A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on an upper surface of the semiconductor region, and the cap insulation so as to straddle the semiconductor region and the cap insulating film A gate electrode extending from the top of the film to the side of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region; The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And

 The cap insulating film includes a SiO region provided on the semiconductor region,

 2

 Contains silicon, oxygen and 5 atomic% or more of nitrogen provided on both sides of the SiO region.

2

 Having a SiON region;

 Si N region provided on the upper surface of the SiO region and SiON region;

 2 3 4

 A field-effect transistor characterized in that it also has power.

(19) A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on an upper surface of the semiconductor region, and the cap insulation so as to straddle the semiconductor region and the cap insulating film A gate electrode extending from the top of the film to the side of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;

 The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And

 The cap insulating film includes a SiO region provided on the semiconductor region,

 2

 The silicon, oxygen, and 5 atomic% or more provided on the upper surface and both side surfaces of the SiO region

2

 A SiON region containing nitrogen;

 A field-effect transistor characterized in that it also has power.

(20) A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and the cap insulation so as to straddle the semiconductor region and the cap insulating film A gate electrode extending from the top of the film to the side of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;

 The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And

 The cap insulating film includes a SiO region provided on the semiconductor region,

 2

Si provided on both side surfaces of the SiO region and projecting upward from the side surface of the SiO region N region,

 Four

 A field-effect transistor characterized in that it also has power.

[0030] (21) In the field effect transistor, the plurality of semiconductor regions are arranged so that directions of channel currents flowing in the semiconductor regions are parallel to each other. 1 to 20 field effect transistor.

(22) A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,

 A plating process for forming a patterned first insulating film on the semiconductor layer, and an insulating film side wall made of a second insulating film in contact with the side surface of the first insulating film, Providing the semiconductor layer exposed in the etching step for forming the insulating film at a position near the patterned first insulating film, the first insulating film, and the second insulating film; The semiconductor layer is formed using the insulating film side wall made of the insulating film as a mask.

 Etching to form a semiconductor region protruding upward with respect to the substrate plane;

 A method for producing a field-effect transistor, comprising:

(23) forming a sacrificial oxide film on a side surface of the semiconductor region protruding upward with respect to the substrate plane;

 And a step of removing the sacrificial oxide film by wet etching, wherein the side wall of the semiconductor region is formed on the side surface of the semiconductor region with respect to the wet etching. 24. The method for producing a field effect transistor according to 23, wherein the material is made of a material having a lower etching rate.

(24) A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,

(a) a sacrificial acid formed on the side surface of the semiconductor region with respect to wet etching at a portion having a pair of side surfaces perpendicular to the semiconductor layer and facing each other on the semiconductor layer, and in contact with the semiconductor layer on the pair of side surfaces A step of providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film; (b) using the cap insulating film as a mask and forming a semiconductor region protruding above the base force under the cap insulating film;

 A method for producing a field-effect transistor, comprising:

 [0034] (25) After the step (b),

 (c) forming a sacrificial oxide film on the side surface of the semiconductor region;

 (d) removing the sacrificial oxide film by wet etching;

 24. The method for producing a field effect transistor according to 24, further comprising:

(26) forming a gate insulating film on the side surface of the semiconductor region from which the sacrificial oxide film is removed;

 Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;

 Introducing a impurity on both sides of the semiconductor region sandwiching the gate electrode to form a source Z drain region;

 The method for producing a field effect transistor according to 23 or 25, further comprising:

(27) The step of (a) providing a cap insulating film includes:

 Providing a central region on the semiconductor layer;

 Providing a side etching resistant region on a side surface of the central region by depositing a side etching resistant region material on the semiconductor layer and the central region and then performing an etch knock;

 A process for producing a field effect transistor according to any one of the above 24 to 26, characterized by comprising:

 (28) The step of (a) providing a cap insulating film includes:

After depositing a central region material on the semiconductor layer and depositing a top surface resistant region material on the central region material, patterning the central region material and the top surface resistant region material and performing wet etching on the central region. Forming a top surface etching resistant region having a lower etching rate than the sacrificial oxide film formed on the side surface of the semiconductor region, and providing a side surface etching resistant region on the side surface of the central region and the top surface etching resistant region. Process,

 A process for producing a field effect transistor according to any one of the above 24 to 26, characterized by comprising:

 [29] (29) The step of providing the side face etching resistant region includes:

 28. The method of manufacturing a field effect transistor as described in 28 above, which is a step of performing etch back after depositing a side face etching resistant region material on the entire surface.

[0039] (30) The deposition of the side surface etching resistant region material and the upper surface etching resistant region material is performed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The method for producing a field effect transistor according to any one of the above 27 to 29.

 [0040] (31) The step of (a) providing a cap insulating film includes:

 A step of providing a substantially rectangular parallelepiped cap insulating film material on the semiconductor layer, and a condition that the nitriding rate of the cap insulating film material is higher than the nitriding rate of the semiconductor layer, and the side surface and the upper surface of the cap insulating film material and the semiconductor Performing a nitridation process on the layer, performing etch back, the side surface on which the cap insulating film material has been subjected to the nitriding process on the side surface, and a top surface on which the nitriding process on the cap insulating film material has been performed on the top surface. A process of making a region,

 A process for producing a field effect transistor according to any one of the above 24 to 26, characterized by comprising:

 (32) (a) the step of providing a cap insulating film,

 A step of providing a substantially rectangular parallelepiped cap insulating film material on the semiconductor layer, and an upper surface anti-etching region on the cap insulating film material;

 Nitriding the side surfaces of the cap insulating film material and the semiconductor layer, performing etch back, and setting the side surfaces of the cap insulating film material subjected to the nitriding treatment to side etching resistant regions;

 A process for producing a field effect transistor according to any one of the above 24 to 26, characterized by comprising:

(33) The nitriding treatment is radical nitriding, thermal nitriding, or nitrogen ion implantation. 31. A method for producing the field effect transistor according to 31 or 32 above.

(34) The method further comprising the step of removing the cap insulating film provided on the semiconductor region that is not covered with the gate electrode among the cap insulating film.

A method for producing a field effect transistor according to any one of -33.

[0044] (35) (a) Process power for providing a cap insulating film A material layer having a lower etching rate than a sacrificial oxide film provided on a side surface of the semiconductor region for wet etching on a semiconductor layer. 26. The method of manufacturing a field effect transistor according to any one of 24 to 26, wherein the step of patterning is performed after depositing a cap insulating film material.

[0045] (36) The field effect transistor according to any one of 24 to 35, wherein the wet etching is wet etching using an HF solution, and the sacrificial oxide film also has SiO force.

 2

 The manufacturing method of the star.

 [0046] In the transistor having the structure of the present invention, a region in which the upper corner of the semiconductor layer is covered with the cap sidewall insulating film is provided in at least a partial region of the upper portion of the semiconductor layer. Since at least a part of the gate electrode is not covered so as to surround the upper corner of the semiconductor layer through the gate insulating film, parasitic transistors are suppressed and leakage current is suppressed.

 [0047] In addition, a region in which the upper corner of the semiconductor layer is covered with the cap side wall insulating film is provided in at least a partial region of the upper portion of the semiconductor layer near the end of the source Z drain region. Since it is not covered so as to surround the upper corner of the semiconductor layer via the gate insulating film, electric field concentration is suppressed and leakage current due to GIDL is suppressed.

In the present invention, since the corner portion of the upper surface of the semiconductor layer is covered with the first cap insulating film and the cap side wall insulating film, the sacrifice formed on the side surface of the semiconductor region prior to the formation of the gate insulating film. When the pretreatment for removing the oxide film is performed, the corner portion of the upper surface of the semiconductor layer where the first cap insulating film is not etched by the pretreatment for forming the gate insulating film is not exposed. For this reason, the electric field concentration from the gate electrode in the upper part of the semiconductor layer (semiconductor region) is relaxed, the leakage current due to GIDL is reduced, and the leakage current due to a parasitic transistor with a low threshold voltage formed at the upper corner of the semiconductor layer. Is suppressed. [0049] Insulating material resistant to sacrificial oxide film etching process (typically Si N, Si

 3 4

Many materials containing nitrogen, such as ON, have a dielectric constant higher than that of SiO.

 2

 Of the insulating film, it is necessary to have resistance against the etching process of the sacrificial oxide film. At least a part of the portion is more dielectric constant than the material resistant to the etching process of the sacrificial oxide film. By using a material having a low thickness, the electric field concentration from the gate electrode on the upper part of the semiconductor layer can be reduced.

 [0050] Typically, in the present invention, the dielectric constant is lower than that of the second cap insulating film (upper surface anti-etching region), and when the first cap insulating film (center region) is formed of a material, the entire cap insulating film is formed. Compared to the case where the first cap insulating film, the second cap insulating film, and the cap sidewall insulating film (side etching region) are made of SiN, which is resistant to hydrofluoric acid.

 3 4

 The capacitance between the upper part and the gate electrode is reduced, and the electric field concentration on the upper part of the semiconductor layer can be reduced. As a result, leakage current called GIDL (Gate Induced Drain Leakage) is reduced and leakage current due to a parasitic transistor having a low threshold voltage formed at the upper corner of the semiconductor layer is also suppressed.

[0051] In the present invention, the side wall of the cap insulating film material that has been preliminarily formed is subjected to nitriding treatment, whereby the cap side wall insulating film is formed on the outer side surface of the cap insulating film. Since the cap sidewall insulating film is formed on the inner side of the side surface of the previously formed cap insulating film material, it is not necessary to deposit the cap, so that the entire width of the cap insulating film is suppressed, and as a result, the cap insulating film is masked. Thus, the width of the Fin layer (fin width Wfin) formed by etching the semiconductor layer can be reduced. By reducing the fin width Wfin of the FinFET, the short channel effect is suppressed and the performance can be improved. Also, the nitridation process is a nitride film (or SiO film) that is formed compared to the CVD process.

 2 Field-effect transistors can be manufactured with excellent processing accuracy because of excellent controllability of the thickness of the region into which nitrogen is introduced.

 Brief Description of Drawings

FIG. 1 is a cross-sectional view illustrating a first embodiment

 FIG. 2 is a sectional view for explaining the first embodiment.

FIG. 3 is a sectional view for explaining the first embodiment. FIG. 4 is a sectional view for explaining the first embodiment.

 FIG. 5 is a sectional view for explaining the first embodiment.

 FIG. 6 is a sectional view for explaining the first embodiment.

 FIG. 7 is a sectional view for explaining the first embodiment.

 FIG. 8 is a plan view for explaining the first embodiment.

 FIG. 9 is a cross-sectional view illustrating a second embodiment

 FIG. 10 is a cross-sectional view illustrating a second embodiment

 FIG. 11 is a cross-sectional view illustrating a second embodiment

 FIG. 12 is a cross-sectional view illustrating a second embodiment

 FIG. 13 is a cross-sectional view illustrating a second embodiment

[14] Plan view for explaining a preferred embodiment of the present invention

FIG. 15 is a cross-sectional view illustrating a third embodiment

 FIG. 16 is a cross-sectional view illustrating a third embodiment

 FIG. 17 is a sectional view for explaining a fourth embodiment.

 FIG. 18 is a sectional view for explaining the fourth embodiment.

 [FIG. 19] Explanatory diagram of problems in the prior art 圆 20] Drawing explaining the effect of the invention

圆 21] Plan view explaining conventional technology

[22] Cross-sectional view explaining conventional technology

圆 23] Cross-sectional view explaining conventional technology

圆 24] Explanatory diagram of problems in conventional technology

 [Fig.25] Explanatory diagram of problems in conventional technology

 FIG. 26 is a sectional view for explaining a preferred embodiment of the present invention.

FIG. 27 is a sectional view for explaining a preferred embodiment of the present invention.

FIG. 28 is a plan view for explaining a preferred embodiment of the present invention.

FIG. 29 is a cross-sectional view illustrating a preferred embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

(First embodiment) On the SOI substrate (FIG. 1 (a)) on which the buried insulating layer 2 and the semiconductor layer 3 are formed on the semiconductor substrate 1, the first cap insulating film material (intermediate region material) 8, the second cap insulating film material (upper surface) (Etching-resistant region material) 9 is deposited (Fig. 1 (b)).

[0054] The semiconductor substrate 1 is usually a silicon substrate. The buried insulating layer 2 is typically made of SiO.

 2 and its thickness is typically 50 nm to 400 nm. The semiconductor layer 3 is typically silicon and its thickness is typically 20 nm to 200 nm. The material of the first cap insulating film 8 is typically SiO, and the material of the second cap insulating film 9 is typically Si.

 twenty three

N, which are deposited, for example, by CVD. First cap insulation film 8, second carrier

Four

 The thickness of each of the insulating films 9 is typically 10 nm to 50 nm.

[0055] FIGS. 2 to 6 (c) are top views of fin-type field effect transistors, respectively, (a) is a cross-sectional view of the fin-type field effect transistor in the AA ′ direction, and (b) is a cross-sectional view. B—A cross-sectional view in the B ′ direction.

 [0056] The first cap insulating film material 8 and the second cap insulating film material 9 are formed so as to cover the region where the element region is formed by forming a resist pattern by normal photolithography and etching using the resist as a mask. Process it (Figure 2). The first cap insulating film material 8 may be etched using the resist as a mask, or after removing the resist, the second cap insulating film 9 may be etched using the mask.

 [0057] A cap cover insulating film material (side face etching resistant region material) 10 is deposited on the entire surface (Fig. 3). Cap cover insulating film material 10 has resistance to pre-processing of gate insulating film formation (etching rate is lower than SiO for wet etching with hydrofluoric acid solution)

 2

 Made of material. The cap cover insulating film 10 is typically a SiN film deposited by a film forming technique such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The thickness of the cap cover insulating film 10 is typically 2 nm to 20 nm.

3 4

 Yes, usually in the range of 3nm to 10nm.

The cap cover insulating film 10 is etched back by an etching process such as RIE, and the cap cover insulating film is formed on the side walls of the first cap insulating film (center region) 8 and the second cap insulating film (upper etching resistant region) 9. A cap side wall insulating film (side etching region) 19 made of 10 is formed (Fig. 4). Using the second cap insulating film 9 and the cap sidewall insulating film 19 as a mask, the semiconductor layer 3 is patterned by an etching process such as RIE (FIG. 5).

[0060] Similar to the normal MOSFET formation process, the gate insulating film 4 is formed, the gate electrode material is deposited and patterned, and the gate electrode 5 is formed. Using the gate electrode as a mask, high-concentration impurities (n-channel) N-type dopants such as As and Sb in the case of transistors, p-type dopants such as B and In in the case of p-channel transistors, usually introduced so that the impurity concentration is 1 X 10 ¹⁹ cm _ ³ or more) Introduced by implantation, the source Z drain region 6 is formed, and the transistor is completed (Figure 6).

 At this time, prior to the formation of the gate insulating film, the side surface of the silicon layer (semiconductor region) exposed by etching is once thermally oxidized to form a sacrificial oxide film, and the sacrificial oxide film is diluted with dilute hydrofluoric acid. Even when the step of removing the first cap insulating film 8 is performed, the side surfaces and the upper surface of the first cap insulating film 8 are covered with the hydrofluoric acid resistant cap side wall insulating film 19 and the second cap insulating film 9, respectively. The first cap insulating film is not etched during the film removal process.

 Note that ion implantation (referred to as channel ion implantation) in the vicinity of a semiconductor region where a channel is formed may be performed at the time when a sacrificial oxide film is provided. Also, channel ion implantation may be performed in other process steps!

 [0063] Similar to the normal MOSFET fabrication process, gate sidewalls 14, cobalt silicide, -silicide silicide 15 such as silicide, interlayer dielectric 16 such as SiO, and metal

 2

 The contact 17 and the wiring 18 are sequentially formed. This cross-sectional view is shown in Fig. 7, and the plan view is shown in Fig. 8.

 [0064] The upper and side surfaces of the first cap insulating film 8 are respectively resistant to the second cap insulating film 9 and the cap side wall insulation that are resistant to the pretreatment for forming the gate insulating film (removal of sacrificial oxide film by hydrofluoric acid) Since it is covered with the film 19, the first cap insulating film 8 is not etched by the pretreatment for forming the gate insulating film.

Further, when the first cap insulating film 8 is made of a material having a lower dielectric constant than the second cap insulating film 9 and a lower dielectric constant than the cap side wall insulating film 19, for example, the entire cap insulating film is formed. (First cap insulating film 8, second cap insulating film 9, cap side wall insulating film 19 as a whole) Compared to the case where SiN is resistant to hydrofluoric acid, the upper part of the semiconductor layer and the gate electrode

 3 4

 The capacity between is reduced. When this capacitance is reduced, the electric field concentration from the gate electrode on the semiconductor layer is reduced. When the electric field concentration from the gate electrode in the upper part of the semiconductor layer is relaxed, leakage current called GIDL (Gate Induced Drain Leakage) is reduced and the threshold voltage formed at the upper corner of the semiconductor layer is low. Leakage current due to the transistor is also suppressed.

[0066] (Second embodiment)

 In the first embodiment, the side wall of the first cap insulating film 8 is not formed by a film forming technique such as CVD, such as radical nitridation, thermal nitridation, or nitrogen ion implantation. Resistant to pre-treatment processes such as sacrificial oxide film removal by modification technology (more effective than wet SiO etching using HF solution)

 2) The method of forming the cap side wall insulating film 19 with a low etching rate will be described (in the first embodiment, a side etching resistant region is provided on the side surface of the first cap insulating film 8; In the second embodiment, the side surface of the first cap insulating film becomes a side etching resistant region containing nitrogen by nitriding, so in the second embodiment, the nitriding treatment of the first cap insulating film is performed. The part (the part other than the side etching resistant area) becomes the central area.)

 [0067] On the SOI substrate in which the buried insulating layer 2 and the semiconductor layer 3 are formed on the semiconductor substrate 1 as in the first embodiment, the first cap insulating film material 8 and the second cap insulating film material (upper surface resistance Etching region material) 9 is deposited (same as Figure 1). Thereafter, the element region is formed by forming the first cap insulating film material 8 and the second cap insulating film material 9 by forming a resist pattern by normal photolithography as in the first embodiment, and etching using the resist as a mask. (Same as Fig. 2).

 The side surface of the first cap insulating film 8 is nitrided using nitrogen radicals to form a modified layer (side surface etching resistant region material) 20. At this time, the surface of the semiconductor layer 3 is also nitrided (FIG. 9). The nitriding may be performed by a method other than radical nitriding, for example, thermal nitriding. The thickness of the modified layer is typically 1 nm to 5 nm.

[0069] The modified layer 20 on the semiconductor layer is removed by etching back the entire surface of the Si N film by RIE. Then, a cap side wall insulating film (side surface etching resistant region) 19 made of the modified layer 20 is formed on the side surface of the first cap insulating film 8 (FIG. 10).

 The subsequent steps are the same as in the first embodiment. Using the second cap insulating film 9 and the cap sidewall insulating film 19 as a mask, the semiconductor layer 3 is patterned by an etching process such as RIE (FIG. 11).

[0071] Similar to the normal MOSFET formation process, the gate insulating film 4 is formed, the gate electrode material is deposited and patterned, and the gate electrode 5 is formed. Using the gate electrode as a mask, high-concentration impurities (n channel) n-type dopant in the case of transistors, p-channel in the case of transistor P-type dopant. typically the introduction) such that the impurity concentration becomes 1 X 10 ¹⁹ cm_ ³ or more is introduced by ion implantation, the source / drain region 6 Forming completes the transistor.

 At this time, prior to the formation of the gate insulating film, a step of once thermally oxidizing the side surface of the silicon layer exposed by etching to form a sacrificial oxide film and then removing the sacrificial oxide film with dilute hydrofluoric acid. Even if it is carried out, the side surface and the upper surface of the first cap insulating film 8 (central region) are covered with the hydrofluoric acid resistant cap side wall insulating film 19 and the second cap insulating film, respectively. The first cap insulation film (center area) is not etched during the film removal process (Fig. 12).

 [0073] Similar to the normal MOSFET fabrication process, gate sidewalls 14, cobalt silicide, -silicide silicide 15 such as silicide, interlayer dielectric 16 such as SiO, and metal

 2

 Next, contact 17 and wiring 18 are formed. A cross-sectional view is shown in FIG. The plan view is the same as Fig. 8. Moreover, the modification of material and a dimension is the same as 1st embodiment.

[0074] It should be noted that the modified layer 20 is a perfect Si N film. A large amount (typically 5% or more,

 3 4 2

 More preferably, it may be a film into which nitrogen of 15% or more is introduced. The nitrogen content in these modified layers can be set to a desired content depending on the nitriding conditions.

In the case of the first embodiment, since the cap sidewall insulating film 19 is provided on the side surface of the first cap insulating film 8, the entire cap insulating film (first cap) is formed by the thickness of the cap sidewall insulating film 19. The width in the fin width direction of the insulating film, the second cap insulating film, and the cap sidewall insulating film as a whole) (width in the horizontal direction in FIG. 5 (a): width in the direction perpendicular to the channel current) increases. However, in the second embodiment, the cap side wall insulating film on the side surface inside the first cap insulating film 8 19 is provided, so that the entire width of the cap insulating film is suppressed, and as a result, it is easy to reduce the width Wfin (fin width) of the Fin layer formed by etching the semiconductor layer using the cap insulating film as a mask. Become. In general, in a FinFET, the shorter the fin width Wfin, the shorter the channel effect is suppressed and the performance is improved. Therefore, the second embodiment is effective in improving the performance of a short channel transistor.

[0076] In addition, the nitriding process is a nitride film (or SiO film) formed in comparison with the CVD process.

 2 is excellent in processing accuracy as compared with the first embodiment because it is excellent in controllability of the thickness of the region into which nitrogen is introduced in a large amount.

 [0077] (Third embodiment)

 In the first and second embodiments, a form in which the second cap insulating film 9 is not provided may be used. FIGS. 15 and 16 show cases where the second cap insulating film 9 is not provided in the first and second embodiments. The drawings correspond to FIGS. 6 and 12, respectively.

 When the third embodiment is applied to the first embodiment, the upper portion of the first cap insulating film 8 is etched by the pretreatment for forming the gate insulating film, but the side surface is protected by the cap side wall insulating film. Therefore, the cap insulating film does not recede due to etching, and if the first cap insulating film 8 is thicker (typically 15 nm or more), the first cap insulating film is protected by the cap side wall insulating film. Since the film 8 is not lost, the same effect as in the first and second embodiments can be obtained.

 In the second embodiment, the second cap insulating film material 9 is described. However, when the third embodiment is applied to the second embodiment, the first cap insulating film material is used. Only 8 may be deposited, and nitriding treatment (radical nitridation, thermal nitridation, nitrogen ion implantation) may be performed on the upper surface and side surfaces of the first cap insulating film material 8. In this case, the modified layer is formed on the upper surface and the side surface of the first cap insulating film 8. Subsequently, when the modified layer 20 on the semiconductor region is removed prior to the process of etching the semiconductor region, for example, the modified layer 20 on the cap insulating film is covered with a resist or the like to complete the process. A transistor having a modified layer 20 on the upper and side surfaces of the cap insulating film can be obtained. This configuration is also effective in suppressing the exposure of the upper corner of the semiconductor and obtaining the effects of the invention.

[0080] When the third embodiment is applied to the second embodiment, an oxide film (first cap insulation If a condition in which the nitridation rate of the film) is larger than the nitridation rate of the semiconductor layer is used, a thicker nitride film is formed on the first cap insulating film than on the semiconductor layer in the process corresponding to FIG. Even if the nitride film on the first cap insulating film is left after the removal of the nitride film on the layer and the deposition of the second cap insulating film 9 is omitted, the upper and side surfaces of the first cap insulating film are nitrided. A structure covered with a film can be formed.

 [0081] (Fourth embodiment)

 The first, second, and third embodiments may be used for manufacturing a FinFET that does not have the buried insulating layer 2. The manufacturing method is the same as that of the first, second, and third embodiments except that a normal Balta substrate is used instead of the SOI substrate and a step of forming the field insulating film 21 is included. In the present invention, the “base” means an arbitrary plane parallel (horizontal) to the substrate.

 FIG. 17 and FIG. 18 show cases where the buried insulating layer is not provided in the first and second embodiments.

 The drawings correspond to FIGS. 6 and 12, respectively.

 [0083] The field insulating film 21 is formed by etching a silicon substrate to form a Fin region (for example, in FIG. 5 and FIG. 11, it does not have a portion corresponding to the buried insulating layer 2, and the lower portion of the semiconductor region 3 is buried and insulated. The layer 2 is extended downward by the thickness of the layer 2 and the extended part corresponds to the form connected to the semiconductor substrate 1). After that, for example, an insulating film is deposited (for example, SiO is deposited by CVD), the second

 2

 Planarization of the insulating film by CMP (SiO deposited by CVD in the above example) using the Yap insulating film as a mask, and selective selection of the insulating film (SiO deposited by CVD in the above example)

2 2 Can be formed by performing a back-back. At this time, in FIG. 5 and FIG. 11, a field insulating film 21 made of an insulating film (SiO deposited by CVD in the above example) is formed in the portion corresponding to the buried insulating layer 2 except for the lower portion of the semiconductor region. Is done.

 2

 [0084] (Another embodiment of the invention)

The FinFET of each embodiment is a double gate type field effect transistor in which a thick cap insulating film is provided on a semiconductor region and a channel region is formed only on a side surface. The FinFET of each embodiment has a semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and a gate insulating film provided on the side surface of the semiconductor region. A gate electrode extending to the side of the semiconductor region is provided so as to straddle the upper force semiconductor region of the cap insulating film and the cap insulating film. Also A source Z drain region is provided on both sides of the gate electrode in the semiconductor region.

 In the FinFET cap insulating film of each embodiment, at least a part of the side surface in the extending direction of the side surface of the semiconductor region that is in contact with the semiconductor region is made of SiO with respect to wet etching using an HF solution. Is also a side etching resistant region with a low etching rate (half

 2

 (At least a part of the side surface of the cap insulating film located in the direction in which the side surface of the conductor region extends upward is a side etching resistant region).

The FinFET of each embodiment includes a step of forming a first insulating film, a step of providing an insulating film side wall made of a second insulating film in contact with a side surface of the first insulating film, and a first insulating film And a step of forming a semiconductor region protruding upward with respect to the substrate plane by etching the semiconductor layer using the second insulating film (insulating film side wall) as a mask. The step of forming the first insulating film corresponds to, for example, the step of forming the central region of the first embodiment and the second embodiment. The step of forming the second insulating film corresponds to the step of forming the side face etching resistant region (cap side wall insulating film) of the first embodiment and the second embodiment.

 [0087] The semiconductor substrate 1 is typically a silicon substrate. The buried insulating layer 2 is typically SiO, and its film thickness is typically 50 nm and 400 nm. However, buried insulating layer

2

 The effects of the invention remain the same even if the material and film thickness of 2 have other configurations. The semiconductor layer 3 is typically silicon. The semiconductor layer may be silicon germanium, germanium, or other semiconductor material. Further, it may be a multilayer film having a material force other than silicon and silicon, or a multilayer film having a material force other than silicon. The thickness of the semiconductor layer 3 is typically 20 nm to 200 nm, but the effect of the invention does not change even if the film thickness has other configurations.

[0088] The second cap insulating film 9 and the cap side surface insulating film 19 are pretreatment steps prior to the formation of the gate insulating film, specifically, for example, removal of the sacrificial oxide film by hydrofluoric acid, dilute hydrofluoric acid, or buffered hydrofluoric acid. In contrast, any material that is resistant (hereinafter referred to as a material resistant to hydrofluoric acid) may be used. The term “resistance” as used herein means that the etching rate for the sacrificial oxide film (SiO film) is smaller than that for wet etching using a hydrofluoric acid solution. The rate is preferably 1Z2 or less, more preferably 1Z5 or less.

[0089] Hydrofluoric acid solutions having various configurations and concentrations are used for removing the sacrificial acid film, but as a material resistant to hydrofluoric acid, for example, a wet solution at room temperature using 1% solution dilute hydrofluoric acid is used. A material whose etching rate is lower than that of SiO film formed by thermal oxidation.

 2

 You only have to choose a fee. More typically, a material with an etching rate of 1Z2 or less of the SiO film formed by thermal oxidation with respect to wet etching at room temperature using 1% dilute hydrofluoric acid as a material resistant to hydrofluoric acid It is preferred to choose a material that is less than 1Z5

 2

 More preferred to choose.

[0090] The reason for this is the typical sacrificial acid film removal process, which is resistant to the above-described resistance to wet etching at room temperature using a 1% dilute hydrofluoric acid solution. (1Z2 or less, more preferably 1Z5 or less).

 2

 Therefore, the composition and concentration of the hydrofluoric acid solution that is actually used to remove the sacrificial oxide film differs from the 1% dilute hydrofluoric acid solution.

 2

 Even if the etching rate differs from the case of wet etching at room temperature using 1% dilute hydrofluoric acid, the above hydrofluoric acid resistant material has sufficient etching resistance to obtain the effects of the invention. Obtained (with etching rate sufficiently lower than SiO)

 2

 This is a force that can be considered good if the resistance to wet etching at room temperature using a 1% dilute hydrofluoric acid solution is used as a criterion for material selection.

 [0091] Even when the sacrificial oxide film is removed by an etching process other than wet etching, such as plasma etching or chemical dry etching, wet etching at room temperature using a 1% dilute hydrofluoric acid solution is performed. In contrast, if the material has the above resistance, it is common to have etching properties in etching processes other than these wet etchings. Therefore, it is suitable for wet etching at room temperature using a 1% dilute hydrofluoric acid solution. If resistance is the criterion for material selection, it is acceptable.

 [0092] The material resistant to hydrofluoric acid typically includes a silicon compound having a nitrogen concentration of 5 atomic% or more. Typically, Si N, SiON, radical nitridation, nitrogen by thermal nitridation

 3 4

 Examples include SiO films with atoms introduced.

 2

[0093] In the present invention, the etching rate of the material constituting the side surface etching resistant region with SiO. The sacrificial oxide film is removed under the condition that the size relationship of the gates does not change. That is, the etching rate of the material constituting the side etching resistant region is smaller than the etching rate of SiO! / ヽ

 2

 The sacrificial oxide film is removed under conditions.

 In addition, it is desirable that the material of the first cap insulating film 8 has a lower dielectric constant than that of the cap side wall insulating film 19.

 The first cap insulating film 8 is made of SiO, the second cap insulating film 9 and the cap side surface insulating film 19 are made of

 2

 The formation of Si N is a typical example that satisfies these conditions.

3 4

 Other material combinations that satisfy may be used.

[0096] Further, the entire cap insulating film may be formed of a material resistant to the gate insulating film pretreatment. For example, the entire cap insulating film is made of SiN that is resistant to etching with hydrofluoric acid. Even in this case, the cap insulating film is a gate insulating film.

 3 4

 The problem of being etched by the pre-formation treatment can be solved. However, the capacitance between the gate electrode and the upper part of the semiconductor layer is large (since the relative dielectric constant of Si N is larger than that of SiO),

 3 4 2

 Since the electric field concentrates on the upper part of the semiconductor layer, the leakage current is larger than when the center portion of the cap insulating film is formed of a material having a low dielectric constant.

 Note that in this specification, when simply referred to as a cap insulating film, an insulating layer provided on a semiconductor layer, which includes a first cap insulating film, a second cap insulating film, a cap side wall insulating film, and the like. Means the entire membrane.

 This will be described with reference to FIGS. 19 and 20. 19 and 20 are enlarged views of the vicinity of the upper portion of the semiconductor layer in the cross sections of FIGS. 6 (a) and 7 (a). When the upper corner 2 3 of the semiconductor layer is not covered by the cap insulating film (Fig. 20 (a), Fig. 20 (b)), electric field concentration occurs where the capacitance C1 between the gate electrode and the semiconductor layer is very large, resulting in leakage current Will increase. On the other hand, when the entire cap insulating film 24 is SiN (FIG. 19B), the surface of the cap insulating film

 3 4

 Is Si N and the center is made of a material with a lower dielectric constant than Si N, such as SiO (Fig. 1

3 4 2 3 4

9 (a)) In any case, since the upper corner 23 of the semiconductor layer is covered with the cap insulating film, the capacitance C1 between the gate electrode and the semiconductor layer is smaller than in the case of FIG. Leakage current is reduced. Furthermore, when comparing the cases of FIG. 19 (a) and FIG. 19 (b), the dielectric constant is low at the center of the cap insulating film as shown in FIG. Since the capacitance C 1 with the conductor layer is even smaller than in the case of FIG. 19 (b), the effect of alleviating electric field concentration and reducing leakage current is greater.

The electric field relaxation effect described with reference to FIG. 19 (a) can be obtained if at least a part of the cap insulating film has a region having a dielectric constant lower than that of the cap side wall insulating film. A form in which a region having a dielectric constant lower than that of the cap sidewall insulating film may be provided in at least a part of the insulating film. For example, in the configuration of FIG. 19 (a), a very small part of the first cap insulating film close to the semiconductor region is attracted more than SiO such as SiON and SiN.

 3 4 2 It may be formed by a region having a high electric conductivity. However, it is preferable that the volume ratio of the region having a low dielectric constant in the total volume of the cap insulating film is larger because the electric field relaxation effect described with reference to FIG. In addition, if a region having a low dielectric constant is provided near the upper corner of the semiconductor region, the electric field relaxation effect described with reference to FIG. It is preferable to provide a region having a dielectric constant lower than that of the cap side wall insulating film in the sandwiched region. Particularly, a region having a dielectric constant higher than that of the cap side wall insulating film is sandwiched between the cap side wall insulating film and in contact with the cap side wall insulating film. However, it is preferable that the area is provided with a low area.

[0100] The dielectric constant is lower than that of the cap sidewall insulating film, and the region satisfies this condition except for SiO.

 It may be formed of the second material such as SiOF or an organic film. Also, the dielectric constant is lower than that of the cap sidewall insulating film, and the region may be a cavity.

[0101] The cap sidewall insulating film 19 is typically a SiN film. Cap sidewall insulation film 19 thickness

 3 4

 The thickness is typically from 2 nm to 20 nm, usually in the range of 3 nm to 10 nm. However, it does not have to be in this range. In particular, when the cap sidewall insulating film 19 is formed by plasma nitriding or the like, it may be 3 nm or less, for example, 1 to 2 nm. In addition, there is a process for forming the cap side wall insulating film 19, but the cap side wall insulating film 19 is lost by a pretreatment process prior to forming the gate insulating film, etc., and a manufacturing method that does not remain in a completed transistor is used. This is also effective because once the cap sidewall insulating film 19 having high resistance to pretreatment is provided, the loss of the first cap insulating film is reduced.

[0102] In the drawings of the present specification, the semiconductor region, the first cap insulating film, and the second cap insulating film are illustrated as being substantially rectangular parallelepipeds as typical examples. It may have a shape deviated from a rectangular parallelepiped due to the influence of the manufacturing process such as the oxidization process and thermal oxidation process. For example, a corner of the semiconductor region may be rounded by a thermal oxidation process such as sacrificial oxidation or gate oxidation. Also, due to the influence of the etching process such as RIE, the side surfaces of each component such as the semiconductor region, the first cap insulating film, and the second cap insulating film may be tapered or have a gently curved surface. ! ,.

 [0103] The fin width (the width Wfin of the semiconductor layer 3 in the horizontal direction in FIG. 7A) is normally 5 nm to 50 nm, typically lOnm to 35 nm. However, in a fine transistor with a gate length of 50 nm or less, the fin width Wfin may be 5 nm or less.

 [0104] In the embodiment, the element region has a single rectangular shape. However, the element region may have a multi-fin structure in which a plurality of fins (semiconductor regions) are combined. In this case, the AA ′ section in FIG. 14 has a shape corresponding to the AA ′ section in each embodiment of the present invention. The fins in FIG. 14 are arranged so that the channel current directions flowing in the fins are parallel to each other. In the field effect transistor of FIG. 14 (a), an independent gate electrode and source Z drain region are provided for each fin. In the field effect transistor of FIG. 14 (b), in addition to the fins, a connection semiconductor region 31 extending in a direction orthogonal to the channel current direction and connected via the fins is one of the source Z drain regions. It is provided as a part. One gate electrode is formed so as to straddle the fins connected by the connecting semiconductor region 31.

 [0105] The gate electrode is made of polysilicon, or a conductive material such as metal or metal silicide.

 [0106] The channel formation region (portion covered by the gate electrode) of the semiconductor region forming the fin region may or may not be doped with impurities. When the gate electrode is polysilicon, a p-type impurity is usually introduced in an n-channel transistor, and an n-type impurity is introduced in a p-channel transistor.

[0107] The present invention is intended to prevent the upper corner of the semiconductor layer located below the cap insulating film (8, 9, 22) from being exposed by providing the cap side surface insulating film 19. The cap side insulating film 19 does not need to cover the entire side surface of the cap insulating film (8, 9, 22). It only needs to cover the lower side of the membrane. Further, a manufacturing process that covers only the side surface of the portion of the cap insulating film that is in contact with the semiconductor layer, that is, the lower side surface of the cap insulating film, may be used. Examples of these are shown in Figs.

FIG. 26 (a), FIG. 26 (b), and FIG. 26 (c) are cross-sectional views corresponding to the steps and cross sections of FIG. 4 (a), FIG. 5 (a), and FIG. 6 (a), respectively. is there. In this embodiment, in the third embodiment in which the cap insulating film 22 is a single layer (typically made of SiO), the cap cover insulating film 10 is deposited on the whole.

2

 After that, when the cap cover insulating film 10 is etched back by an etching process such as RIE to form the cap side wall insulating film 19, when the etch back time is set long, the cap cover insulating film on the side surface of the cap insulating film It is formed by the upper part of 10 being etched away.

[0109] FIGS. 27 (a), 27 (b), and 27 (c) are cross sections corresponding to the steps and cross sections of FIGS. 4 (a), 5 (a), and 06 (a), respectively. FIG. In this configuration, the cap insulating film has two layers (typically, a first cap insulating film 8 made of SiO and a second cap insulating film made of Si N.

 2 3 4

 In the first embodiment of the film 9), as in the case of FIG. 26, after the cap cover insulating film 10 is deposited on the entire surface, the cap cover insulating film 10 is etched by an etching process such as RIE to insulate the cap side wall. In the step of forming the film 19, when the etching back time is set long, the upper portion of the cap cover insulating film 10 on the side surface of the cap insulating film is etched and lost.

 FIG. 28 is a plan view corresponding to the planes of FIGS. 6 (c) and 8, and shows the positional relationship between the gate electrode 5 and the semiconductor layer 3. FIG. 29 is a cross-sectional view corresponding to the step and cross section of FIG. 7 (b).

In the present invention, in the region covered with the gate electrode (symbol 25 in FIG. 28, hatched portion), the upper corner of the semiconductor layer located under the cap insulating film (8, 9, 22) is exposed. This is intended to prevent this by providing the cap side insulating film 19, so that the cap side insulating film 19 is provided in the region not covered by the gate electrode (symbol 26 in FIG. 28, dot portion). Any of the structure and the manufacturing method and the structure and the manufacturing method in which the cap side surface insulating film 19 is not provided may be used. In addition, a cap side surface insulating film 19 is provided in a part of a region not covered by the gate electrode (symbol 26 in FIG. The structure and the manufacturing method may be used without the cap side insulating film 19 being provided.

[0112] In addition, in the entire region of the cap insulating film covered with the gate electrode (symbol 25 in FIG. 28, hatched hatched portion), the region covered with the gate electrode (see FIG. The cap side surface insulating film 19 is not provided in a part of the symbol 25 of FIG. 28 (hatched hatched portion), but at least both sides of the region 25 covered by the gate electrode parallel to the direction connecting the source Z drain (FIG. 28). It is also possible to use a structure and a manufacturing method in which the cap side surface insulating film 19 is provided over a certain region in each of the symbols 25 in FIG. A cap side insulating film 19 is provided in the central portion of the gate electrode and in the vicinity thereof (the lower portion in the vicinity of the position indicated by A—A ′ in FIG. 28 and the vicinity thereof), and is directed toward the source / drain region of the gate electrode. A structure in which the cap side-surface insulating film 19 is not provided in the vicinity of the force end may be used.

 [0113] In the direction connecting the source Z drain region, if there is a region where the upper corner of the semiconductor region is not exposed even in only a part of the region, a parasitic transistor is formed in the upper corner of the semiconductor region. Since the leakage current due to the transistor is suppressed, even if the cap side surface insulating film 19 is not provided in the entire region covered with the gate electrode of the cap insulating film, the cap is placed in one place in the direction connecting the source Z drain. If the side insulating film 19 is provided, the effect of the invention can be obtained.

 [0114] That is, a side etching resistant region is provided over the entire length of the side surface of the cap insulating film covered with the gate electrode in the direction connecting the opposing source Z drain regions (channel current direction). It can be provided only on a part of it. (It is acceptable if all of the side surfaces of the cap insulating film covered by the gate electrode are side etching resistant regions. It may be a side etching resistant region.)

 [0115] For the same reason, an upper surface etching-resistant region is provided over the entire length of the upper surface covered with the gate electrode of the cap insulating film in the direction connecting the opposing source Z drain regions (channel current direction). It ’s okay, and it ’s only part of it! / It ’s okay!ヽ (Of the cap insulating film, the entire upper surface covered with the gate electrode may be an upper surface etching resistant region, or a part of the upper surface may be an upper surface etching resistant region).

[0116] However, the purpose is to obtain the GIDL suppression effect in addition to the parasitic transistor suppression effect. In some cases, it is desirable that the cap side surface insulating film 19 is provided on the semiconductor region near the end of the source Z drain region, for example, near the pn junction between the source Z drain region and the channel forming region.

 In this specification, “side surface” refers to a surface substantially perpendicular to the substrate of each component (semiconductor region, central region, cap insulating film, SiO region). Also, especially “covered by the gate electrode

 2

 The side surface in the direction of extension of the side surface of the semiconductor region of the cap insulating film represents a surface substantially perpendicular to the substrate and substantially parallel to the direction facing the source Z drain region (channel current direction). Further, the “upper surface” represents a surface substantially parallel to the base of each component. However, this includes cases where they are not completely vertical or not parallel due to process reasons. The cap insulating film of the present invention has a side surface in the extending direction of the semiconductor region (a side surface when the side surface of the semiconductor region is extended upward in the surface direction). In this specification, the side etching resistant region is formed on at least a part of the side defined as described above. Further, an upper surface etching resistance region and a side surface etching resistance region are formed on at least a part of the upper surface and the side surface, respectively.

 [0118] In this specification, when the top surface etching resistant region and the side surface side etching resistant region are in contact with each other, the side surface etching region covers the side surface of the top surface etching resistant region at the portion where both are connected. Alternatively, the upper surface etching resistant region may cover the upper surface of the side surface etching resistant region (FIG. 13 (a)). Further, the side surface etching resistant region and the upper surface etching resistant region may be formed of a continuous material.

That is, in the present invention, the portion of the cap insulating film that is in contact with the cap insulating film may be a top surface etching resistant region or a side surface etching resistant region. Whether this region is the top etching resistant region or the side etching resistant region depends on the FinFET manufacturing method. For example, in the manufacturing method of the first embodiment, as shown in FIG. 7 (a), the side region etching region 19 is provided on the side surfaces of the central region 8 and the upper surface etching region 9, and the cap insulating film The upper corner is a side etching resistant region. On the other hand, in the manufacturing method of the second embodiment, as shown in FIG. 13 (a), the upper surface etching resistant region 9 is provided on the upper surface of the central region 8 and the side surface etching resistant region 19, and the upper portion of the cap insulating film is formed. The corner is the upper etching resistant area. [0120] In the present invention, in the cross section perpendicular to the channel current direction (the cross section perpendicular to the direction connecting the source Z drain region. For example, the cross section corresponding to the cross section of FIG. The upper surface etching resistant region covers the entire upper surface of the cap insulating film, or the side surface etching resistant region and the upper surface etching resistant region connect, and the sacrificial oxide layer of the cap insulating film is connected. Parts that are not etch resistant to the etching of the film (typically not hydrofluoric acid resistant !, more typically parts of the cap insulating film that are not side etch resistant areas, more typically The upper surface etching resistant region covers the entire upper surface of the central region, and more specifically, the portion made of SiO, for example.

 2

 Since the cap insulating film is covered with a material having etching resistance in its cross section, the effect of preventing the etching of the cap insulating film is particularly large.

 Further, the first cap insulating film and the cap side wall insulating film are arranged on the upper surface of the semiconductor region, and the bottom portion of the first cap insulating film and the bottom portion of the cap side wall insulating film have the same height. However, there may be a slight step difference between the bottoms of the two due to process reasons, for example, the etching process of the first cap insulating film.

 [0122] In addition, when the sacrificial oxidation or the gate insulating film is formed, the insulating film having a very thin film thickness that is thinner than the sacrificial oxide film or thinner than the gate insulating film is formed between the cap sidewall insulating film and the semiconductor region. However, these extremely thin insulating films do not significantly affect the effect of the invention and have little effect on the transistor characteristics. In the present specification, it is also described that the cap side wall insulating film and the semiconductor region are in contact with each other when an insulating film having a weak thickness penetrates between the cap side wall insulating film and the semiconductor region. The same applies to the case where a gap of a very small height generated by etching an insulating film having such a small thickness enters between the cap sidewall insulating film and the semiconductor region.

 [0123] FIG. 7 (b) shows that the cap insulating films (first cap insulating film 8, second cap insulating film 9, cap side surface insulating film 19) are the source in the region 26 not covered with the gate electrode. FIG. 6 is a cross-sectional view of a form that is removed for forming a drain region and forming a silicide region on a source Z drain region.

[0124] FIG. 29 shows that a cap insulating film (first key) is formed on a part of the region 26 not covered with the gate electrode. It is a cross-sectional view of a form in which the yap insulating film 8, the second cap insulating film 9, and the cap side surface insulating film 19) remain, which is a process for forming a source Z drain region or a silicide region forming process on a source Z drain region Even when the transistor is completed, the cap insulating film (first cap insulating film 8, second cap insulating film 9, The cap side surface insulating film 19) remains. In this configuration, for example, when the source Z drain region is formed by oblique ion implantation of the side force of the semiconductor layer, it is not formed to the end of the source Z drain region of the silicide region. It is formed when it is not necessary to completely remove the film.

[0125] It should be noted that the composition ratio of atoms in a plurality of element force materials, for example, materials such as SiO and SiN, used as components of the field effect transistor in each embodiment.

 2 3 4

 Does not work even if the stoichiometric compositional power deviates to some extent. In particular, Si N film used as a material resistant to hydrofluoric acid can be used as long as the required hydrofluoric acid resistance is obtained.

 3 4

 The composition may be separated from the stoichiometric composition power.

[0126] The constituent materials of the field effect transistor of the present invention, such as SiO and SiN, include

 2 3 4

 Clearly, other elements may be mixed within a range satisfying the etching rate range specified above.

 [0127] The channel formation region (the portion of the semiconductor region sandwiched between the source Z and drain regions and covered with the gate electrode) may be subjected to low concentration channel ion implantation. May not be performed. In addition, a channel forming region adjacent to the first conductivity type source Z drain region may have a halo region into which the second conductivity type impurity is introduced over a certain width.

Claims

The scope of the claims  [1] A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and an upper force of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;  The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And  Of the cap insulating film covered with the gate electrode, at least a part of the side surface in the direction of extension of the side surface of the semiconductor region that is in contact with the semiconductor region is subjected to wet etching using HF solution by SiO. The etching rate is low and the side etching resistant region is  2  A field effect transistor characterized by having.  [2] The side surface etching resistant regions are provided opposite to each other on the two opposite side surfaces covered with the gate electrode of the cap insulating film, and are sandwiched between the opposing side surface etching resistant regions in the cap insulating film. 2. The field effect transistor according to claim 1, wherein the field effect transistor has a central region made of a material different from the side etching resistant region at a position.  3. The field effect transistor according to claim 2, wherein the central region has a material force having a dielectric constant lower than that of the side etching resistant region.  [4] The field effect according to claim 2 or 3, wherein the central region has SiO force.  2  Type transistor.  [5] The side etching resistant region is provided over the entire length of the side surface of the cap insulating film covered with the gate electrode in the direction connecting the opposing source Z drain regions. The field effect transistor according to any one of 1 to 4 [6] The side surface etching-resistant region also has SiN force.  3 4  1. The field effect transistor according to item 1. 7. The field effect transistor according to any one of claims 1 to 5, wherein the side etching resistant region is made of a material containing silicon, nitrogen, and oxygen. [8] The cap insulating film has at least a top surface including a top surface anti-etching region having a lower etching rate than SiO for wet etching using an HF solution. 2  The field effect transistor according to claim 1, wherein: [9] The field effect transistor according to [8], wherein the upper surface anti-etching region constitutes at least a part of an upper surface of the cap insulating film covered with the gate electrode.  [10] The upper surface anti-etching region is provided over the entire length of the upper surface of the cap insulating film covered with the gate electrode in the direction connecting the opposing source z drain regions. 9. The field effect transistor according to 8. [11] The method according to any one of claims 8 to 10, wherein the etching resistance region on the upper surface also has SiN force.  3 4  2. Field effect transistor according to item 1. 12. The upper surface etching resistant region is made of a material containing silicon, nitrogen, and oxygen. The field effect transistor according to any one of to 10. [13] The cap insulating film according to any one of claims 1 to 12, wherein the cap insulating film has a substantially rectangular parallelepiped shape. 2. The field effect transistor according to item 1. [14] The field effect transistor according to [7] or [12], wherein a nitrogen content in the material containing silicon, nitrogen, and oxygen is 5 atomic% or more. [15] The cap insulation film strength is higher than that of SiO for wet etching using HF solution.  2. The field effect transistor according to claim 1, wherein the chin rate is low and the material strength is high.  [16] The whole of the cap insulating film also has SiN force.  3 4  Field effect transistor.  [17] A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and an upper force of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region; A source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered by the gate electrode, and a channel region is formed on a side surface of the semiconductor region. A field effect transistor,  The cap insulating film includes a SiO region provided on the semiconductor region,  2  Si N regions provided on the upper surface and both side surfaces of the SiO region;  2 3 4  A field-effect transistor characterized in that it also has power. [18] A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and an upper force of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;  The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And  The cap insulating film includes a SiO region provided on the semiconductor region,  2  Contains silicon, oxygen and 5 atomic% or more of nitrogen provided on both sides of the SiO region. 2  Having a SiON region;  Si N region provided on the upper surface of the SiO region and SiON region;  2 3 4  A field-effect transistor characterized in that it also has power. [19] A semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and an upper force of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;  The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And  The cap insulating film includes a SiO region provided on the semiconductor region,  2  The silicon, oxygen, and 5 atomic% or more provided on the upper surface and both side surfaces of the SiO region 2  A SiON region containing nitrogen;  A field-effect transistor characterized in that it also has power. [20] A semiconductor region protruding upward with respect to the substrate plane and provided on the upper surface of the semiconductor region A cap insulating film, an upper force of the cap insulating film so as to straddle the semiconductor region and the cap insulating film, and a gate electrode extending laterally of the semiconductor region, and between the gate electrode and a side surface of the semiconductor region. A gate insulating film interposed between  The field effect transistor has a source Z drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region is formed on a side surface of the semiconductor region. And  The cap insulating film includes a SiO region provided on the semiconductor region,  2  Si provided on both side surfaces of the SiO region and projecting upward from the side surface of the SiO region 2 2 3 N region,  Four  A field-effect transistor characterized in that it also has power. 21. The field effect transistor according to claim 1, wherein a plurality of semiconductor regions are arranged so that directions of channel currents flowing in the semiconductor regions are parallel to each other. The field effect transistor according to any one of the above. [22] A method for manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,  A plating process for forming a patterned first insulating film on the semiconductor layer, and an insulating film sidewall made of a second insulating film in contact with the side surface of the first insulating film, Providing the semiconductor layer exposed in the etching step for forming an insulating film at a position near the patterned first insulating film, the first insulating film, and the second insulating film Forming a semiconductor region protruding upward with respect to the plane of the substrate by etching the semiconductor layer using the insulating film sidewall made of the insulating film as a mask; and  A method for producing a field-effect transistor, comprising: [23] forming a sacrificial oxide film on a side surface of the semiconductor region protruding upward with respect to the substrate plane; And a step of removing the sacrificial oxide film by wet etching, wherein the side wall of the semiconductor region is formed on the side surface of the semiconductor region with respect to the wet etching. Made of a material with a lower etching rate than 23. The method of manufacturing a field effect transistor according to claim 22, [24] A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,  (a) a sacrificial acid formed on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer, the portion having a pair of side surfaces perpendicular to the semiconductor layer and facing each other, and in contact with the semiconductor layer on the pair of side surfaces A step of providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film;  (b) using the cap insulating film as a mask and forming a semiconductor region protruding above the base force under the cap insulating film;  A method for producing a field-effect transistor, comprising: [25] After the step (b),  (c) forming a sacrificial oxide film on the side surface of the semiconductor region;  (d) removing the sacrificial oxide film by wet etching;  The method for producing a field effect transistor according to claim 24, further comprising:  [26] A step of forming a gate insulating film on the side surface of the semiconductor region from which the sacrificial oxide film has been removed, and a step of depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode When,  Introducing a impurity on both sides of the semiconductor region sandwiching the gate electrode to form a source Z drain region;  26. The method for producing a field effect transistor according to claim 23, further comprising:  [27] (a) the step of providing a cap insulating film,  Providing a central region on the semiconductor layer;  Providing a side etching resistant region on a side surface of the central region by depositing a side etching resistant region material on the semiconductor layer and the central region and then performing an etch knock; The field effect transistor according to any one of claims 24 to 26, wherein The manufacturing method of the star. [28] (a) the step of providing a cap insulating film,  After the central region material is deposited on the semiconductor layer and the top surface etching resistant region material is deposited on the central region material, the central region material and the top etching resistant region material are patterned, and wet etching is performed on the central region. Providing a top surface etching resistant region having an etching rate lower than that of the sacrificial oxide film formed on the side surface of the semiconductor region;  Providing a side surface etching resistant region on the side surface of the central region and the top surface etching resistant region;  27. The method of manufacturing a field effect transistor according to claim 24, wherein [29] The step of providing the side etching resistant region comprises:  29. The method of manufacturing a field effect transistor according to claim 28, wherein the step of etching back after depositing the side face etching resistant region material on the entire surface is performed. [30] The side etching region material and the top surface etching region material are deposited by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. 30. A method of manufacturing a field effect transistor according to claim 27. [31] (a) the step of providing a cap insulating film,  A step of providing a substantially rectangular parallelepiped cap insulating film material on the semiconductor layer, and a condition that the nitriding rate of the cap insulating film material is higher than the nitriding rate of the semiconductor layer, and the side surface and the upper surface of the cap insulating film material and the semiconductor Performing a nitridation process on the layer, performing etch back, the side surface on which the cap insulating film material has been subjected to the nitriding process on the side surface, and a top surface on which the nitriding process on the cap insulating film material has been performed on the top surface. A process of making a region,  27. The method of manufacturing a field effect transistor according to claim 24, wherein [32] (a) the step of providing a cap insulating film, A substantially rectangular parallelepiped cap insulating film material on the semiconductor layer, and the cap insulating film material Providing a top surface anti-etching region on the substrate,  Nitriding the side surfaces of the cap insulating film material and the semiconductor layer, performing etch back, and setting the side surfaces of the cap insulating film material subjected to the nitriding treatment to side etching resistant regions;  27. The method of manufacturing a field effect transistor according to claim 24, wherein  33. The method of manufacturing a field effect transistor according to claim 31 or 32, wherein the nitriding treatment is radical nitriding, thermal nitriding, or nitrogen ion implantation.  [34] The method according to any one of claims 26 to 33, further comprising a step of removing a cap insulating film that is covered with the gate electrode and provided on the semiconductor region, of the cap insulating film. 2. The method for producing a field effect transistor according to any one of the above.  [35] The step (a) providing the cap insulating film is made of a material having a lower etching rate on the semiconductor layer than the sacrificial oxide film provided on the side surface of the semiconductor region with respect to wet etching. 27. The method of manufacturing a field effect transistor according to claim 24, wherein the step of patterning is performed after the cap insulating film material is deposited.  36. The field effect according to claim 23, wherein the wet etching is wet etching using an HF solution, and the sacrificial oxide film is made of SiO.  2  Type transistor manufacturing method.