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WO2006000095A1 - Systeme d'horloge universel d'heterodyne - Google Patents

Systeme d'horloge universel d'heterodyne Download PDF

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Publication number
WO2006000095A1
WO2006000095A1 PCT/CA2005/000995 CA2005000995W WO2006000095A1 WO 2006000095 A1 WO2006000095 A1 WO 2006000095A1 CA 2005000995 W CA2005000995 W CA 2005000995W WO 2006000095 A1 WO2006000095 A1 WO 2006000095A1
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WIPO (PCT)
Prior art keywords
clock
output
phase
clocks
sub
Prior art date
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Ceased
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PCT/CA2005/000995
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English (en)
Inventor
John W. Bogdan
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Individual
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H03L7/235—Nested phase locked loops

Definitions

  • phase synthesizers is represented by the following documents: Dl (US 5,257,294 invented by Fried at al); D2 (US 6,046,644 invented by Pitot at al); D3 (US 5,602, 884 invented by Kenny at al); D4 (PCT/CA02/01873 invented by Bogdan).
  • present frequency synthesizers have relatively high phase jitter levels, and provide limited resolution and accuracy of generated frequencies.
  • said present frequency synthesizers including fractional synthesizers, do not allow phase control functions which would cover transitional phase conditions during frequency switching operations. Therefore said frequency synthesizers can only provide a carrier frequency for data transmitters, but cannot implement an actual carrier phase or a frequency modulation with transmitted data.
  • Said deficiencies of the present frequency synthesizers degrade their performances in IF generation for data receivers as well, because they impair synthesizers ability to maintain an accurate locking to the received signal carrier frequency and phase.
  • synthesized clock generators which are designed for network synchronization systems, provide only limited ranges of frequency and phase modulations.
  • Prior art clock synchronization systems require expensive local oscillators, expensive external off-chip analog components, and expensive IC technologies suitable for mixed mode operations; in order to provide highly stable and low jitter synchronization clocks required in industrial control systems and in communication networks.
  • State of art network synchronizers represented by D3, D4 require use of a multiplication of a local reference clock for producing synchronizer output clocks. Since feasible multiplication factors can not be risen too high without compromising stability margins, a very accurate local reference clock must provide a relatively high clock frequency and the higher frequency increases the cost and the complexity of said local oscillator. In addition to that: since said local clock multiplications can provide only a fixed set of multiplication factors, current synchronizers require specific local reference frequencies and it limits a choice of local oscillators.
  • the DWS MSC invention comprises; a 1 -P phase generator, a synchronous sequential phase processor (SSPP) for real time processing and selection of a phase of out-coming wave-form, and a programmable computing unit (PCU) for controlling SSPP operations and supporting signal synthesis algorithms.
  • SSPP synchronous sequential phase processor
  • PCU programmable computing unit
  • Said SSPP invention comprises a selection of one of multi sub-clocks for providing an edge of out-coming synthesized signal, where said sub-clocks are generated by the outputs of serially connected gates which an SSPP reference clock is propagated through.
  • the SSPP comprises calculating a binary positioning of a next edge of the out-coming wave ⁇ form versus a previous wave edge, which represents a number of reference clock cycles combined with a number of reference clock fractional delays which correspond to a particular sub-clock phase delay versus the reference clock.
  • the SSPP comprises selective enabling of a particular sub-clock, which provides the calculated phase step between the previous and the current wave-form edges.
  • the synchronous sequential processor multiplies processing speed by splitting complex signal processing operation into a sequence of singular micro-cycles, wherein: every consecutive micro-cycle of the complex operation is performed by a separate logical or arithmetical processing stage during a corresponding consecutive time slot synchronous with a reference clock providing a fundamental timing for a synthesized wave-form; serially connected sequential stages are connected to a programmable control unit (PCU), wherein the sequential stages are clocked by reference sub-clocks generated by a reference propagation circuit built with serially connected gates which the reference clock is propagated through; whereby inputs from the PCU are processed into a phase delay between a next edge of the synthesized wave-form versus a previous edge and a position of the next edge is calculated by adding the phase delay to a position of the previous edge, wherein the positions of wave-form edges are provided by a last of the sequential stages and said positions are expressed as numbers identifying reference sub-clocks needed for generating said wave-form edges.
  • SSP synchronous sequential processor
  • the SSPP invention includes using the 1-P phase generator deiined above to generate SSPP clocks which drive said parallel phases and said sequential stages, and to generate selector switching signals for said merging and splitting of processing phases.
  • the SSPP comprises a timing control (TC) circuit, which uses decoding of reference clock counters and/or other wave edge decoding and said SSPP clocks, for performing said time sharing phase assignments and for further control of operations of an already assigned phase.
  • TC timing control
  • Multiplier produces the series of sub-clocks CIkO, CIkR - CIk 1.
  • the sub-clock CIkO keeps clocking in a reversed output of its own selector PRO.
  • the sub-clocks CLkR-CIkI keep clocking in outputs of the previous selectors PRO, PRR - PR2 into their own selectors PRR-PRl. Since the selector PRO is being reversed by every CIkO, every selector in the PRO, PRR - PRl chain is being reversed as well by a falling edge of its own sub-clock CIkO, CIkR - CIk 1, and every selector in the chain represents reversal of its predecessor which is delayed by a single sub-clock fractional delay.
  • the second PS implementation method is based on adjusting alignment between an exit point of the synthesized clock from the reference propagation circuit versus an input reference clock; in a way which adds gate delays for phase increases, and subtracts gate delays for phase decreases.
  • the second method is presented in FIG. IA, and its differences versus the FIG.l are explained below.
  • the moving exit point from the driven by Fsync/2Dsel phase locked delay line is used as a return clock for the PLL x 2Dsel multiplier, instead of using a fixed output of the INVO to be the PLL return clock.
  • the fixed output of the INVO is divided by the programmable frequency divider (PFD) in order to provide the synthesized clock Fsynt, instead of the moving synthesized clock selection point.
  • PFD programmable frequency divider
  • the invention further includes an universal network synchronizer named Heterodyne Timing System (HTS) which is completely integrated into a single chip (see also FIG.4, and FIG.4A).
  • HTS Heterodyne Timing System
  • the HTS invention comprises: using digital phase detectors (DPDs) for measuring phase errors between the APLL output clock and said other HTS reference clocks; using a programmable control unit (PCU) for processing the measured phase errors and producing control codes for the return clock synthesizer, which implement pre-programmed phase and frequency transfer functions between the APLL output clock and said other HTS reference clocks.
  • DPDs digital phase detectors
  • PCU programmable control unit
  • phase transfer control circuits can be implemented as separate on-chip control units or with a single on-chip PCU.
  • the first synchronizer configuration is carried out by an HTS configuration which is based on the DWS MSC, the PS, the DPDl, the DPD2 and the DPD3. As it is shown in FIG.4, the first configuration allows the integration of all the circuits and the functions of the integrated synchronizer, with the exception of the VCXO and eventually the Loop Filter; into a single CMOS ASIC.
  • HTS's APLL mode of operation is described below.
  • One of the first reference clocks F_rl is selected to be applied to the APLL reference input and the return clock synthesizer (RET CS) is switched by the PCU into producing the APLL return clock which is matching said selected first reference clock.
  • the implementation of a DPLL mode is explained below.
  • the APLL output clock f filter is applied to the APLL reference input and the return clock synthesizer (RET CS) is switched by the PCU into producing the APLL return clock which is matching said output clock f filter.
  • the invention includes providing slave mode implementation which replaces the external F_rl clock with the mate HTS output clock f_mate, in order to drive the above described APLL configuration.
  • the slave mode allows maintaining phase alignment between active and reserve HTS units, for the purpose of avoiding phase hits when protection switching reverts to using clocks from the reserve HTS unit.
  • the invention includes using the above mentioned method of slave HTS phase alignment for both the first and for the second synchronizer configurations as well.
  • the above mentioned first PS implementation is selected for the preferred embodiment, and it is shown in the FIG.l , FIG.2, FIG.3 and FIG.5.
  • FSR Fractional Selection Register
  • Timing Control (TC) circuits are shown in FIG.2, the resulting Timing Diagram of Phase Synthesizer (TDPS) is shown in FIG.5, and TC operations are explained below.
  • TC Timing Control
  • the LD_C1 signal enables loading of the Period Counter 1 (PCl) with a number of periods which the previous stages of the Synchronous Sequential phase Processor (SSPP) have calculated for the current phase adjustment.
  • Said download deactivates/activates the ClE signal if a downloaded value is (bigger than 1) / (equal to 1) accordingly.
  • the phase 1 control circuit is similarly driven by the C2E and by the LD_C2; and similarly generates the LD Cl, LD REl, LD BUl signals for controlling phase 1 operations.
  • the PCU reads the measured phase errors and uses the RET_CS to introduce digital phase differences between the APD reference input and the APD return input which will drive the VCXO based PLL for providing required phase transfer functions between the f_filter signal and the f_r2 signals. Since the f_filter drives the OUT_PLL which has much higher BW than the VCXO PLL and the OUT PLL determines phase of the F_outl, the F-outl phase will provide the same phase transfer function as the f_filter.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un SOC bon marché mettant en place un système d'horloge d'hétérodyne programmable (HTS) permettant de synthétiser une horloge de sortie avec une résolution de fréquence indéfinie à partir d'horloges de référence à une fréquence quelconque. L'horloge de sortie possède une très faible gigue indépendante de la qualité des horloges de référence alors que la phase de l'horloge de sortie est commandée avec une résolution appariée à des retards de grilles uniques. HTS permet d'effectuer des multiplications de fréquence dans une gamme continue dépassant 50 000, permettant ainsi d'utiliser un oscillateur local au-dessous de 32kHz, aux fins de mise en oeuvre d'une synthèse programmable d'horloges GHz exemptes de transitoire de phase.
PCT/CA2005/000995 2004-06-28 2005-06-28 Systeme d'horloge universel d'heterodyne Ceased WO2006000095A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002471893A CA2471893A1 (fr) 2004-06-28 2004-06-28 Systeme universel de synchronisation heterodyne
CA2,471,893 2004-06-28

Publications (1)

Publication Number Publication Date
WO2006000095A1 true WO2006000095A1 (fr) 2006-01-05

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
WO2004002052A1 (fr) * 2002-06-25 2003-12-31 Bogdan John W Traitement de signaux numeriques a phase multi-echantillonnee
US20050007206A1 (en) * 2001-12-07 2005-01-13 Renaissance Electronics Corporation Surface mountable circulator/isolator and assembly technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
US20050007206A1 (en) * 2001-12-07 2005-01-13 Renaissance Electronics Corporation Surface mountable circulator/isolator and assembly technique
WO2004002052A1 (fr) * 2002-06-25 2003-12-31 Bogdan John W Traitement de signaux numeriques a phase multi-echantillonnee

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CA2471893A1 (fr) 2005-12-28

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