WO2006087792A1 - Encoding apparatus and encoding method - Google Patents

Abstract

For each of K information elements, an encoding is repetitively performed a designated repetition number of times. A partial interleaving of the results of the repetitive encoding is then performed, by use of a different interleave pattern, every plurality of partial interleave blocks. Results of the partial interleaving are then selected from different ones of the partial interleave blocks and added together by a designated size of addition blocks. For the addition result, a convolution encoding is performed to output M parity codes. In this way, for codes, such as IRA codes or RA codes, defined by an encoding method using an interleave process, a code sequence to be interleaved is divided and then interleaved, whereby the complexity of interleave pattern generation can be reduced without degrading the characteristic and further the processing amount or time can be reduced in accordance with the division number.

Description

 Encoding apparatus and encoding method

 Technical field

 TECHNICAL FIELD [0001] The present invention relates to an information bit encoding apparatus and encoding method in a digital information communication system and the like, and more particularly, to an IRA (Irregular Repeat Accumulate) code or RA that generates a noble code using interleave processing. The present invention relates to a technique suitable for encoding a low-density parity-check (LDPC) code such as a (Repeat Accumulate) code.

 Background art

 [0002] (A) Block code

 The block code is K (K is a positive integer) information alphabet u = (u,

 ο

, U) to KXN (N is a positive integer) generator matrix G = (g) (i = 0, ···, K-l; j = 0, ···,

K-l ij

 Ν- 1) is encoded into code alphabets χ = (X, ···, X). That is, the sign

 0 K-1

 The alphabet X is expressed by the following formula (1.1).

[0003] x = uG --- (1.1)

 On the receiving side, the received data force information vector u for the code vector X is estimated. For this purpose, the parity check relational expression shown below for the code vector X is used.

xH ^T = 0 --- (1.2)

Here, H = (h) [i = 0, ···, M-1 (M is a positive integer); j = 0, ···, N–1] is a parity check matrix (hereinafter simply referred to as in that "the check matrix"), H ^T means swapped e) matrix transpose (the rows and columns of the check matrix H. From the above formulas (1.1) and (1.2), H and G satisfy the following formula (1.3)

[0004] GH ^T = 0 --- (1.3)

 From this equation (1.3), if either the check matrix H or the generator matrix G is given, the sign rule is uniquely determined.

(B) LDPC code A low density parity check (LDPC) code is a generic name of a code defined by a check matrix in which the number of elements different from 0 is less than the total number of elements in a block code. In particular, when the number of elements in each row and column is constant, it is called a “regular LDPC code” and is characterized by the code length N and the number of weights (w, w) for each column and row. On the other hand, the type that allows different number of weights in each column and each row is called “irregular LDPC code”, and the code length N and the weight distribution of columns and rows [(e, p); j = l, · ..., j; k = l, ..., k]

 j k max max Characterized. Here, λ (ρ) represents the ratio of elements different from 0 belonging to the column (row) of the number of weights j. Regular LDPC codes can be regarded as a special case of irregular LDPC codes.

 [0005] In both regular and irregular cases, a specific parity check matrix is not determined only by determining the code length and weight number distribution. Since there are many possibilities for the arrangement of elements different from 0 that specifically satisfy the specified number of weights, each of these defines a different code.

 Therefore, the error rate characteristics of the codes given as described above are determined by the weight number distribution and the specific arrangement method of elements different from 0 under the conditions.

[0006] On the other hand, characteristics such as the circuit scale, processing time, and processing amount of the encoder and decoder are basically affected only by the distribution of the number of weights.

A general LDPC code is defined by a parity check matrix used in the decoding process, and the sign key processing has a power to obtain a generator matrix from the parity check matrix, and a method of sequentially obtaining parity bits using a triangulated parity check matrix. In any case, O (N ² ) processing time is required.

[0007] (C) Tanner graph

 The LDPC code is decoded using the check matrix defined by the Sum-Product method (Sum-Product Algorithm). Tanner graph is used as a useful graph to understand this method. In the Tanner graph, for example, as shown in FIG. 16, each column of the check matrix H is associated with each “variable node” X indicated by a circle mark in the lower row, and each “check node” s indicated by a row mark in the upper row. Correspondingly, when the component of i row and j column of parity check matrix H is different from 0 (h ≠ 0)

, A graph constructed by connecting a variable node X and a check node S with a line (edge). For example, taking the first row of the parity check matrix H shown in Fig. 16 as an example, the first, second, third, and fourth columns are the same. Since this is a value 1 different from 0, check column s corresponding to the first row of parity check matrix H and each column

 0 corresponding variable nodes X, X, X, X

 0 1 2 3) are connected by a line.

 In the decoding process, the variable node X indicates the state of each code bit (probability for possible bit values), and the check node s is a variable node directly connected to the edge by an edge. This means that the result is 0 when added by the S-parity relational expression. Focusing on one variable of the NORITY check relational expression and using the remaining variables as preconditions for estimating the bits of this variable, paying attention to the probabilities of each current bit The probability that each variable node takes the value of each bit can be estimated. This operation can be graphically interpreted on the graph as the reliability information propagates through the current state force edge of each variable node.

[0009] (D) IRA code

 An example of an IRA code encoder is shown in FIG. As shown in FIG. 15, in the IRA encoder, each of the K information bits input is repeated a specified number of repetitions, and the encoder 101 repeats the code, and E (E is positive). A bit string). The distribution function of the number of iterations is given by f, and each may be generally different. That is, the repetition encoder (variable number of times bit repetition unit) 101 has a distribution function f (j = l,..., J) as shown in FIG.

 Copy each of the input information bits (u, u, ···, u) by the number of iterations (= q, q, ···, q) specified for each bit to satisfy j max.

 0 1 K-1 0 1 K-1

 The designated number of times copy circuit 1010 and a parallel Z-serial (PZS) conversion circuit 1011 for converting the parallel output of the designated number of times copy circuit 1010 into a serial signal and outputting it are configured. Note that the relationship between f and (q, q, ..., q) is repeated q times out of K input bits j 0 1 K-1

 This means that there is only a “ratio” of the number of bits. In other words, it means that, among q 0 1 K−1 of (q 1, q 2,..., Q 1), N lnt (K−f) pieces are equal to each other and given a value.

[0010] Then, this bit string is interleaved by the interleaver 102 and the order is replaced, and the obtained bit string is added every a number (a is a positive integer) from the top by the adding circuit 103. That is, while holding the addition result of the previous adder 131 in the latch 132, the previous addition result is cumulatively added to the current input value, and the switch 133 is closed (ON) according to the addition timing of each a. By controlling this, M code bit strings are output. [0011] The result of addition is further accumulated M times by M times of cumulative addition circuit 104 (adder 141 and latch 142), and the result of addition at each timing is output as a sequence of M code bits (parity bits). To do. That is, the bit vector of every addition result is expressed as x = (X, X

 0 1

,..., X) and the sign bit vector is p = (p, p,..., P)

 It will become a relational type (1.4), (1.5).

[0012] p = x --- (1.4)

 0 0

 p = p + x (i = l, ..., M-1) --- (1.5)

 1 i-1 i

 FIG. 17 shows a Tanner graph corresponding to this code. M sign bits (p, p

 0

, ..., P) as parity bits and serially in parallel with K information bits (u, u, ... U)

1 -1 0 1 K-1

 An IRA code that is a systematic code with N (= K + M) bit strings as code bits is a kind of the irregular LDPC code, and its check matrix H is originally triangulated. It can also be interpreted as a code devised so that the conversion processing time is completed in a linear time O (N) proportional to the code length N (for example, see Non-Patent Document 1 below).

[0013] In other words, considering that the value of each variable is bits (because the addition and subtraction results are the same), the above cumulative addition formula is as shown in the following formulas (1.6) and (1.7): Can be transformed into

 p + x = 0 --- (1.6)

 0 0

 p + p + x = 0 (i = l, ..., M-1) --- (1.7)

 1 i-1 i

This is because each x _; is the result of adding a number of input information bits ^, and when this is substituted, the sign bit c = (c, ···, c) = (ιι, ···, u, p,, ..., p)

 0 N-1 0 K-1 0 -1

 It can be interpreted as a relational expression.

 [0014] Due to the characteristics of the code, it is not appropriate to use an interleaver with a simple configuration such as a simple block interleaver. The interleaver is originally designed to be as far away as possible after interleaving the bits in order. It is desirable to arrange in. A perfectly random interleaver is suitable because it allows a uniform probability to place bits in close order in the near V に position even after interleaving.

[0015] Therefore, the S-Random interleaver and its extended version are interleavers that can be randomly generated with the above conditions (hereinafter referred to as "conditional random interleaves"). High Spread Random interleavers (for example, see Non-Patent Document 2 below) are known. In contrast, 3GPP (Third Generation Partnership Project) W-CDMA mobile communication system has been specified as a method that can identify the order of replacement destinations structurally (that is, with a mathematical algorithm) without using pseudorandom numbers. ! /, Prime Interleaver (PIL) adopted as an internal interleaver of the turbo code (hereinafter referred to as “structural random interleaver”. For example, see Non-Patent Document 3 below).

[0016] (E) Code related to IRA code

 (1) When the number of repetitions is fixed (f = 1, f = 0; j ≠ q) and a = l, it becomes an RA code (for example,

 Q j

 Non-patent document 4 described later). In this case, the RA encoder, for example, as shown in FIG. 14, copies each of K information bits by a fixed number of repetitions q, and repeats q times 101a, and an interleaver that interleaves the output. 102a and an M-time cumulative addition unit 104 (adder 141 and latch 142) that outputs the NOT bit by accumulating the output M times.

(2) The size of the IRA code can be changed for each addition block in the addition processing after interleaving. This is referred to herein as an “Extended IRA code” (see, for example, Non-Patent Document 5 below).

 (3) In this extended IRA code, when the number of repetitions is fixed, it is called an “extended RA code”.

 [0018] (4) A convolutional encoder with feedback with a coding rate of 1 can be used by generalizing the cumulative addition process. Such a code is referred to herein as a “general IRA code”. An example of a convolutional encoder with feedback other than cumulative addition is shown in FIG. The convolutional encoder 104a shown in FIG. 13 is composed of four Karo arithmetic units 141, 143, 145, 147 and three latches 142, 144, 146, and the human bit vector is expressed as χ = (χ, χ , ..., x) and

 0 1 M-l and the output bit is parity bit p = (p, p, ..., p), the following equation (1.8)

 0 1 -1

 Satisfying this relational expression.

[0019] X + x + x + p + p + p = 0--(1.8)

 i-3 i-1 i i-3 i-2 i

 However, i = 0, 1,..., M−l, and x = p = 0, i <0.

(5) The above codes are collectively referred to as “general extended IRA codes” in this specification. Most common A typical case is shown in FIG. That is, a variable number of times bit repetition unit 101 having two or more different repetition numbers q _; (for example, see FIG. 11) and a variable number addition unit 103a having two or more different addition sizes a (internal configuration) 12) and the number of blocks to be added MO is different from M and the coding rate is different from 1 (RO = MOZM). Convolutional encoder 104a with feed knock (internal configuration is 13) is used. Note that the variable number adding unit 103a shown in FIG. 12 has different addition block sizes (a, a,

 0 1

At each addition timing of a), the bit -1 held in the latch 132 by the 0 clear circuit 135

 The switch value is cleared to 0, and the switch 133 is controlled to be in the ON state by the switch opening / closing circuit 134, thereby realizing addition processing for each variable addition block size.

However, the conventional code key scheme as described above, particularly the code key scheme of an IRA code which is a kind of LDPC code, has the following problems.

(a) The size of the interleaver used in the IRA code is E = Ma, and a is generally a single digit value. The number of S parity bits M is typically a large value of tens of thousands and tens of thousands. Size E is a large value. A large-size conditional random interleaver takes O (E ² ) processing time proportional to E ² to generate, and a constructive random interleaver takes O (E) processing time.

 (B) In order to avoid this, when preparing a mapping table (interleave pattern table) generated in advance, a memory having a size of O (E) proportional to E is required. Thus, when a plurality of formats of codes are used adaptively, each mapping table is required, so the amount of memory is increased accordingly.The present invention was devised in view of such a problem, It is an object of the present invention to provide an encoding apparatus that can reduce the complexity of generating an interleave pattern without degrading the characteristics and reduce the processing amount or processing time.

 Non-Patent Literature 1: H. Jin, A. Khandeker, and R. McEliece, 'irregular repeat-accumulate codes, in Proc. 2nd. Int. Symp. Turbo Codes and Related Topics, Brest France, pp. 1-8, Sept . 2000.

Non-Patent Document 2: H. Crozier, "New High-Spread High-Distance Interleavers for Turbo-Codes ", Proceedings of the 20th Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada, pp. 3-7, May 28-31, 2000.

 Non-Patent Document 3: Third Generation Partnership Project (3GPP), "Multiplexing and Channel Coding (Frequency Division Duplex Mode)", Technical Specification 25.212, V5.9.0 (2004-06).

 Non-Patent Document 4: D. Divsalar, H.Jin, and RJ McEliece, "Coding theorems for 'turbo-like' codes, pp. 201-210 in Proc. 36th Allerton Conf. On Communication, Control, and Computing. (Allerton , Illinois, Sept. 1998).

 Non-Patent Document 5: M. Yang, WE Ryan, and Y. Li, "Design of Efficiently Encodable Moderate-Length High-Rate Irregular LDPC Codes," IEEE Trans, on Commun. Vol. 52 no. 4, pp.564- 571. Apr. 2004.

 Disclosure of the invention

 [0022] In order to achieve the above object, the encoding device of the present invention includes:

 (1) An apparatus for generating M null codes from K information elements using interleaving, and generating a code of size Ν = Κ + Μ using the information elements and the parity code, A repetitive coding unit that performs repetitive coding for a specified number of repetitions for each of the information elements, and a repetitive coding result obtained by the repetitive coding unit with partial interleaving in a different interleave pattern for each of a plurality of partial interleave blocks An interleaving processing unit, an adding unit that selects and adds partial interleaved results from the different partial interleaved blocks after the partial interleaving for each addition block of a specified size, and a convolutional code sign for the addition result by the adding unit. And a convolutional coder that outputs the number of parity codes. It is a feature that was withered.

 [0023] (2) Here, the number of the result of the repetition code 匕 is obtained, and the designated size of the i-th addition block in the addition unit is a (i = 0, ···, M-1) , The maximum size of the addition block is a

 1 max number of parity codes When a positive integer less than or equal to M is M (1 = 0, ..., a-1),

 1 max

 The servo processing unit has the partial interleave block max of each size a satisfying the following formula (4.1):

Each partial interleave is configured to perform the partial interleaving. It may be configured to select and add the partial interleaving results one by one from the beginning of each partial interleave block after the partial interleaving by the specified size & i of the addition block!

 [0024] [Equation 1]

 1

 E = J M, .---(4.1)

(3) Further, the interleaving processing unit is common to the partial interleave blocks, and includes a common partial interleaver that sequentially performs the partial interleaving on the partial interleave blocks. The adding unit may be configured to sequentially add the results of sequential partial interleaving by the common partial interleaver.

 (4) Furthermore, the specified size a may be constant.

 [0026] (5) In addition, when the repetitive coding result belongs to the first and second partial interleave blocks in mO and ml pieces, the above-mentioned first partial interleave block By avoiding the position determined by the mO repetition code result by partial interleaving, the relative position in the second partial interleave block of the ml repetition encoding result is determined, and The interleave processing force

The above-mentioned partial interleaving block except the above ml pieces may be configured to be subjected to the partial interleaving for the remaining repetition code results.

[0027] (6) Further, the iterative coding unit may perform the iterative code result so that the repetition codes for the number of repetitions for each of the K information elements belong to different partial interleave blocks. May be configured to be output to the interleave processing unit.

 (7) In this case, when E is the number of repetition code keys, the number of repetitions in the repetition code field is q (i = 0, ..., Kl), and the maximum value is q And the repetitive encoding unit

 1 max

 Indicates that the repetition code is divided into q blocks and each block size is distributed so that the repetition code is distributed to the different partially interleaved blocks.

 max

 Is a positive integer K less than or equal to K (i = 0, ···, q 1) that satisfies the following equation (4.2)

 1 max

Configured to output to the interleave processing unit in units, and the interleave processing The management unit should be configured to perform partial interleaving of size κ _; for each of the above blocks.

 [0028] [Equation 2]

E = ^ K,-(4.2)

[0029] (8) The q may be constant! /.

 (9) Furthermore, when the result of the repetition code included in the addition block belongs to the first and second partial interleave blocks in kO and kl, respectively, the kO repetition code Avoiding the position determined by the partial interleaving for the result, the relative position in the second partial interleave block to which the kl repetitive coding results belong is determined, and the interleaving processing power It is also possible to perform the partial interleaving on the result of the remaining repetitive codes excluding the above-mentioned kl interleave blocks.

 [0030] (10) In addition, the interleave processing unit includes a memory that holds the repetitive encoding result belonging to the partial interleave block in a predetermined write order, and a read order different from the write order according to the interleave pattern. A read control unit that performs the partial interleaving by reading the result of the repetitive code, and an interleave pattern control unit that generates a different interleave pattern for each of the different partial interleave blocks held in the memory and supplies the interleave pattern to the read control unit Please prepare.

 [0031] (11) Further, the interleave pattern control unit generates the different interleave pattern by performing a predetermined replacement process on the interleave pattern used by the read control unit for another different partial interleave block. It is possible to have an interleave pattern replacement generation unit.

(12) Further, according to the code method of the present invention, M parity codes are generated from K information elements by using an interleaving process, and a code of size N = K + M is generated by the information elements and the parity codes. For each of the K information elements, a repetitive coding process for performing a repetitive coding process for a specified number of repetitions, and the repetition code. The partial interleaving process in which the interleaved result is partially interleaved with a different interleaving pattern for each of the plurality of partial interleaved blocks, and the partial interleaved result is selected from the different partial interleaved blocks for each additional block of the specified size. It is characterized by having an addition process of adding, and a convolutional encoding process of outputting M parity codes by performing convolutional coding according to the addition result.

 [0032] (13) Here, in the partial interleaving process, the partial interleaving is sequentially performed on the partial interleaving blocks, and the sequential partial interleaving result is sequentially performed in the adding process. May be added.

 According to the present invention, the following effects and advantages can be obtained.

 (a) Complexity of interleave pattern generation without degrading characteristics by dividing the interleaver in codes defined by coding methods using random interleave processing such as IRA codes and RA codes The processing amount or processing time can be reduced according to the number of divisions.

[0033] (b) A memory that holds a read index of an interleaved result by sequentially applying l partial interleavers to a plurality of partial interleaved blocks and simultaneously performing bit addition at each stage. Can be shared by each partially interleaved block, and the memory size can be greatly reduced compared to when interleaving is applied to large (E) bits at once.

 Brief Description of Drawings

 FIG. 1 is a block diagram showing a main configuration of an IRA encoder (encoder device) as a first embodiment of the present invention.

 2 is a block diagram showing a configuration example of an interleave processing unit and an adding unit shown in FIG.

FIG. 3 is a Tanner graph in the IRA encoder shown in FIG.

 FIG. 4 is a Tanner graph of an IRA encoder according to a modification of the first embodiment.

FIG. 5 is a block diagram showing a main configuration of an RA encoder (encoder device) as a second embodiment of the present invention. 6 is a block diagram showing a configuration example of an interleave processing unit and an addition unit shown in FIG.

FIG. 7 is a Tanner graph in the RA encoder shown in FIG.

 FIG. 8 is a Tanner graph in an RA encoder according to a modification of the second embodiment.

 FIG. 9 is a block diagram showing a configuration example of an interleave pattern control unit for explaining the interleave pattern generation processing in the first embodiment.

 FIG. 10 is a block diagram showing a configuration example of a conventional general-purpose extended IRA encoder.

 FIG. 11 is a block diagram showing an example of the internal configuration of the repetition encoder (variable number of times bit repetition unit) shown in FIGS. 10 and 15.

 12 is a block diagram illustrating an internal configuration example of a variable number adding unit illustrated in FIG.

 FIG. 13 is a block diagram showing an example of the internal configuration of the convolutional encoder with feedback shown in FIG.

 FIG. 14 is a block diagram showing a configuration example of a conventional RA encoder.

 FIG. 15 is a block diagram showing a configuration example of a conventional IRA encoder.

 FIG. 16 is a diagram for explaining a Tanner graph.

 FIG. 17 is a Tanner graph of an IRA code.

 BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

 [A] Description of the first embodiment

 FIG. 1 is a block diagram showing the main configuration of an IRA encoder (encoder) as a first embodiment of the present invention. The IRA encoder 1 shown in FIG. 1 has K pieces (K is a positive integer). ) M bits (M is a positive integer) from the information bits, and the code bits of size N (= K + M) are generated together with the K information bits. (Variable number of times bit repeater) 2, serial Z parallel (SZP) converter 3, a (a is a positive integer) partial interleaver (0th to a-1 interlino) 4 0— 4 ( It has an interleave processing unit 4, a parallel Z-serial conversion unit 5, an addition unit (a-time addition unit) 6 and an M-time cumulative addition unit 7 having a-1).

[0036] Here, the variable number of times bit repetition unit 2 performs each of K input information bits (information elements). At this time, it generates a repetition code (bit) for the specified number of repetitions (variable) and outputs E repetition codes (E is a positive integer) as a result. For example, j ( The number of bits N (j = l, ···, j) that generate repeated bits of j is a positive integer) is a distribution function (number of times

 j max

 (Also called cloth) f (j = l, ···, j) force is given by N = Int (K'f). However, the following (2.1)

 j max j j

 And adjust each to satisfy Eq. (2.2).

[0037] [Equation 3] N _; = K--(2.1)

[0038] [Equation 4]

^; N. = Ε = Μα-(2.2)

[0039] At this time, the variable number of times bit repetition unit 2 uses (j, ···, j) as a combination of j combinations in which Ν is different from 0 in ascending order, and the first Ν (c = j) Repeat bit times, the next Ν (t = j

 0 F-l c 0 0 t 1

) Pieces = j

 Repeat one, and then j

 Continue to F-1 max. The bits obtained in this way are arranged serially to be output bits of the repetition code. This function includes, for example, a specified number of times copy circuit that copies each information bit input as described above with reference to FIG. 1 by the number of repetitions specified by the distribution function f and outputs it in parallel. This can be realized by using a PZS conversion circuit that serializes the output.

[0040] The SZP conversion unit 3 performs parallel conversion on the serial output (E repetition codes) obtained by the variable number of times bit repetition unit 2 and outputs it in units of M blocks (partially interleaved blocks). To do.

The interleave processing unit 4 performs partial interleaving on the result of the above repetitive coding with a different interleaving pattern for each of the a partial interleaving blocks. For this purpose, each partial interleaver 4 i (i = 0, ... , a-1), the M repeated codes of the partial interleave block input from the SZP conversion unit 3 are interleaved according to different interleave patterns (replacement patterns). For each partial interleaver — i, for example, a conditional random interleaver such as the S-Random interleaver described above or its extended version, the High Spread Random interleaver, is used. Apply. However, it is also possible to apply a structured random interleaver such as PIL described above. Note that an interleave pattern that differs for each partial interleaver 4 i can be obtained, for example, by changing the seed of the pseudo-random function, details of which will be described later.

 [0041] The PZS converter 5 converts the output of each partial interleaver 4 i into serial data and outputs E bits (interleave result). The a-time adder 6 outputs the output result. A is added, that is, a is added in order of the leading force of the partial interleave result for each partial interleave block by each partial interleaver 4 i. More specifically, if the j-th read index (original bit position) of the i-th partial interleaver 4 i is r, the river page r, r,..., R, r, r '… Cara one by one in Silanole

 i, j 0,0 1,0 a- 1,0 0,1 1,1

 Arithmetic generates M bits! /

 [0042] For this reason, the a-time adder 6 includes an adder 61, a latch 62, and a switch 63, and the addition result obtained by the previous adder 61 held in the latch 62 is added to the current input. Cumulative addition is performed by adding at 61, and when the addition is completed a times, the switch 63 is turned on to output the addition result a times. However, to perform this addition process a times, in this embodiment, in order to avoid temporarily storing E read indexes, a partial interleavers 4 i are sequentially added one by one (in time division). When executed, the memory for temporarily storing M read indexes is shared and used.

 That is, for example, as shown in FIG. 2, the partial interleaver 4 i includes a write switch 40, a repeated code temporary storage memory 41, a read relative position memory 42, an interleave pattern generation unit 43, and a timing counter 44. The a-time addition unit 6 includes M sets of adders 61, latches 62, and switches 63 in parallel, and also includes a P / S conversion unit 64.

Here, the write switch 40 is used to turn ON / OFF the writing of the repeated code to the repeated code temporary storage memory 41. The repeated code temporary storage memory 41 is turned on by the write switch 40 being turned ON. It holds M repetition codes (that is, repetition codes belonging to one partial interleave block), and the read relative position memory (read control unit) 42 is supplied from the interleave pattern generation unit 43. According to the given interleave pattern, the repetition code addresses (read indexes) to be read from the repetition code temporary storage memory 41 are sequentially specified for M times, so that the repetition codes are written in an order different from the order of writing to the memory 41. Is read and partial interleaving is performed on M repetition codes.

 [0045] The interleave pattern generation unit 43 reads a different interleave pattern for each update timing given from the timing counter 44 and gives it to the relative position memory 42 to change the reading order. The timing counter 44 The write (update) timing to the repeated code temporary storage memory 41 and the update timing of different interleave patterns in the interleave pattern generation unit 43 are output a times respectively, so that the next partial interleave after the above read out The M repeated codes belonging to the block are written into the repeated code temporary storage memory 41, and different interleave patterns for the partial interleave block are given to the read relative position memory 42. To the part inter one leave is completed for Buburokku sequentially contents of the repetition code temporary storage memory 41 and reading the relative position memory 42 is adapted to be updated.

 That is, the interleave pattern generation unit 43 and the timing counter 44 generate an interleave pattern different for each different partial interleave block and give it to the read relative position memory 42 as the read control unit. In FIG. 1, each of the partial interleavers 4 i is provided in parallel, and the partial interleaving is performed in parallel at the same time (of course, a powerful configuration is possible). In Fig. 2, the same processing is realized by using a configuration in which the interleaving << (common partial interleaving) 4a common to each partial interleaved block is used and the block subject to partial interleaving is changed sequentially. It is.

[0047] On the other hand, each of the M adders 61 is one of the M bits read from the repeated code temporary storage memory 41 and the bit held in the corresponding latch 62 (previous addition result). Each of the M latches 62 temporarily holds the addition result of the corresponding adder 61 and feeds back the bit to the adder 61. Repeater code temporary storage memory by adder 61 and latch 62 M bits written to a total of 41 times and read a total number of times from the corresponding memory 41, that is, the partial interleave results of a partial interleaved blocks are sequentially accumulated by the calorie calculator 61 and the latch 62, respectively. It ’s going to be done.

 [0048] Each of the M switches 63 is controlled to be in the ON state at the timing when the addition of a times is completed, so that the bit value (that is, the result of addition of a times) held in the latch 62 at that time is controlled. The PZS converter 64 outputs the result to the PZS converter 64. The PZS converter 64 serially converts and outputs the M a-time addition results thus input.

 With the above configuration, for example, for the first partial interleaved block, a block that holds M addition results in the order of the memory addresses of the read relative position memory 42 Addition result temporary storage memory (M latches 62) Then, the bit value is written to the second partial interleaved block, and then the partial interleaving read Wenda for the second partial interleaved block is obtained from the new interleave pattern, the contents of the read relative position memory 42 are updated, and the address In order, for the bit (previous addition result) of the same address (corresponding to the position of the latch 62) held in the block addition result temporary storage memory 60 (M latches 62), the above in the repeated code temporary storage memory 41 The read index bits are added by the corresponding adder 61. Thereafter, similarly, M bits are added up to the last (a-th) partial interleave block, and each switch 63 is controlled to be ON when each calorie calculator 61 completes the a-calorie calculation. Then, the M a-time addition results are serially converted by the PZS converter 64 and output.

 That is, one partial interleaver 4a is sequentially applied to each of the a partial interleave blocks, and bit addition is performed simultaneously at each stage. In this way, the read relative position memory 42 can be shared with each partial interleave block.

Next, the M-times cumulative adder 7 performs M cumulative additions on the output of the a-time adder 6 and outputs M parity bits. For this purpose, the adder 71 and the latch 7 2 The previous addition result held in the latch 72 is feed-knocked to the adder 71 and added to the current input (a-th addition result) by the adder 71. . For example, M block of a block addition result temporary storage memory 60 is added in the order of addresses a times. Assuming that the result is x = (x, ..., x), the cumulative addition shown in the following equations (2.3) and (2.4)

0 -1

 By doing this, we find ノ NORITTY bits ρ = (ρ, ···, ρ). However, the following

 0 -1

 In Eq. (2.4), i == l, ..., M−1.

 [0050] p = χ · '· (2 · 3)

 ο ο

 ρ = ρ + χ ー (2.4)

 i i-1 i

 Then, the obtained M norm bits p = (p,..., Ρ) are converted into 情報 information bits u = (u,

 0 M-1 0

···, u)) and serially combined, system-coded as shown in equation (2.5) below

K-1

 Sign bit C is obtained.

 [0051] c = (c, ···, c) = (ιι, ···, u, p, ···, p) --- (2.5)

 0 N-1 0 K-1 0 M-1

 Figure 3 shows the Tanner graph in this example. As shown in Fig. 3, the variable node (u, ··, u) force indicated by a circle at the bottom is also M for each partial interleaver 4 0— 4 (a— 1).

 0 K-1

 Each edge is drawn, and E repetition codes are divided into a blocks (partial interleave blocks) of M pieces each and input to each partial interleaver 4 i. Each check node (s,..., S) force indicated by

 0 -1

 A total of a edges are bowed I, and each partial interleano—partial interleaving of i indicates that a total of a bits are selected and collected (added) one by one, each check Node (s, ..., s) and variable nodes corresponding to the NORITY bits (p, ..., p)

 0 -1 0 -1

 The above-mentioned M cumulative additions are represented by connecting the edges in a zigzag pattern to the (topmost circle).

 [0052] As described above, according to the IRA encoder 1 of the present embodiment, the E repetition codes that are the output of the variable number of times bit repetition unit 2 are divided into M blocks each of which is M pieces, and each block ( Apply partial interleaving of different interleaving patterns to M bits), select a total of a bit one by one in the order of the leading force of each result, add (a addition), and then the addition result Since the parity bit is generated by accumulating M times M times, the following effects or advantages can be obtained.

[0053] (1) One partial interleaver (conditional random interleaver) Even if the processing time required for processing at 4 i is set to 0 (M ² ) and this is performed sequentially as described above, LZa time is shortened compared to interleaving without splitting. (2) If the above-mentioned structural random interleaver is applied to the partial interleaver 4-i, the processing time will not change if sequential partial interleaving is performed as described above, but the partial interleaver will not change. If each of 4-i is processed in parallel, the processing time can be lZa. Further, if to parallel processing, rather than sequentially in each part interleaver 4 (random interpolymer rie server conditional), it is possible to shorten further the processing time LZA ^2.

 [0054] (3) One partial interleaver 4 i (4a) is sequentially applied to each a block, and bit addition is performed simultaneously at each stage, thereby reading the interleaved result reading status Can be shared by each partially interleaved block, and the memory size can be reduced to lZa compared to the case where interleaving is applied to a large size (E) bits at a time.

 It should be noted that the above addition block size (a) may be more generalized and variable (a: i = 0,..., M−l). In this case, it is an “extended IRA code”. That is, the size of the i-th addition block of variable addition processing is a, the maximum addition block size is a, and the number of parity codes is less than M

 1 max

 When the positive integer of M is M (1 = 0, ···, a –1), the interleave processing unit 4 performs the following (1

 1 max

 ) Max for partial interleaved blocks of each size a satisfying the formula

 Then, the adder 6 selects and adds partial interleave results one by one from the beginning of each partial interleave block after partial interleaving for the specified size a of each addition block.

[0056] Further, in general terms, a convolutional encoder with feedback may be used for the M-time cumulative addition unit 7. In this case, it becomes a “general 匕 extended IRA code”.

 (A1) Description of modification of first embodiment

In the example described above, the following problem may occur when a repeated code spans two partially interleaved blocks. That is, with a method of applying an interleaver (whether a random interleaver, conditional random interleaver or structural random interleaver in the above example) unconditionally to a bit string of size E, the result of repeated information bits Bits of the same value belong to the same block after interleaving (this is called block duplication), and the information will cancel each other out. [0057] In the Tanner graph, this corresponds to connecting the same variable node and check node pair with an edge twice, which is different from the code intended as the LDPC code. . Here, the “intended code” is defined by the parameter (f, a) (j = 2, ..., j).

 j max

 It is an irregular LDPC code defined by a parity check matrix that determines the site distribution.

[0058] Even if a slight deviation from the intended code is allowed, for example, if a double edge occurs in an information bit that has been repeatedly coded 2 to 3 times, it becomes equivalent to an edge of 0 to 1. This is an inappropriate code. When it is 0, the information bit has no relation to the soft decision code. In the case of 1, since the reliability information obtained from the nodes connected by the edge can only be returned as it is, the soft decision effect cannot be given to other bits.

 [0059] For example, in the first embodiment described above (Fig. 2), when a bit string of repetition codes for input information bits is serially arranged and divided into a partial interleaved blocks by M pieces, a certain information bit is obtained. The repetition code of may belong to two partially interleaved blocks. Here, assuming that each information bit u repeats j times, mO (mO is a positive integer) belongs to the first partial interleave block, and the remaining ml = (j—mO) (ml is a positive integer) Belongs to the second partial interleave block.

 [0060] In this case, when partial interleaving of size M is performed on the first partial interleaving block, the read position (relative index) for the mO bit strings is determined, so this read position is stored. Keep it. Then, before executing the partial interleaving for the second partial interleave block, for the ml repeated codes of the first information bit u, avoid the read position for the mO bit strings stored earlier, and A relative read position in the block is determined in advance by a predetermined method (for example, randomly), and partial interleaving is performed on the remaining (M-ml) bit strings excluding the ml. The same processing is performed for the third and subsequent partially interleaved blocks.

[0061] As a result, as shown in FIG. 4, for example, in the Tanner graph of the resulting code, it is possible to avoid that the same node pair is double-connected by an edge (that is, block overlap). 80)) As a result, the generation of “unintentional codes” is avoided and characteristic deterioration is avoided. can do.

 [B] Description of the second embodiment

 FIG. 5 is a block diagram showing the main configuration of an RA encoder (encoder) as a second embodiment of the present invention. The RA encoder 1A shown in FIG. Bit force Generates M parity bits and generates code bits of size N = K + M together with K information bits. For example, repetitive encoder (q-bit repetitive part) 2A, serial Z parallel (SZP) conversion unit 3A, q partial interleavers (0th-q-1 interleaver) 4A— 0— 4A— (q— 1) interleave processing unit 4A, parallel Z serial (PZS) ) A conversion unit 5A, a variable addition unit 6A, an M accumulation addition unit 7 and a variable addition control unit 8 are provided.

[0062] Here, the q-bit repetition unit 2A repeatedly codes all the K input information bits by a fixed number (specified number of repetitions) q (q is a positive integer), SZP The conversion unit 3A performs an SZP conversion on the output of the q-bit repetition unit 2A and outputs it in q blocks of q sets. Specifically, each of the repetition bits is sequentially separated. It is arranged sequentially in the block of bits. That is, q copies of K information bits are generated and input to the partial interleaver 4A-t (t = 0,..., Q-1).

[0063] The interleave processing unit 4A performs partial interleaving on the result of the repetitive code by the q-bit repetition unit 2A with a different interleaving pattern for each of q partial interleave blocks. By 4A-t, the K information bits are subjected to partial interleaving of size K (random interleaving, conditional random interleaving, or structural random interleaving).

[0064] The PZS conversion unit 5A serially converts the output of the partial interleaver 4A-t (interleave result) and outputs the result. The variable addition unit 6A specifies (variable) the interleave result. Addition number (addition block size) a (i = 0, ..., M-1) Accumulated addition is performed. Adder 61, latch 62, and switch 63 are provided, and addition block size a is added. Each time, the bit held in the latch 62 by the 0 clear circuit 81 The value is cleared to 0, and the switch 63 is controlled to be in the ON state by the switch opening / closing circuit 82, so that an addition process for each variable addition block size a _; can be realized.

 [0065] However, in order to perform this variable number of times addition processing, in the present embodiment as well, K partial interleavers 4A-t are sequentially executed one by one (in time division), so that K read indexes are obtained. Share the memory for temporary storage.

 That is, for example, as shown in FIG. 6, the partial interleaver 4A-k includes a repetitive code temporary storage memory 41A, a read relative position memory 42A, an interleave pattern generation unit 43A, and a timing counter 44A. 6A includes an adder 61A for each addition block in parallel, and an adder 61B, a latch (remaining bit temporary memory) 65, and a PZS conversion unit 64.

 Here, the iterative code temporary storage memory 41A holds information bits (u—u) which are K repetition code key results, and the read relative position memory 42A is an interleaved memory.

0 K-1

 Write to the memory 41A by sequentially specifying K addresses (reading indexes) of information bits (repetition codes) to be read from the repetitive code temporary storage memory 41A according to the interleave pattern given from the subpattern generation unit 43A. It reads out repeated codes in an order different from the order, and executes partial interleaving for K repeated codes.

 [0067] The interleave pattern generation unit 43A changes the read order by giving a different interleave pattern to the read relative position memory 42A for each timing given from the timing counter 44A, and the timing counter 44A has an interleave pattern. The output timing of the different interleave patterns in the generation unit 44A is output q times.From this, different interleave patterns for the next partial interleave block are given to the read relative position memory 42A, and so on. The contents of the read relative position memory 42A are sequentially updated until partial interleaving for all (q sets) partial interleave blocks is completed.

That is, in FIG. 5, as the interleave processing unit 4A, partial interleavers 4A-t are provided in parallel, and partial interleaving is performed in parallel at the same time ( Of course, it is possible to use a powerful structure.) In Figure 6, a common interleaver (common partial interleaver) 4b is used for each partial interleave block, and the block to be partially interleaved is changed sequentially. Thus, equivalent processing is realized. In this example, q sets of K information bits are generated to generate q sets of partial interleave blocks. Therefore, K information bits are stored in the temporary code temporary memory 41A. If the data is written only once, partial interleaving is performed q times sequentially using the K information bits continuously. In other words, the repetition code temporary memory 41A functions as the q-bit repetition unit 2A and the SZP conversion unit 3A shown in FIG.

[0069] On the other hand, each adder 61A corresponds to the addition block, and is specified by the read relative position memory 42A from the repeated code temporary memory 41A in the process of partial interleaving executed q times sequentially. Information bits (repeated codes) that should be read according to the addresses to be read (that is, different interleave patterns) and belong to the same addition block are added.

 [0070] Adder 61B performs addition on the remaining bits (kO) generated by dividing E (= q XK) information bits into the above addition blocks, and latch 65 The result is temporarily held, and the addition result finally corresponds to, for example, an addition block of size (a−kO) excluding kO extra bits (located at the top in FIG. 6). An adder 61 is added together with the other (a -kO) information bits in 1A. The PZS converter 64 serially converts the addition result from each adder 61A and outputs M bits.

 However, in this example, since the number E of edges is divisible by K, it can be strictly divided into q sets of bits for every K pieces. At this point there is no “remainder” in the bit. The remaining kO bits are that the output after interleaving is added to the specified number of added blocks (a,

 Therefore, when adding for each block, it means that the set of bits to be added straddles the first interleaver and the second interleaver.

That is, in this example, the adder 61A and the adder 61B function as the adder 61 shown in FIG. 5, and the latch 65 and the repeated code temporary storage memory 41A are latched as shown in FIG. 62 as a timing counter 44A, interleave pattern generation unit 43A, and read relative position memory 42A. As switch 63 and variable addition control unit 8 (0 clear circuit 81, switch open / close circuit 82) shown in FIG. Will fulfill the function.

That is, the number of addition blocks V (k = l,..., K) taking k addition numbers is the distribution function g (k k max k

= 1,..., K) and V = Int (M'g). However, the following (3.1) max k k

 And adjust each V to satisfy Eq. (3.2).

 k

[0074] [Equation 5]

[0075] [Equation 6]

 [0076] At this time, a combination of k with different V from 0 is arranged in ascending order (k, ···, k), and k 0 Gl repeats the first V (x = k) bits k times , Repeat next V (y = k) k times,

 0 0 1 1

 Continue until k = k.

 G ~ l max

 The M-time cumulative addition unit 7 is the same as that described above in the first embodiment, and performs M cumulative additions on the output of the variable-time addition unit 6A to output M NORITY bits. In this example as well, the previous addition result held in the latch 72 is fed back to the adder 71 and added to the current input (a-time addition result) by the adder 71.

That is, assuming that the addition result is x = (X,..., X), the following (3.3) and (3.4)

 0 -1

 Accumulated addition is performed as shown in the equation to obtain the NORITY bits p = (P,..., P).

 0 -1

 p = χ '(3/3)

 0 0

 p = p + x (i = l,…, Μ—1) ··· (3 · 4)

 1 i-1 i

 The obtained parity bit p = (p, ..., p) is serialized with the information bit u = (u, ..., u)

 0 M-1 0 K-l

 By combining, systematic coded code bit c is obtained as shown in the following equation (3.5).

[0078] c = (c, ···, c) = (ιι, ···, u, p, ···, p) --- (3.5)

 0 N-1 0 K-1 0 M-1

Figure 7 shows the Tanner graph in this example. As shown in Fig. 7, Variable nodes shown (u, · · ·, u) forces different partial interleavers 4A— 0— 4A- (

 0 K-1

 One edge is drawn for q-1), and E = qK information bits (repeated codes) are divided into K blocks (partial interleaved blocks) by K and each partial interleaver 4A. — From each check node (s, ···, s) that is represented as t

 0 -1 Each edge of the partial interleaver 4A—t has a bow I, and the partial interleave result of each partial interleaver 4A—t is added for each added block of size a. , Corresponding to each check node (s, ···, s) and the NORITY bit (p, ···, p)

 The above-mentioned cumulative addition of M times is represented by the zigzag edge connection between the variable nodes 0-1 and 0-1.

 [0079] As described above, according to the RA encoder 1A of the present embodiment, the E (= qK) repetition codes, which are the output of the variable number of times bit repetition unit 2A, are divided into q blocks of K units each. Apply partial interleaving of different interleaving patterns to each block (K bits), add bits in units of variable-size a addition blocks according to the interleaving results, and accumulate the addition results M times By adding, a NOTIFY bit is generated, and the same effects or advantages as in the first embodiment can be obtained. That is,

(1) One partial interleaver (conditional random interleaver) If the processing time required for processing at 4A-t is ο (κ ² ) 1 / q time reduction compared to interleaving.

[0080] (2) When the above-described structural random interleaver is applied to the partial interleaver 4A-t, the processing time does not change if sequential partial interleaving is performed as described above. If each interleaver 4A-t is processed in parallel, the processing time can be reduced to lZq. Moreover, if each partial interleaver (conditional random interleaver 4A-t is processed in parallel rather than sequentially, the processing time can be further reduced to 1Z q ² .

[0081] (3) One partial interleaver 4A—t (4b) is sequentially applied to q blocks, and bit addition is performed simultaneously at each stage, so that the read index of the interleave result is obtained. The memory 42A can be shared by each partially interleaved block. Compared to the case where interleaving is applied to a large size (E) bits at a time, The memory size is lZq.

[0082] Note that the number of repetitions q is more general and variable (q.:i = 0, ···, q — 1) (q is the maximum

 l max max large value) (in this case, it becomes an “extended IRA code”). That is, when E information bits (repetition code 匕 result) are E and the number of repetitions is q, the repetitive encoding unit 2A performs repetitive encoding so that the repetitive codes are distributed to different partial interleave blocks. The result is q blocks, and each block size satisfies the following formula (3.6) max

 Interleave processing in block units with positive integer K less than or equal to K (i = 0, ···, q -1)

 1 max

 The data is output to the unit 4A, and the interleave processing unit 4A performs the partial interleaving of size K for each block.

[0083] [Equation 7]

 9

E = ^ K _t · '· (3.6)

[0084] Also in this example, a convolutional encoder with feedback can be used for the loop accumulation adder 7 in general terms. In this case, it becomes a “generalized (extended) IRA code”.

 (B1) Description of modification of second embodiment

 Also in the second embodiment described above, it is assumed that, as in the modification of the first embodiment, the addition block force spans two partial interleave blocks. For example, the kth addition block spans the first partial interleave block and the second partial interleave block, and kO (kO is a positive integer) belongs to the first partial interleave block, and the remaining kl Let the number of bits (kl is a positive integer) belong to the second partial interleave block.

[0085] In such a case, the relative read Lf standing in kO corresponding blocks obtained as a result of the partial interleaving for the first partial interleaved block is stored, and the second Before executing partial interleaving for the partial interleave block, kl relative positions different from the above kO positions are randomly determined to be the first kl read addresses. After this, partial interleaving is applied to the remaining (K kl) bits, and addition is performed in the order of read addresses. The same processing is performed for the third and subsequent partially interleaved blocks. [0086] As a result, even in the above-described RA encoder 1A, as shown in FIG. 8, for example, in the Tanner graph of the resulting code, the same node pair is double-connected by an edge (ie, the block (Refer to reference numeral 90), and as a result, generation of “unintentional code” can be avoided and characteristic deterioration can be avoided.

 [C] Generation method of interleave pattern (read index)

 In the first embodiment described above, when partial interleaving is sequentially performed with a different interleaving pattern for each partial interleave block, as the partial interleaver 4 i applied to the first partial interleave block, for example, the above 3GPP It is assumed that PIL (see Non-Patent Document 3) used in the turbo code is used. On the other hand, the partial interleaver 4 applied to the second and subsequent partial interleave blocks is configured as follows.

 That is, positive integers (offset values) b (i = 1,..., A−1) which are different from each other (M−1) or less are assigned to each partial interleaver 4 i. This number should be greater than the maximum number of repetitions q where possible. For example, as shown in FIG.

 Reads out a different interleave pattern (read index) to the read pattern control unit 46 and performs a predetermined replacement process on the interleave pattern (read index) used for other different partial interleave blocks in the relative position memory 42 An index control unit (interleave pattern replacement generation unit) 45 is added.

 Thus, according to the update timing from the timing counter 44, the read W length control unit 45 sets the relative read index r in the read relative position memory 42 for the j-th partial interleave block. For each read index r for the first (i = 0th) partially interleaved block, the above-mentioned integer b can be obtained by adding (r + b mod M → r) with M modulo .

As a result, the interleave pattern generation unit 43 only needs to give the read relative position memory 42 an interleave pattern only for the first time (for the first partial interleave block), and for the subsequent partial interleave blocks, The read index control unit 45 sets the read index as an offset value as described above. By updating (replacing) with b _;, it becomes possible to apply partial interleaving with different interleaving patterns for each partial interleaving block.

[0090] As described above, for each partial interleave block, a specified number of (mod M) added to one size M interleave pattern is used as a relative read index, so that each partial interleave block is used. Compared to regenerating the necessary interleave pattern for each block, the interleave pattern generation process can be shortened to lZa.

[0091] When a conditional random interleaver is used as the partial interleaver 4 i, a processing amount of 0 (M ² ) is applied to only one partial interleaver 4, and the other partial interleaver 4 i is Since it can be obtained by simple addition and integer division processing, the processing amount is only required to be added to lZa + α.

 Furthermore, even when a structural random interleaver is applied as the partial interleaver 4 i, the amount of processing is reduced when the processing of adding or dividing integers or more is required for the generation of the read word size. In addition, when one type of interleave pattern is determined by one size, this is a method of generating interleavers of the same size but different patterns.

 Further, the above-described interleave pattern generation method can of course be applied to the RA encoder 1 A of the second embodiment.

 As described in detail above, according to the present embodiment, the code sequence to be interleaved is divided in codes defined by the code method using random interleaving such as IRA codes and RA codes. By performing partial interleaving, the complexity of generating an interleave pattern can be reduced without degrading characteristics, and the processing amount or processing time can be reduced according to the number of divisions.

Note that the present invention is not limited to the above-described embodiments and modifications, and it goes without saying that various modifications can be made within the scope without departing from the spirit of the present invention.

 Industrial applicability

[0094] According to the present invention, a code sequence to be interleaved is separated in codes defined by a code method using random interleaving processing such as IRA codes and RA codes. By dividing and partially interleaving, the complexity of generating an interleave pattern can be reduced without degrading the characteristics, and the amount of processing or processing time can be reduced according to the number of divisions. It is considered extremely useful in the field.

Claims

The scope of the claims  [1] K (Κ is a positive integer) information element power is also generated by interleaving to generate パ リ テ ィ (Μ is a positive integer) parity code, and the size of the information element and the parity code Ν = An encoding device that generates a sign of Κ + Μ,  An iterative encoding unit that performs an iterative code for each of the number of information elements for a specified number of repetitions;  An interleaving processing unit for partially interleaving the repeated code key result by the repeated code key unit with a different interleave pattern for each of a plurality of partial interleave blocks;  An adder that selects and adds the partial interleave results for each of the added blocks of the specified size;  An encoder apparatus comprising: a convolutional code key unit that performs convolutional coding on the addition result of the adder unit and outputs the number of parity codes. [2] The number of the result of the repetition code 符号 is を (Ε is a positive integer), and the specified size of the i-th addition block in the addition unit is a (i = 0, ···, M-1) When the maximum size of the addition block is a and the positive integer equal to or less than the parity code number M is M (1 = 0,..., A —1), the max 1 max  Interleaving processing force The partial interleaving max of each size a satisfying the following formula (4.1)  It is configured to perform the partial interleaving for each block,  The adder is configured to select and add the partial interleave results one by one from the beginning of each partial interleave block after the partial interleave, for the specified size a of each addition block. The encoding device according to claim 1, wherein:  [Equation 8]  1  E = J,.-"(4.1) [3] The interleaving processing power is common to each partial interleave block, and the partial interleaving is performed sequentially on each partial interleave block. With a partial interleaver,  3. The encoding device according to claim 1, wherein the adding unit is configured to sequentially add the results of sequential partial interleaving by the common partial interleaver.  [4] The encoding device according to claim 2 or 3, wherein the designated size a is constant.  [5] When the repetitive coding result belongs to the first and second partial interleave blocks divided into mO and ml (mO and ml are both positive integers), the first partial interleave The partial interleaving of the block avoids the position determined by the mO repetitive coding results, and the relative number of the ml repetitive coding results within the second partial interleaving block. The interleave processing unit force is configured to perform the partial interleaving based on the result of the remaining repetitive code excluding the ml blocks of the second interleave block. The encoding device according to any one of claims 1 to 4.  [6] The iterative encoding unit comprises:  The repetition code key result is output to the interleave processing unit so that the repetition codes for the number of repetitions for each of the K information elements belong to different partial interleave blocks, respectively. The encoding device according to claim 1.  [7] E number of repetition code key results, and q (i  = 0,..., Q 1), and when the maximum value is q, the repetitive coding unit  The repetitive encoding result is q blocks so that the return codes are distributed to the different partially interleaved blocks.  (4.2) Satisfy Eq. (1) in block units that are positive integers K or less K (i = 0, ..., q 1)  1 max  Configured to output to the interleave processing unit,  7. The encoding apparatus according to claim 6, wherein the interleaving processing unit is configured to perform partial interleaving of size κ for each block. [Equation 9] E = g K _t- (4.2) [8] The _q; characterized in that it is a constant, the encoding apparatus according to claim 6 or 7. [9] The iterative encoding results included in the addition block are divided into kO and kl (k0 and kl are positive integers) in the first and second partial interleave blocks, respectively. In the second partial interleave block to which the kl repeated coding results belong, avoiding the position determined by the partial interleaving according to the kO repeated coding results. Relative positions are determined, and the interleave processing unit power is configured to perform the partial interleaving on the remaining repetitive code i results excluding the kl pieces of the second interleave block. The encoding device according to claim 7 or 8. [10] The interleave processing unit  A memory for holding the repetitive encoding result belonging to the partial interleave block in a predetermined writing order;  A read control unit that performs the partial interleaving by reading the repetition code key result in a read order different from the write order according to the interleave pattern;  The interleave pattern control unit that generates a different interleave pattern for each of the different partial interleave blocks held in the memory and supplies the interleave pattern to the read control unit is provided. The code | symbol apparatus as described in a term. [11] The interleave pattern control unit  An interleave pattern replacement generation unit configured to generate the different interleave pattern by performing predetermined replacement processing on an interleave pattern used for another different partial interleave block in the read control unit. 10. The encoding device according to 10. [12] An encoding method for generating M parity codes from K information elements using interleaving, and generating a code of size N = K + M using the information elements and the parity codes. An iterative encoding process in which each of the K information elements is iteratively coded for a specified number of iterations;  A partial interleaving process of partially interleaving the repetition code key result with a different interleave pattern for each of the plurality of partial interleave blocks;  Based on the result, an addition process of selecting and adding the partial interleave results for each of the different interleaved blocks from the different partial interleave block cars, and applying the convolutional coding to the addition results. And a convolutional encoding process for outputting the parity code.  In the partial interleaving process, each partial interleave block is sequentially subjected to the partial interleaving,  13. The encoding method according to claim 12, wherein in the addition process, the results of the sequential partial interleaving are sequentially added.