WO2006080056A1 - Semiconductor device and production method therefor - Google Patents

Abstract

To prevent a reduction in on-current of an element caused by a compressive stress acting in an active area. A trench area (3a) formed with a trench width capable of limiting an a compressive stress in an active area (2) is formed in the area in contact with the active area (2) of an element isolation area (3), whereby a compressive stress in the active area (2) is limited and a reduction in on-current of an element formed in the active area (2) is prevented.

Description

 Specification

 Semiconductor device and manufacturing method thereof

 Technical field

 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an element isolation structure by STI and a manufacturing method thereof. Background art

 In recent logic circuits, an element isolation structure using STI (Sallow Trench Isolation) that isolates a MOS (Metal Oxide Semiconductor) transistor in a trench embedded with an insulator is applied. The STI is formed by the following process. First, a nitride film is deposited on a silicon substrate, a resist is applied, and an element isolation region is opened with a photomask. Next, the nitride film and silicon substrate are etched by the RIE (Reactive Ion Etching) method, the surface of the etched silicon substrate is thermally oxidized, and the oxide film is deposited by HDP (High Density Plasma) technology, and then annealed. This densifies the oxide film. Then, the surface is planarized by a CMP (Chemical Mechanical Polishing) method (see, for example, Non-Patent Document 1).

 [0003] In addition, in order to improve the flatness when the insulator is loaded into the STI and the surface is flattened by the CMP method, the STI around the active region is formed deeply and the STI inside is shallowly formed. The structure is disclosed in, for example, Patent Documents 1, 2, 3, and 4.

 Special Reference 1: V. Senez et al., Investigations of stress sensitivity of 0.12 CMOS technology using process modeling ", IEEE IEDM Technical Digest, 2001, p.38.1.1-38.1.4

 Non-Patent Document 2: R. A. Bianchi et al., Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance, lEEE IEDM '02. Digest, 2002, p.117-120

 Patent Document 3: Yukihiro Kumagai et al., "Evaluation of change in drain current due to strain in 0.13- μm-node MOSFETs", Extended Abstract of the 2002

 International Conference on SSDM, 2002, p.14-15

Patent Document 1: JP-A-9-45761 Patent Document 2: JP-A-11-121606

 Patent Document 3: Japanese Patent Laid-Open No. 2000-49221

 Patent Document 4: Japanese Unexamined Patent Publication No. 2000-156402

 Disclosure of the invention

 Problems to be solved by the invention

FIG. 12 is a cross-sectional view of a main part in one process of a semiconductor device having an element isolation structure using a conventional STI.

 In the conventional semiconductor device 50, an STI 52 force S having a depth capable of element isolation, for example, a depth of about 0.3 / im is formed on a silicon substrate 51, and this region becomes an element isolation region. A region sandwiched between the STIs 52 becomes an electrically active region (hereinafter simply referred to as an active region) in which an element such as a MOS transistor is formed. In order to form a MOS transistor, a gate oxide film 53 is further formed on the surface of the silicon substrate 51, and a gate 54 such as polysilicon is formed thereon.

[0005] By the way, during this process, stress acts on the active region due to the expansion of STI52. As a result, it is known that compressive stress is applied to the channel of the MOS transistor, and the characteristics of the MOS transistor fluctuate. For example, if the source and drain are arranged in the (110) direction on a (100) -plane silicon wafer, the on-current of the n-channel type MOS transistor (hereinafter abbreviated as nMOS transistor) due to the compressive stress in the gate length direction. decreases, (hereinafter abbreviated as _P M_〇_S transistor.) p-channel type MOS preparative transistor oN current increases (for example, non-Patent Document 2 see.). In addition, the on-currents of the nMOS transistor and the pMOS transistor decrease due to the compressive stress in the gate width direction (see Non-Patent Document 3, for example). For this reason, the MOS transistor with a narrow gate width increases the average compressive stress in the gate width direction and decreases the on-current.

 [0006] To suppress the current decrease in the MOS transistor, reduce the STI compressive stress in the gate length direction and the gate width direction of the nMOS transistor, and reduce the STI compressive stress in the gate width direction of the pMOS transistor. It is necessary.

[0007] As described above, the conventional semiconductor device has a problem that the on-current is reduced due to the compressive stress acting on the active region due to the expansion of the trench in which the insulator is loaded. Gate width This effect is particularly noticeable for narrow MOS transistors.

[0008] The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device capable of preventing a decrease in on-state current of an element due to compressive stress acting on an active region. Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a reduction in on-current of an element due to compressive stress acting on an active region.

 Means for solving the problem

 In the present invention, in order to solve the above problem, in a semiconductor device in which a plurality of active regions formed on a semiconductor substrate are electrically isolated by an element isolation region by a trench in which an insulator is loaded As shown in FIG. 1, a trench region 3a formed with a trench width capable of suppressing the compressive stress in the active region 2 is provided in a region in contact with the active region 2 in the element isolation region 3. A semiconductor device 1 is provided.

 [0010] According to the above configuration, the active region is provided in the element isolation region 3 in the region in contact with the active region 2 by the trench region 3a formed with a trench width capable of suppressing the compressive stress in the active region 2. The compressive stress in the region 2 is suppressed, and a decrease in the on-current of the element formed in the active region 2 is prevented.

 In addition, the element isolation region 3 is shallower than the trench region 3a and has a depth capable of suppressing parasitic capacitance between the gate 12 and the substrate (silicon substrate 10) when forming the MSO transistor. The parasitic capacitance generated in the element isolation region 3 is suppressed by further including the trench region 3b for suppressing the parasitic capacitance formed by burying.

 In addition, in the method of manufacturing a semiconductor device in which a plurality of active regions formed on a semiconductor substrate are electrically isolated by an element isolation region by a trench in which an insulator is loaded, element isolation to be formed Forming a first trench region having a width capable of suppressing compressive stress in the active region in a region in contact with the active region to be formed, and in the element isolation region, the first isolation region Forming a second trench region having a depth shallower than a depth of the trench region and capable of suppressing a parasitic capacitance between the gate and the substrate when forming the MOS transistor. A method is provided.

[0013] According to the above method, the region in contact with the active region to be formed in the element isolation region to be formed. A first trench region having a width capable of suppressing compressive stress in the active region is formed in the region, and the parasitic capacitance between the gate and the substrate is shallower than the depth of the first trench region in the element isolation region. A second trench region having a depth capable of suppressing the above is formed. This suppresses compressive stress in the active region and prevents a decrease in the on-state current of the MOS transistor formed in the active region. Furthermore, parasitic capacitance in the element isolation region is suppressed.

 The invention's effect

 [0014] According to the present invention, since the trench region formed with a trench width capable of suppressing the compressive stress in the active region is formed in a region in contact with the active region in the element isolation region, the compressive stress in the active region is formed. Is suppressed, and it is possible to prevent a decrease in the on-state current of the element formed in the active region.

 [0015] Further, the element isolation region is shallower than the depth of the trench region formed with a trench width capable of suppressing the compressive stress in the active region, and the parasitic capacitance between the gate and the substrate when the MOS transistor is formed is suppressed. By further including a trench region for suppressing parasitic capacitance formed by embedding an insulator at a possible depth, parasitic capacitance generated in the element isolation region can be prevented.

 [0016] These and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate preferred embodiments by way of example of the present invention. Brief Description of Drawings

 [0017] FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to a first embodiment, illustrating a step in forming a MOS transistor in an active region.

 FIG. 2 is a plan view of the semiconductor device according to the first embodiment.

 FIG. 3 is a graph showing the dependence of compressive stress on STI width and gate width.

 FIG. 4 is a diagram showing a model used for calculation of compressive stress.

 FIG. 5 is a cross-sectional view of a principal part showing a configuration of a semiconductor device capable of suppressing a compressive stress generated in an active region.

 FIG. 6 is a diagram showing the element isolation region width dependence of the compressive stress in the active region in the conventional semiconductor device and the semiconductor device of the first embodiment.

[FIG. 7] In one step of the first manufacturing method for manufacturing the semiconductor device of the first embodiment. FIG. (Part 1)

 FIG. 8 is a fragmentary cross-sectional view of the semiconductor device in one step of the first manufacturing method for manufacturing the semiconductor device of the first embodiment. (Part 2)

 FIG. 9 is a fragmentary cross-sectional view of the semiconductor device in one step of the first manufacturing method for manufacturing the semiconductor device of the first embodiment. (Part 3)

 FIG. 10 is an essential part cross-sectional view of the semiconductor device in one step of the second manufacturing method of manufacturing the semiconductor device of the first embodiment;

 FIG. 11 is a plan view of a semiconductor device according to a second embodiment.

 FIG. 12 is a fragmentary cross-sectional view of one step of a semiconductor device having an element isolation structure using a conventional STI.

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

 FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment, and is a diagram showing a step in forming a MOS transistor in an active region.

 FIG. 2 is a plan view of the semiconductor device according to the first embodiment.

 A part of the cross section taken along line A—A in FIG. 2 corresponds to the configuration in FIG.

 The semiconductor device 1 has a configuration in which a plurality of active regions 2 which are MOS transistor formation regions are electrically isolated by an element isolation region 3 by a trench embedded with an insulator. These are formed on the silicon substrate 10, for example. In addition, a gate insulating film 11 and a gate 12 are formed on the silicon substrate 10 in order to constitute an MOS transistor.

 [0020] The element isolation region 3 includes two trench regions (hereinafter referred to as STI) 3a and 3b formed in the silicon substrate 10. The STI 3a formed in the region in contact with the active region 2 has an STI width (details will be described later) capable of suppressing the compressive stress in the active region 2. Note that the depth of STI3a is the same as that of the conventional semiconductor device 50 (see FIG. 12), and should be deep enough for element isolation. For example, it is about 0.3 μΐη. On the other hand, the other part of the element isolation region 3 is STI3b formed at a depth shallower than the depth of STI3a and capable of suppressing the parasitic capacitance between the gate 12 and the silicon substrate 10, for example, about 50 nm.

[0021] The calculation results of examining the STI width capable of suppressing the compressive stress in the active region 2 are shown below. Figure 3 shows the dependence of compressive stress on STI width and gate width.

 FIG. 4 is a diagram showing a model used for calculation of compressive stress.

Here, the compressive stress in the gate width direction on the surface of the silicon substrate 20 that reduces the on-current is not limited to the nMOS transistor and the pMOS transistor, and this is represented by the vertical axis. The horizontal axis is the position in the gate width direction, with 0 being the center of the gate.

[0023] When STI21 compressive stress is 200 MPa, STI21 depth is 0.3 μm, gate width is 1.0, 3.0, 10 xm, STI width is 0.1, 1. O zm The compressive stress in the gate width direction was calculated. In Fig. 3, the solid line shows the case where the STI width is 1. O zm, and the broken line shows the case where the STI width is 0.1 μm.

 As can be seen from this figure, when the STI width is 1.0 μm, the compressive stress at the center of the gate increases as the gate width is reduced. In other words, when the gate width is reduced, the compressive stress averaged in the gate width direction increases, and the on-currents of the nMOS transistor and the pMOS transistor decrease. On the other hand, when the STI width is 0.1 / m, the increase in compressive stress at the center of the gate is suppressed even if the gate width is narrowed. Therefore, even if the gate width is narrowed, a decrease in on-state current can be suppressed. From the simulation results, it was found that if the STI width is narrowed, the compressive stress generated in the active region by the expanding STI21 can be suppressed.

 [0025] By the way, in general, the STI width cannot be reduced due to layout limitations. Therefore, from the above consideration, the following semiconductor devices can be considered.

 FIG. 5 is a cross-sectional view of the principal part showing the configuration of the semiconductor device capable of suppressing the compressive stress generated in the active region.

 The semiconductor device 30 has a configuration in which a narrow STI 32 is formed only in a region in contact with the active region in the element isolation region formed in the silicon substrate 31. The depth of STI32 is the same as that of the conventional semiconductor device 50 (see FIG. 12), and is, for example, about 0.3 × m. It is desirable that the STI width be constant regardless of the size of the element isolation region and be narrowed to the lower processing limit.

[0027] In the semiconductor device 30 having such a configuration, the STI width is set to the minimum width regardless of the layout, so that the compressive stress in the active region is suppressed and the ON current of the MOS transistor is prevented from decreasing. it can. However, this structure has a problem that the parasitic capacitance 35 between the gate 34 and the silicon substrate 31 in the element isolation region increases due to the influence of the gate insulating film 33 and the gate 34 formed on the silicon substrate 31. .

From the above viewpoint, as shown in FIG. 1, the other part of the element isolation region 3 is shallower than the depth of the STI 3a and the depth at which the parasitic capacitance between the gate 12 and the silicon substrate 10 can be suppressed. For example, by using STI3b formed at about 50 nm, it is possible to suppress the parasitic capacitance 35 as shown in FIG.

 Next, changes in compressive stress in the active region when the element isolation region width of the semiconductor device 1 of the first embodiment is varied will be described. For comparison, the element isolation region width dependency of a conventional semiconductor device 50 as shown in FIG. 12 is also shown.

 FIG. 6 is a diagram showing the element isolation region width dependence of the compressive stress in the active region in the conventional semiconductor device and the semiconductor device of the first embodiment.

 As in Fig. 3, the vertical axis represents the compressive stress in the gate width direction, and the horizontal axis represents the position in the gate width direction. The solid line shows the characteristics of the conventional semiconductor device, and the broken line shows the characteristics of the semiconductor device 1 of the first embodiment fixed at the STI width of 0.Ιμΐη.

 [0031] As a model used for the calculation, parameters were set as follows. The gate width of the semiconductor device 1 of the first embodiment and the conventional semiconductor device 50 shown in FIG. 12 is 1. Ο μ ΐη, the STI width of the STI3a of the semiconductor device 1 is 0 · 1 μm, the depth of the STI3a The depth of STI3b is 50 nm, and the intrinsic stress of STI3a, 3b and STI52 of the conventional semiconductor device 50 is 200 MPa. Then, when the element isolation region width was 0.1, 0.3, 1.0, and 10 μm, the compressive stress in the gate width direction of the channel portion was calculated. When the element isolation region width is 0.1 lzm, the conventional semiconductor device 50 and the semiconductor device 1 of the first embodiment are the same.

 [0032] From FIG. 6, in the semiconductor device 1 of the first embodiment, as the width of the element isolation region is increased, the effect of suppressing the compressive stress is increased as compared with the conventional semiconductor device 50. I understand. As a result, it was found that the effect of suppressing the compressive stress can be obtained even if the other part of the element isolation region 3 is the STI3b as shown in FIGS.

[0033] As described above, according to the semiconductor device 1 of the first embodiment, the active region (channel The compressive stress in the region can be reduced, and the on-current of the MOS transistor can be prevented from decreasing.

 Next, two embodiments of the manufacturing method for manufacturing the semiconductor device 1 as shown in FIG. 1 will be described.

 FIG. 7 to FIG. 9 are cross-sectional views of main parts of the semiconductor device in one process of the first manufacturing method for manufacturing the semiconductor device of the first embodiment.

 First, a SiN (silicon nitride) film 13a is deposited on the silicon substrate 10 to a thickness of, for example, lOOnm, and a resist (not shown) is applied. Then, in order to form the element isolation region 3 that separates the active regions 2 from each other, first, a resist opening is formed using a photomask in a region that contacts the active region 2 in the element isolation region 3 to be formed. . Then, after etching the SiN film 13a and removing the resist, the silicon substrate 10 is etched by a depth that allows element separation, for example, 0.3 zm, using the SiN film 13a as a mask. Note that it is desirable to reduce the width of the opening 14 formed at this time as much as possible, and it is desirable to reduce it to the lower limit (the limit of embedding in which an insulator can be embedded) so as to be the smallest STI width in the chip. Specifically, based on the calculation result described above, for example, it is set to 0.1 11 or less (Fig. 7 (8)).

 Next, after silicon on the sidewall of the opening 14 is thermally oxidized, an oxide film 15a is deposited with a thickness of, for example, 600 nm by a CVD (Chemical Vapor D mark osition) method using HDP technology. Subsequently, after annealing, the SiN film 13a is used as a stopper and flattened by the CMP method (Fig. 7 (B)).

 [0037] After the planarization, the SiN film 13a is removed with, for example, a hot sulfuric acid solution, and then immersed in, for example, an HF (hydrogen fluoride) solution so that the surface of the silicon substrate 10 becomes flat. As a result, the STI 3a having a width capable of suppressing the compressive stress shown in FIG. 1 is formed (FIG. 7C).

 Thereafter, a SiN film 13b is again deposited, for example, by lOOnm, a resist (not shown) is applied, and an element isolation region is opened using a photomask. Taking into account misalignment of the photomask, the edge of the photomask used here is the center of the photomask used in the process shown in FIG. After the SiN film 13b is etched and the resist is removed, the silicon substrate 10 is etched by, for example, 50 nm using the SiN film 13b as a mask (FIG. 8A).

[0039] After etching, the oxide film 15b is deposited with a thickness of, for example, 350 nm by the CVD method using HDP technology. Subsequently, after annealing, the SiN film 13b is used as a stopper and planarized by CMP. (Fig. 8 (B)).

 [0040] After planarization, the SiN film 13b is removed with a hot sulfuric acid solution (FIG. 8C).

Further, well implantation and channel implantation are performed, and after the surface of the silicon substrate 10 is pretreated, gate oxidation is performed to form a gate insulating film 11. The film thickness of the gate insulating film 11 is, for example, 2. Onm. After forming the gate insulating film 11, for example, polysilicon of lOOnm is deposited on the gate insulating film 11 to form the gate ₁₂ . Through the above process, as shown in Figure 1,

A semiconductor device 1 having an element isolation region 3 by STIs 3a and 3b is formed (FIG. 9A).

[0041] Although the cross-sectional view illustrating the following steps is a cross-sectional view taken along line BB in FIG. 2, the gate 12 is processed so that the gate length is, for example, 50 nm (FIG. 9). (B)) After forming the diffusion layer 16 of the source drain extension and forming the sidewalls 17, the diffusion layer 18 of the source drain is formed (FIG. 9C).

As described above, the force S for manufacturing the semiconductor device 1 according to the first embodiment as shown in FIGS. 1 and 2 can be obtained.

 Next, a second embodiment of the method for manufacturing the semiconductor device 1 will be described.

FIG. 10 is a fragmentary cross-sectional view of the semiconductor device in one step of the second manufacturing method for manufacturing the semiconductor device of the first embodiment.

 As in the first manufacturing method, a SiN film 13c is deposited on the silicon substrate 10 to a thickness of, for example, lOOnm, and a resist (not shown) is applied. Then, unlike the first manufacturing method, an opening corresponding to the element isolation region to be formed is made using a photomask, and the SiN film 13c is etched. Further, after removing the resist, the silicon substrate 10 is etched by a depth capable of element isolation, for example, 300 nm using the SiN film 13c as a mask to form a trench 19 (FIG. 10A).

 Subsequently, after the silicon sidewall in the trench 19 formed by etching is thermally oxidized, the oxide film 15c is deposited with a thickness of, for example, 50 nm by the CVD method using the HDP technique. Thereafter, anisotropic etching of the oxide film 15c is performed so that the oxide film 15c remains on the side wall of the trench 19 (FIG. 10B).

Further, the silicon surface inside the trench 19 is selectively grown, for example, by 250 nm. Here, the depth force from the surface of the silicon substrate 10 is embedded with an insulator. Thus, the substrate is grown to a depth that can suppress the parasitic capacitance between the gate and the silicon substrate 10 (FIG. Io (c)).

 [0046] A technique for epitaxially growing the inside of the trench after thermally oxidizing the sidewall of the trench and removing the oxide film at the bottom of the trench is disclosed in, for example, Japanese Patent Laid-Open No. 10-144780 (however, in this case, the epitaxial The grown part is the active region.)

 The following steps are the same as the steps from FIG. 8B of the first manufacturing method, and by forming an oxide film 15b in the trench 19, for example, as shown in FIG. It is possible to form the element isolation region 3 composed of STI3a having a narrow width of lzm or less and STI3b having a depth capable of suppressing the parasitic capacitance between the gate shallower than STI3a and the silicon substrate 10.

 [0048] In the first manufacturing method described above, the lithographic process is required twice, and the force S, which required high alignment accuracy in the steps of Fig. 7 (A) and Fig. 8 (A), is as described above. In the second manufacturing method, the lithographic process can be reduced once. In addition, since the STI width in contact with the active region is determined by the thickness of the CVD film, the STI width can be made narrower, and a high compressive stress suppression effect can be expected.

 Next, a semiconductor device according to a second embodiment will be described.

 FIG. 11 is a plan view of the semiconductor device according to the second embodiment.

 The same components as those of the semiconductor device 1 of the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted.

 The semiconductor device 40 of the second embodiment has a configuration in which an nMOS transistor is formed in the active region 2a and a pMOS transistor is formed in the active region 2b. In the semiconductor device 40, in the element isolation region 3, a region located in the gate length direction of the pMOS transistor is an STI 3c formed with a sufficient depth (eg, 0.3 zm) for element isolation. Note that the periphery of the active region 2a where the nM0S transistor is formed and the element isolation region 3 in the gate width direction of the pMOS transistor are narrow, as in the semiconductor device 1 of the first embodiment. It has a two-layer structure of STI3a and shallower STI3b.

[0051] In this way, by making the isolation region 3 in the gate length direction of the pMOS transistor the STI3a and the deep STI3c as in the conventional case, the compressive stress in this direction becomes stronger and the on-current of the pMOS transistor increases. be able to. [0052] The above merely illustrates the principle of the present invention. In addition, many variations and modifications are possible to those skilled in the art, and the invention is not limited to the precise configuration and application shown and described above, but all corresponding variations and equivalents are It is regarded as the scope of the present invention by the claims and their equivalents.

 Explanation of symbols

[0053] 1 Semiconductor Device

 2 Active region

 3 Element isolation region

 3a, 3b STI (trench region)

 10 Silicon substrate

 11 Gate insulation film

Claims

The scope of the claims  [1] In a semiconductor device in which a plurality of electrically active regions formed on a semiconductor substrate are electrically isolated by an element isolation region by a trench in which an insulator is loaded,  A semiconductor device characterized in that a trench region formed with a width capable of suppressing compressive stress in the electrically active region is provided in a region in contact with the electrically active region in the element isolation region.  [2] The semiconductor device according to [1], wherein the width is 0.1 μm or less.  [3] The semiconductor device according to [1], wherein the trench region is formed to a depth that allows element isolation. [4] Parasitic capacitance formed by filling the element isolation region with an insulating material at a depth shallower than the trench region and capable of suppressing parasitic capacitance between the gate and the substrate when forming the MOS transistor 2. The semiconductor device according to claim 1, further comprising a trench region for suppression. [5] Of the element isolation regions, the other trench regions located in the gate length direction of the p-channel MOS transistor formed in the electrically active region are formed with a depth capable of element isolation. 2. The semiconductor device according to claim 1, wherein: [6] In the element isolation region formed in the method of manufacturing a semiconductor device in which a plurality of electrically active regions formed on the semiconductor substrate are electrically isolated by an element isolation region by a trench embedded with an insulator And forming a first trench region having a width capable of suppressing compressive stress in the electrically active region in a region in contact with the electrically active region to be formed;  A second trench region having a depth shallower than the depth of the first trench region and a depth capable of suppressing parasitic capacitance between the gate and the substrate when forming the MOS transistor is formed in the element isolation region. Process,  A method for manufacturing a semiconductor device, comprising: [7] The width of the first trench region is 0.1 _β m or less. 7. A method for manufacturing a semiconductor device according to item 6. [8] The method for manufacturing a semiconductor device according to [6], wherein the first trench region is formed with a depth allowing element isolation. [9] In a method for manufacturing a semiconductor device, in which a plurality of electrically active regions formed on a semiconductor substrate are electrically isolated by an element isolation region by a trench embedded with an insulator. Forming a trench;  Forming an insulating film having a predetermined thickness on the sidewall of the trench;  Selectively epitaxially growing the bottom of the trench such that the depth from the surface of the semiconductor substrate is a predetermined depth;  A step of placing an insulator inside the trench;  A method for manufacturing a semiconductor device, comprising: 10. The method for manufacturing a semiconductor device according to claim 9, wherein the predetermined film thickness is 0.1 μm or less. [11] The trench according to claim 1, wherein the trench is formed to a depth that allows element isolation. 10. A method for manufacturing a semiconductor device according to item 9. 12. The predetermined depth is a depth capable of suppressing parasitic capacitance between the gate and the substrate in forming the MOS transistor by embedding the insulator. The manufacturing method of the semiconductor device of description. [13] a semiconductor substrate;  An active region isolated on the semiconductor substrate;  A gate electrode formed on the active region via a gate insulating film;  A groove surrounding the active region and having a step at the bottom;  An insulating film for carrying the groove;  A semiconductor device.