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WO2006062195A1 - Substrat de boîtier de semiconducteur - Google Patents

Substrat de boîtier de semiconducteur Download PDF

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Publication number
WO2006062195A1
WO2006062195A1 PCT/JP2005/022678 JP2005022678W WO2006062195A1 WO 2006062195 A1 WO2006062195 A1 WO 2006062195A1 JP 2005022678 W JP2005022678 W JP 2005022678W WO 2006062195 A1 WO2006062195 A1 WO 2006062195A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring pattern
semiconductor
semiconductor chip
semiconductor mounting
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2005/022678
Other languages
English (en)
Japanese (ja)
Inventor
Masahito Kawabata
Yoshihito Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006546774A priority Critical patent/JPWO2006062195A1/ja
Publication of WO2006062195A1 publication Critical patent/WO2006062195A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10W74/012—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H10W70/65—
    • H10W72/30—
    • H10W74/15—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H10W72/01225—
    • H10W72/073—
    • H10W72/07338—
    • H10W72/856—
    • H10W72/90—
    • H10W72/923—
    • H10W72/9415—
    • H10W90/724—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor mounting board, and more particularly to a wiring pattern of a printed wiring board on which a semiconductor chip is mounted.
  • Flip chip mounting is a method in which a semiconductor chip is mounted face-down on a substrate wiring pattern while being in a bare state.
  • the electrode arrangement of this semiconductor chip is mostly the one that has one or two peripheral arrangements on the outer periphery (all four sides are arranged), but solid-state imaging devices, RAM 'ROM, etc. Some are arranged only on the two opposite sides, or in a U-shape.
  • the mounting substrate 300 has only a wiring pattern 301 that constitutes the electrode wiring, and no pattern exists in a region where no electrode is formed on the semiconductor chip side.
  • Patent Document 1 In order to avoid this problem, for example, when mounting a solid-state imaging device with electrodes arranged on only two sides, there is no electrode !, and dummy wiring is placed parallel to the chip end face at the part (Patent Document 1) Has been proposed.
  • the substrate 400 is parallel to the end face of the semiconductor other than the wiring pattern 401 constituting the electrode wiring provided to face the electrode pad of the semiconductor chip.
  • a dummy wiring pattern 403 is provided.
  • the sheet-like or paste-like sealing resin 405 is first supplied onto the mounting substrate 400, and then the semiconductor chip 404 is mounted by the thermocompression bonding method. Done in a way ing.
  • a dummy pattern is continuously formed along the side where the electrode pad is not formed, and the temperature of the resin at the time of thermocompression is transmitted through the dummy wiring pattern 403 to dissipate heat. Since the dummy wiring portion having good heat conduction is heated to a high temperature and the resin is cured at the peripheral edge of the opening 402, it is still difficult to form the resin on the end face of the semiconductor chip 404.
  • Patent Document 1 Japanese Patent No. 3207319
  • the dummy wiring restricts the mounting conditions, and it is difficult to realize a high-quality semiconductor mounting structure.
  • the present invention has been made in view of the above circumstances, and eliminates restrictions on mounting conditions, and can efficiently perform bonding and grease sealing, and realize a semiconductor mounting substrate that realizes a high-quality semiconductor mounting structure
  • the purpose is to do.
  • the semiconductor mounting substrate of the present invention has a bare semiconductor chip mounted on the face down.
  • a dummy wiring pattern provided so as to form an angle of
  • the resin sealing around the entire circumference of the semiconductor chip can be realized uniformly, and a high-quality semiconductor mounting structure can be realized.
  • to make a predetermined angle with respect to the side of the semiconductor chip means to form a dummy wiring pattern so as not to be parallel to the side. Desirably, the shape is orthogonal to the side.
  • there is a dummy wiring pattern peripheral area that is, an area without a dummy wiring pattern.
  • the dummy wiring pattern has a uniform height, and the area between both sides of the dummy wiring pattern and the semiconductor chip.
  • the temperature of the resin is prevented from lowering through the wiring pattern during thermocompression bonding, and the high power S of the resin is efficiently realized at the periphery of the semiconductor chip.
  • the resin temperature decreases due to heat radiation by the dummy wiring pattern in the area along the dummy wiring pattern, and as a result, sufficient sealing strength is obtained. I can't do it.
  • the semiconductor mounting substrate of the present invention includes a substrate in which the dummy wiring pattern is provided in a direction symmetrical to the wiring pattern.
  • the semiconductor mounting substrate of the present invention includes a substrate in which the dummy wiring pattern is formed in the same process as the wiring pattern.
  • the semiconductor chip has an electrode arrangement portion on two opposite sides, and the dummy wiring pattern is in a central portion of two sides excluding the two sides. Including those provided.
  • the semiconductor chip is provided with electrode arrangement portions on three sides so that the U-shape is formed, and the dummy wiring pattern has substantially the remaining one side. Including the one provided in the center.
  • the sealing resin crawls up to the end face of the semiconductor chip, which is the least likely to crawl up. Therefore, a high-quality semiconductor mounting structure can be realized. And when mounting is done by thermocompression bonding, the heat conduction is the highest! ⁇ Since the heat escape from the substrate wiring can be minimized, the heating temperature of the semiconductor chip can be set low, the thermal stress on the semiconductor chip can be reduced, and the semiconductor mounting structure can be realized with little thermal distortion.
  • the wiring pattern of the substrate facing the non-electrode placement portion of the semiconductor chip is a substrate on which a bare semiconductor chip is flip-chip mounted face down. There are a plurality of non-electrode arrangement sides.
  • the semiconductor mounting board of the present invention includes one in which a plurality of the dummy wiring patterns are provided on each side.
  • the semiconductor mounting substrate of the present invention includes one in which only one dummy wiring pattern is provided at the center of each side. The invention's effect
  • the sealing resin when the semiconductor mounting is performed using the sealing resin, the sealing resin is the largest.
  • the heat escape of the substrate wiring force having the highest heat conduction can be suppressed to the minimum.
  • the chip's heating temperature can be set low, so that it is possible to reduce the thermal stress on the semiconductor chip and realize a V and semiconductor mounting structure with less thermal distortion.
  • FIG. 1 is a top view and a sectional view of a semiconductor mounting showing a first embodiment of the present invention.
  • FIG. 2 is a mounting process sectional view showing the first embodiment of the present invention.
  • FIG. 3 is a top view of a substrate showing a second embodiment of the present invention.
  • FIG. 4 is a mounting process cross-sectional view showing a second embodiment of the present invention.
  • FIG. 5 is a top view of a substrate in the prior art.
  • FIG. 6 is a sectional view of a mounting process in the prior art.
  • FIG. 7 is a top view of a substrate showing the case of Patent Document 1 in the prior art.
  • FIG. 8 is a mounting process sectional view showing the case of Patent Document 1 in the prior art.
  • FIG. 1 shows an explanatory view of a main part of the semiconductor mounting substrate according to the first embodiment.
  • This semiconductor mounting substrate is provided with a wiring pattern 101 facing the electrode pad 106 placement portion of the semiconductor chip 104 on the substrate 100 on which the bare semiconductor chip 104 is flip-chip mounted face down, and the semiconductor chip 104 is not mounted.
  • the electrode arrangement portion is also provided with a dummy wiring pattern 103 having a patterning force equivalent to that of the wiring pattern 101, that is, a pattern having the same shape as the wiring pattern perpendicular to each side and formed in the same process. .
  • the dummy wiring pattern 103 is in a floating state without being electrically connected to either the semiconductor chip or the external terminal.
  • the semiconductor chip 104 has electrodes arranged on two sides opposite to each other in a force B shape, and the semiconductor mounting substrate has a non-electrode arrangement side on a non-electrode arrangement side of the semiconductor chip 104. It is located at the center of the area facing the part, and only one dummy wiring pattern 10 3 is arranged.
  • the semiconductor mounting substrate 100 is made of an organic resin base (glass epoxy, aramid epoxy, BT resin, polyimide, liquid crystal polymer, etc.) or an inorganic material base (glass, ceramic, etc.).
  • the wiring pattern 101 that forms the wiring electrode is rolled or electrolytically plated with Cu and Ni and Au plated on the surface (electrolytic or electroless), and the wiring height is 20 ⁇ 80 / ⁇ ⁇ .
  • the semiconductor mounting substrate 100 is provided with an opening 102 for hollow mounting. Needless to say, the present invention can be applied to a flat semiconductor mounting substrate without forming the opening 102.
  • the dummy wiring pattern 103 provided on the non-electrode placement side of the semiconductor chip 104 has the same specifications as the wiring pattern 101 constituting the wiring electrode (wiring material configuration, wiring thickness, wiring Width, surface contact method, etc.).
  • the substrate 400 has a wiring pattern constituting the wiring electrode. If the method of providing the dummy wiring pattern 403 so as to be parallel to the end face of the semiconductor chip other than the semiconductor 401 is taken, there is a difference.
  • the semiconductor chip 104 is made of Si, SiC, GaAs, etc., and has a thickness of 0.1 to 0.7 mm.
  • the electrode pad 106 of the semiconductor chip 104 is made of Au, Cu, Ni, or the like.
  • the electrode formation method is a plating method (electrolysis or electroless), and the height is 5 to 20 / ⁇ ⁇ .
  • the semiconductor chip 104 is sealed with a sealing resin 105 when mounted on the semiconductor mounting substrate 100.
  • the sealing ⁇ 105, epoxy, imide, silicone, are based on acrylic, form supplies ⁇ is pasty also properly the viscosity from 20 to 150? & '3 is ⁇ stage I spoon It is a film.
  • the conditions for thermocompression bonding of the semiconductor chip 104 are pressure bonding for 2 to 20 seconds with 100 to 250 ° C. as the peak of the resin temperature.
  • FIG. 2 shows a flow chart of the semiconductor chip mounting process with this electrode arrangement.
  • a flow of mounting the semiconductor chip 104 on which the electrode pads 106 for connection are formed on the semiconductor mounting substrate 100 in which the wiring pattern 101 is provided and the dummy wiring pattern 103 is provided on the side where no electrode pad exists is shown. .
  • the sealing resin 105 is supplied in advance to the semiconductor mounting substrate 100, and the sealing resin 105 has a height depending on the presence or absence of the wiring pattern 101 and the dummy wiring pattern 103. There are irregularities in The height unevenness is in accordance with the wiring pattern 101 and the dummy wiring pattern 103, and corresponds to an electrode height of 20 to 80 / ⁇ ⁇ .
  • the sealing resin 105 is supplied so that the thickness of the resin is 30 to: LOO / z m and is equivalent to the sum of the electrode heights.
  • the semiconductor chip 104 is mounted on the semiconductor mounting substrate 100 (FIG. 2 (a)) and mounted by a thermocompression bonding method (FIG. 2 (b)).
  • the sealing resin 105 does not wet the semiconductor chip 104 by the recess, but the dummy wiring pattern is interposed between the wiring patterns 101. Since 103 is provided, the portion has a convex surface of the grease, wets the semiconductor chip 104, and then wets and spreads to cover the entire end face of the semiconductor chip 104.
  • FIG. 3 is an explanatory diagram of a main part of the semiconductor device of the second embodiment.
  • the semiconductor chip 202 has a two-letter electrode arrangement, and a dummy wiring pattern formed on the semiconductor mounting substrate 200 facing the non-electrode arrangement side in the same process as the wiring pattern 201.
  • Three 203 are provided on each non-electrode arrangement side.
  • the vertical distance D of the wiring pattern 201 is equally divided by the plurality of dummy wiring patterns 203.
  • the number of dummy wiring patterns 203 to be arranged is set to the minimum number necessary to make the wet-up of the sealing resin uniform on the chip.
  • FIG. 4 shows a flow chart of a semiconductor chip mounting process with this electrode arrangement.
  • a flow of mounting the semiconductor chip 204 on which the electrode pad 206 is formed on the semiconductor mounting board 200 having the wiring pattern 201 in which the electrode pad 206 is not present and a plurality of dummy wiring patterns 203 are provided in the part is shown. .
  • the substrate 200 is supplied with sealing resin 205, and the sealing resin 205 can be uneven depending on the presence or absence of the wiring pattern 201.
  • the unevenness of the height is the wiring pattern 201, the dummy ridge line pattern 203, and the electrode height is 20-80 ⁇ m.
  • the sealing resin 205 has a thickness of 30 to: LOO / zm, and is supplied in the equivalent of the electrode height.
  • the semiconductor chip 204 is mounted on the semiconductor mounting substrate 200 by a thermocompression bonding method.
  • the sealing 205 does not wet the semiconductor chip 204 by the recess, but a plurality of dummy wiring patterns 203 are provided between the wiring patterns 201. Therefore, the portion has a convex surface of the grease, wets the semiconductor chip 204, then spreads wet, and covers the entire end face of the semiconductor chip 204.
  • the dummy wiring pattern and the wiring pattern are preferably formed so as to be symmetric, but the direction may be symmetric only in the direction. In other words, it is desirable that the side on which the dummy wiring pattern is formed and the side on which the wiring pattern is formed are symmetrical.
  • the semiconductor mounting substrate of the present invention has a uniform semiconductor electrode arrangement, and has improved the mounting and sealing quality of all semiconductor chips. Especially when the electrodes are arranged only on two sides. It is effective for use in memory chips such as solid-state image sensors and RAM 'ROM. In addition, since it can be mounted reliably and stably, it can be used for semiconductor packages such as SIP (System in Package) that require stacking. Furthermore, it is effective for the purpose of evenly sealing the resin even on a semiconductor chip having a small number of electrodes, such as a high-frequency module component or an optical module component.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne l'application uniforme d’un scellement par résine et l'obtention d’un boîtier flip-chip haute fiabilité en effectuant un câblage identique à un câblage d’électrode pour une section de disposition non-électrode d’un substrat de boîtier de semi-conducteur. Sur le substrat de boîtier (100), un motif de câblage leurre (103) de même spécification que celle d’un motif de câblage (101) constituant le câblage d’électrode existe en une partie centrale d’un côté sur lequel ne figure aucune pastille d’électrode (106) de la puce de semi-conducteur. Ainsi, le non-mouillage d’une résine de scellement (105) est évité et le scellement réalisé de façon sûre en favorisant l’accumulation de la résine de scellement sur les plans d’arête d’une puce de semiconducteur (104).
PCT/JP2005/022678 2004-12-09 2005-12-09 Substrat de boîtier de semiconducteur Ceased WO2006062195A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006546774A JPWO2006062195A1 (ja) 2004-12-09 2005-12-09 半導体実装基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004-356689 2004-12-09
JP2004356689 2004-12-09

Publications (1)

Publication Number Publication Date
WO2006062195A1 true WO2006062195A1 (fr) 2006-06-15

Family

ID=36578015

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/022678 Ceased WO2006062195A1 (fr) 2004-12-09 2005-12-09 Substrat de boîtier de semiconducteur

Country Status (2)

Country Link
JP (1) JPWO2006062195A1 (fr)
WO (1) WO2006062195A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016129409A1 (fr) * 2015-02-13 2016-08-18 ソニー株式会社 Élément d'imagerie, procédé de fabrication, et dispositif électronique

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335593A (ja) * 1995-06-08 1996-12-17 Matsushita Electron Corp 半導体装置およびその製造方法
JPH10214857A (ja) * 1997-01-31 1998-08-11 Hitachi Ltd 半導体装置およびその製造方法
JPH11238745A (ja) * 1998-02-23 1999-08-31 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体キャリア
JP2000294896A (ja) * 1998-12-21 2000-10-20 Seiko Epson Corp 回路基板ならびにそれを用いた表示装置および電子機器
JP2001358175A (ja) * 2000-06-16 2001-12-26 Matsushita Electric Ind Co Ltd 電子部品の実装方法及び電子部品実装体

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3207319B2 (ja) * 1993-05-28 2001-09-10 株式会社東芝 光電変換装置及びその製造方法
JP2001250889A (ja) * 2000-03-06 2001-09-14 Matsushita Electric Ind Co Ltd 光素子の実装構造体およびその製造方法
JP2003092382A (ja) * 2001-09-18 2003-03-28 Sony Corp 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335593A (ja) * 1995-06-08 1996-12-17 Matsushita Electron Corp 半導体装置およびその製造方法
JPH10214857A (ja) * 1997-01-31 1998-08-11 Hitachi Ltd 半導体装置およびその製造方法
JPH11238745A (ja) * 1998-02-23 1999-08-31 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体キャリア
JP2000294896A (ja) * 1998-12-21 2000-10-20 Seiko Epson Corp 回路基板ならびにそれを用いた表示装置および電子機器
JP2001358175A (ja) * 2000-06-16 2001-12-26 Matsushita Electric Ind Co Ltd 電子部品の実装方法及び電子部品実装体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016129409A1 (fr) * 2015-02-13 2016-08-18 ソニー株式会社 Élément d'imagerie, procédé de fabrication, et dispositif électronique
US12125860B2 (en) 2015-02-13 2024-10-22 Sony Corporation Image sensor, method of manufacturing the same, and electronic apparatus

Also Published As

Publication number Publication date
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