WO2006054568A1 - Organic semiconductor circuit and method for driving same - Google Patents

Abstract

An organic semiconductor circuit which can suppress changes of switching characteristics of an OFET due to continuous operation, and a method for driving such organic semiconductor circuit are provided. The organic semiconductor circuit is provided with a pair of or a plurality of pairs of organic semiconductor switching elements wherein control lines of the two kinds of organic semiconductor switching elements having different control voltage polarities when a current is carried are commonly connected, and a load connected to the organic semiconductor switching elements. Operation of inverting the polarity of the control voltage applied to the control line before the lapse of a prescribed time are repeated.

Description

 Specification

 Organic semiconductor circuit and driving method thereof

 Technical field

 The present invention relates to an organic semiconductor circuit using an organic field effect transistor (OFET) as an organic semiconductor switching element and a driving method thereof.

 Background art

 [0002] Thin film transistors (TFTs), which are currently used in the field of flat panel displays and made of thin film field effect transistors (FETs), are arranged between a source electrode and a drain electrode separated by a semiconductor forming a channel. This switching is controlled by the voltage applied to the gate electrode. TFT devices that are currently in practical use are made of amorphous silicon (a-Si) or low-temperature polysilicon as the semiconductor, and silicon oxide or silicon nitride is used as the gate insulating layer. In order to produce devices such as flat panel displays based on these technologies, many high-temperature manufacturing processes are required.

 [0003] On the other hand, with the development of flat panel display technology, demands for weight reduction, mechanical flexibility, impact resistance and resource saving of the substrate are increasing. However, plastic board and resin film, which is expected as a substrate that satisfies such requirements, has limitations in the manufacturing process at high temperatures, and it is difficult to process at temperatures exceeding 200 ° C.

 In recent years, organic semiconductor thin film transistors (OTFTs) or organic field effect transistors (OFETs) using organic materials that exhibit semiconductor properties have been studied. Using organic materials makes it possible to fabricate thin-film devices at a lower temperature process than when using conventional a-Si or low-temperature polysilicon, which is necessary for processes using silicon. It is expected that it can be manufactured without using the high-cost equipment.

 [0005] When OFET can be produced without going through a high-temperature treatment step as described above, it becomes easy to use a plastic plate or resin film having mechanical flexibility as a substrate. Or, the feasibility of using paper-like flexible displays, portable information devices, disposable ID tags, etc. will increase.

[0006] Channel carriers in OFET using low molecular organic semiconductors such as pentacene Although mobility is smaller than that of low-temperature polysilicon-based semiconductor layers, it has been reported to be close to that of amorphous silicon-based semiconductors. For example, as described in Non-Patent Document 1, a value of 1 to 3 square cmZV's is obtained.

[0007] Further, as an element using an organic semiconductor, an organic light emitting diode (OLED) is generally known. Much research has been done on materials, structures, manufacturing methods, etc. to extend the life of OLEDs. As one method, there is known a method for extending the life by removing a short circuit due to a sudden failure or an arrangement or a point defect by an AC driving method (for example, see Patent Document 1).

 [0008] When multi-coloring is realized by using OLED as a display element, it is possible to stack OLEDs of each color instead of juxtaposing red, green and blue OLEDs in a plane. (For example, refer nonpatent literature 2). In this way, the emission area of each color OLED can be widened, so that a predetermined luminance can be obtained even if the brightness per unit area is low, and the current density of the material can be lowered without degrading the display quality. it can. This is advantageous when extending the life of the element or increasing the area of the display device. Even when using OLED as a mixed color or single color instead of multi-color display, reducing the current density of the material is advantageous for extending the life of the element (for example, see Patent Document 2).

 Patent Document 1: JP-A-8-180972

 Patent Document 2: Japanese Patent Laid-Open No. 2003-272860

 Patent Document 3: Japanese Patent Laid-Open No. 2004-170487

 Non-patent document 1: C. D. Dimitrakopoulos et al., J. Appl. Phys. 80 (1996), pp. 2501-2508 Non-patent document 2: Z. Shen et al., Science 276 (1997), pp. 2009-2011

 Non-Patent Document 3: DA Bernards et al., Appl. Phys. Lett 84 (2004), pp. 4980-4982 Non-Patent Document 4: Y. Sakamoto et al., J. Am. Chem. Soc. 126 (2004), pp. 8138 -8140 Disclosure of the Invention

 Problems to be solved by the invention

[0009] For example, when an OLED is used as a display element in order to realize a flexible display or the like, an organic field-effect transistor using a silicon TFT as exemplified in Patent Document 1 as a switching element for driving the OLED Organic semiconductor switches such as (OFET) It is preferable to use a ring element. This is expected to be used for flexible substrates that are strong against bending. On the other hand, OFET has a defect that the switching characteristics with respect to the control voltage applied to the gate electrode deteriorate when operated continuously. As shown in a comparative example to be described later, the power that has the power to restore the switching characteristics if the dormant state is continued for a long time without applying a voltage to the gate electrode of OFET. It is often difficult to continue the state for a long time.

 The present invention provides an organic semiconductor circuit capable of solving the problems in continuously operating OFET as described above, and suppressing the deterioration of OFET switching characteristics due to continuous operation, and a driving method thereof. The purpose is to do.

 Means for solving the problem

 [0011] A method for driving an organic semiconductor circuit according to the present invention is a method for driving an organic semiconductor circuit including a load and an organic semiconductor switching element that drives the load, and is applied to control the organic semiconductor switching element. The operation of reversing the polarity of the control voltage to be performed before a predetermined time elapses is characterized.

 [0012] Further, the organic semiconductor circuit according to the present invention is a pair of organic semiconductor circuits in which control lines of two kinds of organic semiconductor switching elements having different control voltage polarities when connected are connected in common. A semiconductor switching element and a load connected to these organic semiconductor switching elements are provided, and the operation of reversing the polarity of the control voltage applied to the control line before a predetermined time elapses is repeated.

 [0013] Preferred embodiments of the organic semiconductor circuit and the driving method thereof according to the present invention will be described later.

 The invention's effect

 [0014] According to the organic semiconductor circuit and the driving method thereof of the present invention, by repeating the operation of inverting the polarity of the control voltage applied to control the organic semiconductor switching element before the predetermined time has elapsed, It is possible to suppress deterioration of the characteristics of the organic semiconductor switching element when the is continuously operated.

 Brief Description of Drawings

FIG. 1 is a circuit for explaining a basic concept of a method for driving an organic semiconductor circuit according to the present invention. FIG.

 FIG. 2 is a circuit diagram of an organic semiconductor circuit according to Embodiment 1 of the present invention.

 FIG. 3A is a timing chart for explaining a method for driving an organic display panel in which a plurality of organic semiconductor circuits of FIG. 2 are arranged two-dimensionally.

 FIG. 3B is a timing chart for explaining a method for driving an organic display panel in which a plurality of organic semiconductor circuits of FIG. 2 are two-dimensionally arranged.

 FIG. 4 is a plan view showing a pixel portion of an organic display panel in which a plurality of organic semiconductor circuits of this embodiment are two-dimensionally arranged.

 FIG. 5 is a view showing a cross-sectional structure along the line VV ′ of FIG.

 FIG. 6 is a circuit diagram of an organic semiconductor circuit according to Embodiment 2 of the present invention.

 7A is a timing chart for explaining a method of driving an organic display panel in which a plurality of organic semiconductor circuits of FIG. 6 are two-dimensionally arranged.

 7B is a timing chart for explaining a method for driving an organic display panel in which a plurality of organic semiconductor circuits in FIG. 6 are two-dimensionally arranged.

 FIG. 8 is a circuit diagram of an organic semiconductor circuit according to Embodiment 3 of the present invention.

 FIG. 9 is a diagram showing a basic concept of a method for driving an organic semiconductor circuit using only one OFET for driving a load as a comparative example.

 FIG. 10 is a circuit diagram showing a specific configuration of a comparative example corresponding to the circuit of FIG.

 FIG. 11 is a graph showing deterioration of switching characteristics of an OFET for driving a load of an organic semiconductor circuit according to a comparative example.

 FIG. 12 is a circuit diagram of an organic semiconductor circuit including a sensor element according to Embodiment 4 of the present invention.

 FIG. 13A is a timing chart for explaining a driving method of an organic sensor array in which a plurality of organic semiconductor circuits of FIG. 12 are two-dimensionally arranged.

 FIG. 13B is a timing chart for explaining a method for driving an organic sensor array in which a plurality of organic semiconductor circuits in FIG. 12 are two-dimensionally arranged.

BEST MODE FOR CARRYING OUT THE INVENTION

In a preferred embodiment of the method for driving an organic semiconductor circuit according to the present invention, the control power The operation of inverting the polarity of the pressure is repeated at regular intervals. In particular, the scanning signal is periodically applied to the organic semiconductor switching element for data writing or data reading, and the operation of inverting the polarity of the control voltage every time that is an integral multiple of the period of the scanning signal is repeated. preferable. That is, the polarity of the control voltage may be reversed every time the scanning signal is input once or a plurality of times. In particular, when the scanning signal cycle is short, when it is difficult to speed up the polarity inversion of the control voltage due to the capacitance and inductive components of the power line and signal line, the scanning signal is input multiple times. It is practically preferable to lower the frequency of polarity inversion by performing polarity inversion every time.

 [0017] Preferably, the organic semiconductor circuit includes a plurality of organic field effect transistors (OFETs) as the organic semiconductor switching elements.

In a preferred embodiment of the organic semiconductor circuit according to the present invention, the two types of organic semiconductor switching elements are connected to a common load. Alternatively, each is connected to a separate load.

 [0019] Further, it is preferable that the load is an organic light emitting device. For example, an organic light emitting diode (OLED) can be used as the organic light emitting element. Furthermore, when two types of organic semiconductor switching elements are connected to a common load, it is preferable that the load is a bipolar organic light emitting element.

[0020] Further, another preferred embodiment of the organic semiconductor circuit according to the present invention includes a sensor element, and the control voltage is applied to the control lines of the two types of organic semiconductor switching elements based on the detection result. Applied.

[0021] An organic display panel according to the present invention is characterized in that a plurality of organic semiconductor circuits including the organic semiconductor switching element and the light emitting element as described above are two-dimensionally arranged to constitute a plurality of pixels. To do.

[0022] Further, the organic sensor array according to the present invention is characterized in that a plurality of organic semiconductor circuits including the organic semiconductor switching elements and sensor elements as described above are arranged one-dimensionally or two-dimensionally.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram for explaining the basic concept of a method for driving an organic semiconductor circuit according to the present invention. It is a road map. This organic semiconductor circuit has a pair of organic semiconductor switching elements OFET1 and OFET2, which are formed by commonly connecting control lines of two types of organic semiconductor switching elements having different control voltage polarities when they become conductive. In other words, OFET1, which is a p-type FET, becomes conductive when a negative control voltage is applied to the control line (gate) lg, and OFET2, which is an n-type FET, has a positive polarity on the control line (gate) 2g. When the control voltage is applied, it becomes conductive.

 [0025] OFET1 and OFET2 control lines (gate electrodes) lg and 2g are connected in common and connected to an input data line 21. For example, when the organic semiconductor circuit constitutes an organic display panel, the signal applied to the input data line 21 corresponds to display data, but corresponds to the control voltage itself of OFET1 and OFET2 in the circuit of FIG.

 The sources 1 s and 2 s of OFET 1 and OFET 2 are commonly connected to the first power supply line 11. The drains Id and 2d of OFET1 and OFET2 are connected to one terminal of the common load 3, and the other terminal of the load 3 is connected to the second power supply line 12.

 [0027] Depending on the polarity of the control voltage applied to the input data line 21, either one of OFET1 and OFET2 becomes conductive and is connected between the first power supply line 11 and the second power supply line 12. Load current flows through load 3. When the control voltage applied to the input data line 21 is positive, OFET2 is turned on to drive the load 3, and OFET1 is turned off. On the other hand, when the control voltage applied to the input data line 21 is negative, OFET1 becomes conductive and drives the load 3, and OFET2 becomes nonconductive. When the control voltage applied to the input data line 21 is zero (0) volts, both OFET1 and OFET2 are in a non-conductive state and no current flows through the load 3.

[0028] As described above, when OFET is operated continuously, the switching characteristics with respect to the voltage applied to the gate electrode deteriorate. This is a phenomenon caused by continuously applying a voltage of the same polarity to OFET, and will be described in detail later with reference to FIG. In the embodiment of the present invention, as described above, a pair of p-type and n-type OFETs 1 and 2 control lines lg and 2g are connected in common, and the operation of inverting the polarity of the control voltage before a predetermined time is repeated. As a result, when one OFET becomes conductive, the other OFET becomes nonconductive and the switching characteristics are restored. As a result, changes in switching characteristics are suppressed. [0029] This action is considered to be caused by the following mechanism. In other words, it is considered that charges are accumulated at the interface between the gate insulator and the semiconductor due to the gate voltage applied during the long-time conduction state. Although the mechanism by which charge is accumulated at the interface between the gate insulator and the semiconductor by applying the gate voltage is not clear, impurities mixed in the organic semiconductor, polar molecules adsorbed on the surface of the gate insulating film, etc. It is thought that the incentive is to generate an electric field in the direction that weakens the electric field generated by the gate voltage by orienting in the direction of the electric field by application of a long period of time or migrating them. In addition, the electric field caused by the charge accumulated at the interface due to the application of the gate voltage for a long time is gradually relaxed to the thermal stable state at room temperature when left for a long time. If an electric field opposite to that generated by the previously applied gate voltage is applied, the relaxation is accelerated. Therefore, by applying a reverse voltage to the OFET gate electrode, the switching characteristics of the OFET can be quickly recovered.

 (Embodiment 1)

 FIG. 2 is a circuit diagram of an organic semiconductor circuit according to Embodiment 1 of the present invention. This organic semiconductor circuit is one example of the basic circuit shown in FIG. 1, and an organic light emitting diode (OLED) is used as the load 3. Similarly to the circuit in Fig. 1, it has p-type OFET1 and n-type OFET2, and their sources Is and 2s are connected to the first power supply line 11 in common! RU The drains Id and 2d of OFET1 and OFET2 are connected to the power sword terminal of OLED3 which is a common load, and the anode terminal of OLED3 is connected to the second power supply line 12.

 The gates lg and 2g of OFET1 and OFET2 are connected in common, and this connection node is connected to the source 5s of the write selection OFET5, the drain 6d of the reset OFET6, and one terminal of the capacitor 4. The other terminal of the capacitor 4 and the source 6s of the reset OFET 6 are connected to the first power supply line 11 together. Reset The gate 6g of OFET6 is connected to the reset line (RES) 23. The drain 5d of the write selection OFET5 is connected to the input data line (DAT) 21, and the gate 5g is connected to the write selection line (SEL) 22.

[0031] The organic semiconductor circuit having such a configuration is driven by the following procedure. First, the first power supply line 11 is set to zero volts (GND level), and the second power supply line 12 has a drive voltage. Apply (positive voltage). Next, the gate voltage is applied to the reset line 23 to make the reset OFET6 conductive. As a result, the electrodes of the capacitor 4 are short-circuited and electric charges are discharged, and the voltage between the electrodes becomes 0 volt (the voltage is reset). Subsequently, a voltage at which the reset OFET 6 becomes non-conductive is applied to the reset line 23 to open the short circuit between the electrodes of the capacitor 4. This results in an open state between the force electrodes where the voltage on capacitor 4 remains at 0 volts.

 Next, a voltage (display data voltage) for driving a load (OLED 3) is applied to the input data line 21. Subsequently, a gate voltage is applied to the write selection line 22 to turn on the write selection OFET5. As a result, a voltage corresponding to the potential difference between the input data line 21 and the first power supply line 11 is applied to the capacitor 4, and the capacitor 4 is charged to that voltage. Next, a voltage at which the write selection OFET5 is turned off is applied to the write selection line 22, and the connection between the capacitor 4 and the input data line 21 is released.

 [0033] The voltage between the electrodes of the capacitor 4 is applied as a control voltage to the gate electrodes lg and 2g of the load driving OFET1 and 2, and according to the polarity, one of the load driving OFET1 and 2 becomes conductive and the other It becomes non-conductive. A load current flows to the OLED 3 connected between the first power supply line 11 and the second power supply line 12 via the load drive OFET that has become conductive, and the OLED 3 emits light. Note that since almost no current flows through the gates of OFET1 and 2, the voltage between the electrodes of capacitor 4 remains even after the write selection OFET5 is turned off and the connection between capacitor 4 and input data line 21 is released. Is maintained with almost no decline. Of course, even if a different voltage is applied to the input data line 21, the voltage of the capacitor 4 is not affected.

 When a plurality of the organic semiconductor circuits in FIG. 2 are arranged in a two-dimensional matrix, an active matrix driving type organic display panel can be configured. Each organic semiconductor circuit (OLED3) corresponds to each pixel. In this case, a common write selection line 22 and a common reset line 23 are wired to each of a plurality of rows constituting the matrix. The write selection line 22 and the reset line 23 are independent for each row, and a voltage signal of a selection level is sequentially applied to the write selection line 22 and the reset line 23 in each row. That is, a reset signal and a scanning signal are periodically applied.

[0035] A common input data line 21 is wired to each of the plurality of columns constituting the matrix. The input data line 21 is independent for each column. A data signal having a level corresponding to whether or not a current is supplied to the OELD 3 of the pixel in each column in the row selected by the scanning signal is applied to each input data line 21. The first power supply line 11 and the second power supply line 12 are common to all rows and columns (that is, all pixels).

 FIGS. 3A and 3B are timing charts for explaining a method of driving an organic display panel in which a plurality of the organic semiconductor circuits of FIG. 2 are two-dimensionally arranged. The only difference between Figure 3A and Figure 3B is that the polarity of the data signal applied to the input data line 21 is reversed. That is, the active level of the data signal is a negative potential in FIG. 3A and a positive potential in FIG. 3B. In either case, the voltage on the first power supply line 11 (power supply 1) is zero volts, and the voltage on the second power supply line 12 (power supply 2) is a positive voltage. FIG. 3A and FIG. 3B both show the operation timing of the n-th row among a plurality of rows constituting the matrix display. First, the operation when the nth row of the matrix display is selected will be described in order with reference to the timing chart of FIG. 3A and FIG.

 [0037] (1) Before the selection of the nth row, that is, until the selection of the (n-1) th row, the voltage of the write selection line 22 and the voltage of the reset line 23 of the nth row are both 0 volts. Yes, the write selection OFET5 and reset OFET6 in Figure 2 are both non-conductive.

 (2) As indicated by RES in FIG. 3A, a negative voltage pulse signal is applied to the reset line 23 at the first timing corresponding to the n-th row. At this time, the applied voltage of the input data line 21 is the same zero volt as the first power supply line 11. Therefore, the reset OFET6 becomes conductive, and the voltage between the electrodes of the capacitor 4 becomes 0 volt.

 [0039] (3) Next, the voltage (RES) of the reset line 23 is returned to 0 volt so that the reset OFET6 is turned off and the data signal (DAT) is applied to the input data line 21. This data signal is the active level (negative potential) for the pixels that drive (light-emit) OELD3 among the pixels in the n-th row. Do not drive OELD3! In pixels, it is zero volts.

(4) After this, with a slight delay, the scanning signal (selection signal SEL) applied to the write selection line 22 becomes the active level (negative potential). As a result, the write selection OFET5 in FIG. 2 becomes conductive, and the voltage corresponding to the potential difference between the first power supply line 11 and the input data line 21 is reached. Capacitor 4 is charged.

 [0041] (5) Return the scanning signal (selection signal SEL) on the write selection line 22 to zero volts and write selection After setting the OFET5 to the non-conductive state, also return the data signal (DAT) on the input data line 21 to the negative voltage. . When the data signal (DAT) is at the active level (negative potential), the voltage charged in the capacitor 4 is maintained until the next scanning timing. During this time, the load driving OFET 1 is kept in a conductive state, and a load current flows through the OLED 3 connected between the first power supply line 11 and the second power supply line 12. That is, the light emission state of the OLED 3 is maintained. At this time, the load driving OFET2 maintains the non-conduction state.

 [0042] The above operation is repeated for the row after the (n + 1) -th power, so that each row is selected in order, and the OLED3 of a plurality of pixels in each row depends on the data signal (DAT). A light emitting state or a non-light emitting state is entered.

 Next, the timing chart of FIG. 3B differs from the timing chart of FIG. 3A only in that the active level of the data signal (DAT) applied to the input data line 21 is not a negative potential but a positive potential. . Therefore, among the operation descriptions with reference to the timing chart of FIG. 3A above, the descriptions of steps (1) to (4) indicate that the active level (negative potential) of the data signal (DAT) is set to the active level (positive potential). )), It can be applied to the timing chart in Fig. 3B. In step (5), in the case of the timing chart of FIG. 3B, the load driving OFET1 maintains the non-conductive state, and the load driving OFET2 maintains the conductive state. Therefore, the load current flows to the OLED 3 through the load driving OFET 2 and the light emission state power of the OLED 3 is maintained.

[0044] As described above, if the operation of inverting the active level of the data signal (DAT) applied to the input data line 21 between the positive potential and the negative potential is repeated, the p-type load driving OFE Either T1 or the n-type load drive OFET2 maintains the conduction state, and the other maintains the non-conduction state. In the case of this embodiment, the active level of the data signal (DAT) is substantially equal to the control voltage of the load driving OFET 1 and 2. Since a reverse voltage is applied to the non-conductive OFET gate, the switching characteristics are restored as described above. Therefore, changes in switching characteristics that occur when OFET, an organic semiconductor switching element, is operated continuously are suppressed. [0045] The operation to invert the polarity of the control voltage (active level of the data signal) must be performed before a predetermined time has elapsed (before deterioration of the switching characteristics becomes large). It is preferable to carry out every predetermined time in synchronization with the above. It is preferable to carry out every time that is an integral multiple of the period of the scanning signal. However, if the multiple is increased, a power of 2 can simplify the circuit configuration for the counting. Of course, if a counter circuit is prepared, the polarity can be inverted every time that is an arbitrary multiple of the scanning signal cycle, for example, 3600 times. Also, for example, the problem of display flickering occurs when polarity inversion is performed every 0.2 seconds, or color unevenness caused by inductive and capacitive components of wiring when polarity inversion is performed at the end of all scanning. If problems such as the occurrence of a problem occur, change the polarity to reverse every few tens of seconds or minutes.

It should be noted that the write selection OFET5 and the reset OFET6 have a very short period during which the control voltage (gate voltage) is applied, so that the deterioration of the switching characteristics as described above hardly poses a problem. Therefore, in this embodiment, the control voltage is inverted for the load driving OFETs 1 and 2 to which the control voltage is applied for a long time! The write selection OFET 5 and the reset OFET 6 to which the control voltage is applied for only a short time. For, the control voltage is not reversed.

 Next, an example of the structure and manufacturing method of the organic semiconductor circuit shown in the circuit diagram of FIG. 2 will be described with reference to FIGS. 4 and 5. Actually, an organic semiconductor circuit is manufactured as a component of the organic display panel as described above. FIG. 4 is a plan view showing a pixel portion of an organic display panel in which a plurality of organic semiconductor circuits of this embodiment are two-dimensionally arranged. FIG. 5 is a diagram showing a cross-sectional structure taken along the line VV ′ of FIG.

In FIG. 4, an OLED that is an organic light-emitting element is arranged at the center of one pixel of the organic display panel so as to occupy a wide rectangular area. Around that, wiring patterns such as the first power line 11, input data line 21, write selection line 22, reset line 23, etc. are arranged, and between these wiring patterns, capacitor 4, write selection OFET5, reset OFET6 etc. are formed!

In the cross-sectional view of FIG. 5, a p-type load driving OFETl, a load OLED3, and an n-type load driving OFET2 are formed on the transparent glass substrate 10 in the order of the left force. OF The ET1 includes a gate lg that is an ITO (indium stannate film) electrode, a gate insulating film lh, a p-type semiconductor lp, and a source Is and a drain Id that are gold electrodes. The OLED 3 has an anode 3a that is an ITO electrode, a hole transport layer 3p that is a p-type semiconductor, an electron transport layer 3n that is an n-type semiconductor, and a force sword 3k that is an aluminum electrode. OFET 2 has a gate 2g as an ITO electrode, a gate insulating film 2h, an n-type semiconductor 2n, a source 2s and a drain 2d as gold electrodes.

 [0050] As can be seen from FIG. 5, the drain Id of OFET1 and the drain 2d of OFET2 are connected to the force sword 3k of the OLED. When OFET1 or OFET2 becomes conductive and current flows through OLED3, the light generated in electron transport layer 3n (light emitting layer) is emitted downward through force sword 3k, which is a transparent electrode, and transparent glass substrate 10. .

 [0051] The organic semiconductor circuit (organic display panel) having the above-described structure is manufactured, for example, by the following process.

 First, an indium stannate film (thickness 150 nm) is formed on the transparent glass substrate 10 and patterned to form ITO electrodes for each OFET and OLED. Subsequently, an oxide film (thickness lOOnm) is formed as an OFET gate insulating film. Furthermore, in order to close the pinhole and reduce the surface roughness, a photosensitive resin thin film (thickness of about 200 nm) should be provided by spin coating.

 Next, as a p-type OFET semiconductor, pentacene is vacuum-deposited to a thickness of 70 nm at a rate of 0.1 nm per second. At this time, the substrate temperature is maintained at about 50 ° C. Furthermore, perfluoropentacene disclosed in Non-Patent Document 4 is deposited as a semiconductor of the load driving OFET 2. The vapor deposition conditions may be the same conditions as pentacene as an example. Subsequently, in order to perform wiring of each OFET, Au is vacuum-deposited so that the film thickness becomes 10 nm at 0.6 nm per second.

 Through the steps so far, the load driving OFETl, the load driving OFET2, the write selection OFET5, and the reset OFET6 are formed. Further, the region where the gates of the load driving OFETs 1 and 2 and the first power supply line 11 are opposed to each other with the gate insulator therebetween is the capacitor 4. Of course, the capacitor 4 can be provided separately.

[0055] OLE D3 as a load is formed on the substrate on which each OFET and capacitor are formed as described above. For this purpose, first, the substrate is left in a vacuum so that the substrate temperature is 30 ° C or lower. Next, as the hole injection layer of OLED3, copper phthalocyanine was added at 0.1 nm per second. Vacuum-deposited to a thickness of 5nm. Further, 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl is vacuum-deposited as a hole transport layer 3p so that the film thickness becomes 60 nm at a rate of 0.1 nm per second. Further, tris (8-hydroxyquinoline) aluminum (Alq3) is vacuum-deposited as an electron transport layer 3n at a thickness of 60 nm at a rate of 0.1 nm per second. This Alq3 also serves as a light emitting layer. Furthermore, as an electron injection layer, LiF is vacuum-deposited to a thickness of 0.6 nm. Furthermore, A1 is vacuum deposited as an electron injection electrode (force sword) 3k. In this way, the organic semiconductor circuit shown in FIGS. 2, 4 and 5 is manufactured.

 (Embodiment 2)

 FIG. 6 is a circuit diagram of an organic semiconductor circuit according to Embodiment 2 of the present invention. This organic semiconductor circuit is obtained by replacing the load 3 in the organic semiconductor circuit of Embodiment 1 shown in FIG. 2 with a bipolar light emitting element. The bipolar light emitting element 3 may be one in which two OLEDs are connected in parallel with opposite polarities as disclosed in Patent Document 3. Alternatively, as disclosed in Non-Patent Document 3, [Ru (4, 4'-di-tert-butyl 2, 2'-bibilidyl)

 Three

It is also possible to use an ambipolar light emitting device having a structure in which a ²⁺ complex is sandwiched between ITO electrodes and gold electrodes. In the organic semiconductor circuit of FIG. 6, circuits other than the ambipolar light-emitting element 3 that is a load can have the same configuration as the organic semiconductor circuit of FIG.

In the organic semiconductor circuit of FIG. 6, the ambipolar light-emitting element 3 emits light regardless of the direction of current flow. Therefore, by repeating the operation of inverting the polarity of the second power supply line 12 before the predetermined time elapses, it is possible to suppress the deterioration of the emission characteristics of the OLED. The timing for reversing the polarity of the second power supply line 12 may be a timing for every fixed period as disclosed in Patent Document 3, or the polarity may be reversed every time that is a multiple of the period. You may rub. In the organic semiconductor circuit of this embodiment, the OFET1 and OFET2 control voltages (that is, the active level of the data signal applied to the input data line 21) are inverted similarly to the organic semiconductor circuit of the first embodiment. In addition to the effect of suppressing the deterioration of the switching characteristics of 1 and OFET2, the effect of suppressing the deterioration of the emission characteristics of the OLED can be obtained by repeating the operation of inverting the polarity of the second power line 12.

[0057] Similar to the organic semiconductor circuit of FIG. 2, the organic semiconductor circuit of FIG. By arranging several, an active matrix driving type organic display panel can be constructed. In the case where a plurality of organic semiconductor circuits of FIG. 6 are arranged in a two-dimensional matrix, unlike the case of the organic semiconductor circuit of FIG. 2, the second power supply line 12 is not common to all the rows. It is preferable to keep them independent. Then, the combination of the polarity of the control voltage (active level of the data signal) of the OFET1 and OFET2 when each row is scanned (selected) and the voltage polarity of the second power supply line 12 can be set arbitrarily. become.

 FIGS. 7A and 7B are timing charts for explaining a method of driving an organic display panel in which a plurality of the organic semiconductor circuits of FIG. 6 are arranged two-dimensionally. These timing charts show the operation timing of the nth row of the plurality of rows constituting the matrix display. The timing chart of FIG. 7A is obtained by inverting the polarity of the second power supply line 12 in the timing chart shown in FIG. 3A, and the other signals are the same. The timing chart in FIG. 7B is obtained by inverting the polarity of the second power supply line 12 in the timing chart shown in FIG. 3B, and the other signals are the same.

 [0059] Driving an organic display panel in which a plurality of organic semiconductor circuits in FIG. 6 are arranged two-dimensionally can be performed by combining the timing charts in FIGS. 3A, 3B, 7A, and 7B. it can. In other words, the operation of inverting the polarity of the control voltage (active level of the data signal) of OFET1 and OFET2 at regular intervals may be combined with the operation of inverting the polarity of the second power supply line 12. Note that the OLED driving method disclosed in Patent Document 3 performs only the operation of inverting the polarity of the second power supply line 12, and is a timing chart of FIGS. 3A and 7A (or FIGS. 3B and 7B). Equivalent to

[0060] In driving an organic display panel in which a plurality of organic semiconductor circuits in FIG. 6 are arranged in two dimensions, the polarity inversion of the second power supply line 12 and the active level of the data signal applied to the input data line 21 are changed. When matching the timing with polarity reversal, the timing chart in FIG. 3A and the timing chart in FIG. 7B may be used alternately. Alternatively, the timing chart of FIG. 3B and the timing chart of FIG. 7A may be used alternately.

[0061] The organic semiconductor circuit of the present embodiment using the bipolar OLED as the load 3 is driven by a load. The polarity of the data signal on the input data line 21 is inverted at a time interval that does not cause significant deterioration of the switching characteristics of the OFET1 for load and OFET2 for load drive, and the second power supply line 12 It may be driven so as to reverse the polarity. Therefore, it is necessary to adopt a driving method that transitions between the timing charts of FIGS. 3A, 3B, 7A, and 7B.

The polarity inversion is preferably performed every time that is an integral multiple of the period of the scanning signal (write selection signal). If the multiple is large, a power of 2 can be used to simplify the circuit configuration for counting. Of course, if a counter circuit is prepared, the polarity can be inverted every time that is an arbitrary multiple of the scanning signal cycle, for example, 3600 times. This multiple may be determined appropriately according to the scanning signal cycle, OFET1 or 2, or the characteristic change rate of the load 3. For example, if the polarity is reversed every 0.2 seconds, the display may flicker, or if polarity is reversed at the end of all scans, color unevenness due to the inductive and capacitive components of the wiring may occur. If problems such as this occur, change the polarity to reverse every tens of seconds or minutes.

Next, an example of a method for manufacturing the organic semiconductor circuit shown in the circuit diagram of FIG. 6 will be described.

 First, each OFET is formed on the transparent glass substrate 10, and then one OLED constituting the bipolar OLED 3 is formed. The steps up to here are the same as those of the example of the method for manufacturing the organic semiconductor circuit shown in the circuit diagram of FIG. Next, the other (reverse polarity connection) OLED constituting the bipolar OLED 3 is formed by the following procedure.

[0064] First, LiF is vacuum-deposited as an electron injection layer on the aluminum electrode of one of the already formed OLEDs so as to have a film thickness of 0.6 nm. Subsequently, tris (8-hydroxyquinoline) aluminum is vacuum-deposited to a film thickness of 60 nm at 0.1 nm per second as an electron transport layer. Further, 4,4′-bis [N- (1-naphthyl) N-ferroamino] bilayer is vacuum-deposited at a thickness of 0.1 nm per second to a film thickness of 60 nm as a hole transport layer. As the hole injection layer, copper phthalocyanine is vacuum-deposited to a thickness of 5 nm at 0.1 nm per second. Finally, Au is vacuum-deposited as a hole injection electrode so that the film thickness is 10 nm at 0.6 nm per second. In this way, the organic semiconductor circuit shown in the circuit diagram of FIG. 6 can be manufactured. (Embodiment 3) FIG. 8 is a circuit diagram of an organic semiconductor circuit according to Embodiment 3 of the present invention. In the organic semiconductor circuits of Embodiments 1 and 2 described above, the drains Id and 2d of OFET1 and OFET2 are connected to the common load OLED3. However, in the organic semiconductor circuit shown in FIG. 8, the drains of OFET1 and OFET2 Id and 2d are connected to separate loads 3A and 3B, respectively. That is, the drain Id of OFET1 is connected to the cathode of OLED3A which is the first load, and the drain 2d of OFET2 is connected to the anode of OLED3B which is the second load. This configuration is a configuration in which the bipolar OLED 3 is separated into two OLEDs in the organic semiconductor circuit shown in FIG. 6, and is substantially the same.

First, a method for manufacturing the organic semiconductor circuit shown in FIG. 8 will be described. On the glass plate (thickness 0.9 mm) provided with the patterned indium stannate film (thickness 150 nm), an oxide film (thickness lOOnm) is provided as the OFET gate insulating film. Furthermore, a photosensitive resin thin film (thickness: about 200 nm) is provided by spin coating in order to close the pinhole and reduce the surface roughness.

 [0066] Next, pentacene as a p-type OFETl, 5, 6 semiconductor is vacuum-deposited at 70 nm per second at 0. Inm. The substrate temperature at this time is 50 ° C. In addition, perfluoropetanecene is vacuum-deposited at a thickness of 70 nm per second as an n-type OFET2 semiconductor. The substrate temperature at this time is 50 ° C. In order to wire each element, lOnm is vacuum-deposited at 0.6 nm per second.

 [0067] The substrate is left in vacuum until the substrate temperature becomes 30 ° C or lower. Sequential connection As the hole injection layer of OLED3B, copper phthalocyanine (abbreviated as CuPc) is vacuum-deposited at a rate of 0. Inm per second for 5 nm. In addition, 4,4'-bis [N- (1-naphthyl) N-phenylamino] biphenyl (abbreviated as NPD) is vacuum-deposited at a rate of 0. Inm and 60 nm as a hole transport layer. Furthermore, tris (8 hydroxyquinoline) aluminum (abbreviated as Alq3) is vacuum-deposited at a rate of 0. Inm per second for 60 nm as an electron transport layer. This Alq3 also serves as a light emitting layer. As an electron injection electrode, Mg and Ag are deposited by lOnm. This electron injection electrode also serves as an electrode for reverse connection OLED3A.

[0068] Reverse connection As an electron transport layer of OLED3A, Alq3 is vacuum-deposited at a rate of 0. Inm per second for 60 nm. This Alq3 also serves as a light emitting layer. Subsequently, NPD is vacuum-deposited at a rate of 0. Inm per second for 60 nm as a hole transport layer. Furthermore, as a hole injection layer, CuPc is vacuum evaporated at 0. Inm per second for 5 nm. Finally, Au is vacuum-deposited at 2 nm by 0.6 nm per second. Then A1 0 Complete the wiring by vacuum deposition at 6nm and 80nm. By performing in 2 X 10- ⁴ Pa For example a series of vacuum deposition as described above, it is possible to manufacture an organic semiconductor circuit shown in FIG. 8

Next, a method for driving the organic semiconductor circuit fabricated as described above will be described in order.

 (1) When a negative voltage is applied as the power supply voltage Vdd and a negative voltage is applied as the reset voltage Vres to the reset signal line, the reset OFET 6 becomes conductive, and the capacitor 4 is discharged. After discharge, when the reset voltage Vres of the reset signal line is set to 0 volt, the reset OFE T6 becomes non-conductive.

 [0071] (2) If a negative voltage is applied as the scanning voltage Vsc, which is the control signal voltage, to the scanning signal line of 0 volt while the power supply voltage Vdd is maintained at a negative voltage, the data signal OFET5 Becomes conductive, the data signal line and the capacitor 4 are connected, and the data Data is recorded in the capacitor 4. Since the write O FET 5 is non-conductive except at the write timing, the data in the capacitor 4 is maintained. Capacitor 4 voltage (referenced to the negative power supply voltage Vdd) is applied to the gate electrode of the driving OFET1 as the organic semiconductor switching element for driving the load, and the driving OFET1 is turned on to reverse the light emitting element. Connect OLED3A is activated and reverse connection OLED3A emits light. By the method (2) above, the scanning voltage Vsc is sequentially applied to the scanning signal lines to perform the sequential scanning.

 (3) When scanning is performed on all the scanning signal lines, the process returns to the first scanning signal line, and the above (2) is repeated a specified number of times.

 [0073] (4) Next, when the polarity of the power supply voltage Vdd is inverted from the negative voltage to the positive voltage and a negative voltage is applied to the reset signal line as the reset voltage Vres, the reset OFET6 becomes conductive and the charge of the capacitor 4 Is discharged. After discharge, when 0V is applied as the reset voltage Vres to the reset signal line, the reset OFET6 becomes non-conductive.

[0074] (5) When a negative voltage is applied as the scanning voltage Vsc, which is the control signal voltage at the write timing, to the scanning signal line of 0 volt while maintaining the power supply voltage Vdd at a positive voltage, the data for writing OFET5 Becomes conductive, the data signal line and the capacitor 4 are connected, and the data Data is recorded in the capacitor 4. O for writing except at writing timing Since FET5 becomes non-conductive, the data of capacitor 4 is maintained. The voltage of the capacitor 4 (positive power supply voltage Vdd reference) is applied to the gate electrode of the driving OFET2 as the organic semiconductor switching element for load driving, and the driving OFET2 is turned on, so that the order of the light emitting element Connect OLED3B is activated and forward connection OLED3B emits light. By the above method (5), the scanning voltage Vsc is sequentially applied to the scanning signal lines to perform the sequential scanning.

 (6) When scanning is performed on all the scanning signal lines, the process returns to the first scanning signal line, and the above (5) is repeated a specified number of times. When the repetition is over, return to (1).

 [0076] In the example of this embodiment, the positive voltage is +30 volts, the negative voltage is -30 volts, the scanning speed is 60 Hz, and the repetition specification described in (3) and (6) The number was 4096 times. Note that the positive voltage and the negative voltage are determined based on the characteristics of the OFET produced in this embodiment, and can be changed as appropriate when different OFETs are used.

[0077] In one embodiment, the number of repetitions is 2 ¹² because the external circuit becomes simple. However, if a counter circuit that does not need to be a power of 2 is prepared, for example, 3600 times or other numbers are possible. is there. The number of repetitions is appropriately determined based on the scanning signal cycle, OFET characteristic change rate, display quality, and the like. For example, there is a problem that the display flickers when polarity inversion is performed every 0.2 seconds, or color unevenness due to inductive and capacitive components of wiring occurs when polarity inversion is performed at the end of all scanning. If problems such as the above occur, the present invention is not limited to these values as long as it is determined that polarity inversion is performed every tens of seconds or every few minutes.

 In the organic semiconductor circuit of each embodiment whose circuit is shown in FIG. 2, FIG. 6, or FIG. 8, a force n-type OFET using many p-type OFETs may be used. In this case, it is apparent that the operation is performed if the polarity of the write selection line 22 and the reset line 23 is appropriately reversed according to the polarity of OFET.

[0079] Also, for the write selection OFET5 and the reset OFET6, p-type or n-type is used alone, and the gate voltage is not inverted. As shown in the timing charts of FIGS. 3A, 3B, 7A, and 7B, these OFETs usually have a shorter period during which the gate voltage is applied than the period during which the gate voltage is not applied. There is no problem with this configuration. However, the load driving OFETs 1 and 2 that drive the load 3 (3A and 3B) Since the gate voltage continues to be applied while the current continues to flow through the load 3, the deterioration of the switching characteristics is suppressed by inverting the gate voltage by combining the p-type and n-type OFET in this way. .

 [0080] Further, the force explaining the configuration in which two OLEDs are stacked as the load 3 (3A and 3B). The arrangement of the two OLEDs is not limited to the lamination, but may be another arrangement form such as juxtaposition. In addition, the multi-layered structure disclosed in Patent Document 2 is not limited to the structure in which the forward OLED and the reverse OLED are stacked one by one.

 [0081] The light emission color of each OLED need not be the same color (for example, green). For example, blue and yellow can be combined to be white. The combination may be three colors, blue, green, and red, with only two colors. In addition to white, it is also possible to combine amber and green to create an amber color. In addition to the configuration in which one color is assigned to one pixel, a multi-color pixel can be configured by stacking or juxtaposing organic semiconductor circuits.

[0082] In the case of an organic semiconductor circuit including the organic light-emitting elements described above, when a plurality of light-emitting elements are individually driven by two types of organic semiconductor switching elements (p-type and _n- type OFET)? In addition, the plurality of light emitting elements are preferably light emitting elements that emit light of the same color. As a result, the lifetime of the organic semiconductor circuit can be extended.

 [0083] Alternatively, in the above case, at least one of the plurality of light emitting elements may have an emission spectrum different from that of the other light emitting elements. For example, when the life of a material exhibiting a desired emission color is short, a desired emission color may be obtained using a plurality of light emitting elements having emission colors with longer lifetimes. When a single organic light-emitting diode is manufactured by mixing dye materials of different emission colors, if the energy transfer rate of the exciton force varies greatly depending on the dye material, the emission color caused by variations in manufacturing, etc. The color variation becomes large and color adjustment is difficult. However, if the light emitting diodes of the respective light emitting materials are individually formed and stacked, the design becomes easy even when the energy transition rate from the exciton varies greatly depending on the dye material.

[0084] Further, a plurality of light emitting elements may be arranged so that light emitted from a plurality of light emitting element forces is guided in different directions, or respective light guiding means may be provided. In this configuration, the light emission colors of the light emitting elements may be the same color or different from each other. Different If the light guided in the direction has a different emission color depending on the direction, for example, the direction of the object (front / back, front / rear, left / right, up / down) can be easily distinguished. Available when you need to do it. Alternatively, it can also be used as a decoration that exhibits a different hue depending on the viewing direction.

 [0085] The arrangement of the plurality of light emitting elements as described above may be juxtaposed or stacked! In particular, as disclosed in Non-Patent Document 2 and Patent Document 2, it is known that even if a plurality of organic light emitting diodes are stacked, light from the lower organic light emitting diodes can be sufficiently extracted to the outside. .

 [0086] In addition to what has been described above, as described in Non-Patent Document 2, it is possible to display multiple colors by independently controlling stacked organic light emitting diodes. It is possible to apply the technology such as the stacked light emitting diode to the organic semiconductor circuit according to the present invention.

 [0087] In Embodiments 1 to 3, the low molecular weight material is used as the organic material for both OFET and OLED. However, even when a part or all of the organic material is composed of an oligomer or a polymer, the present embodiment is used. It is clear that the invention can be applied. The present invention is not limited to the exemplified materials.

 [0088] In the present embodiment, the power provided to the reset line 23 and the reset OFET6 in order to reduce the addition to the power supply when the polarity of the input data is reversed. The circuit is operated without performing the reset operation by omitting these. It is also possible to make it. The drive method and circuit of the present invention are characterized by the OFET drive method for driving the addition regardless of the presence or absence of the reset operation.

 (Comparative example)

In order to more clearly describe the effects of the organic semiconductor circuit and the driving method thereof according to the present invention described in the above embodiments, a description of OFET characteristic deterioration will be added below using a comparative example. First, as a comparative example of the organic semiconductor circuit driving method according to the present invention shown in FIG. 1, the basic concept of the organic semiconductor circuit driving method using only one OFET for driving the load is shown in FIG. The load driving OFETl, the load 3, the first power supply line 11 1, the second power supply line 12, and the input data line 21 in FIG. 9 are the same as the corresponding ones in the circuit diagram of FIG. Unlike the circuit diagram of Figure 1, the circuit diagram of Figure 9 uses a p-type load drive. Only OFET1 is provided. Therefore, the polarity of the control voltage applied to the input data line 21 is not reversed. A specific configuration of such an organic semiconductor circuit is, for example, a circuit as shown in FIG. This circuit corresponds to the circuit of FIG. 2 according to Embodiment 1 of the present invention. This circuit is a circuit that is also known in the prior art. Compared with the circuit in Fig. 2, it can be seen that there is no load driving OFET2 and resetting OFET6.

 The organic semiconductor circuit of FIG. 10 is manufactured as follows, for example. A 200 nm thick thermal oxide film is formed on a silicon substrate, and pentacene is vacuum-deposited at a thickness of 0.1 nm per second and a thickness of 70 nm. The substrate temperature at this time is 50 ° C. On top of that, Au is vacuum-deposited at a thickness of 0.6 nm / second and a thickness of 10 nm as an electrode. Subsequently, in order to form an OLED as the load 3, the substrate is left in a vacuum until the substrate temperature becomes 30 ° C. or lower.

 [0090] As a hole injection layer of the load OLED3, copper phthalocyanine is vacuum evaporated at a thickness of 0.1 nm per second at a thickness of 5 nm. Further, 4,4′-bis [N- (1 naphthyl) -N-phenylamino] biphenyl is vacuum-deposited at a thickness of 0.1 nm per second and a thickness of 60 nm as a hole transport layer. In addition, tris (8-hydroxyquinoline) aluminum is vacuum-deposited at a thickness of 0.1 nm per second as an electron transport layer. LiF is vacuum-deposited with a thickness of 0.6 nm as an electron injection layer. Furthermore, A1 is vacuum-deposited by 10 nm as an electron injection electrode.

 FIG. 11 is a graph showing deterioration in switching characteristics of the load driving OFET of the organic semiconductor circuit according to the comparative example. In the graph of FIG. 11, curve A shows the initial characteristics, curve B shows the deteriorated characteristics after operating for a predetermined time, and curve C shows the characteristics recovered from the characteristics of curve B after a predetermined time rest. Both curves are plots of measured data of the characteristics (switching characteristics) of the source-drain current Ids against the gate voltage Vg of the load driving OFET1 of the organic semiconductor circuit of FIG. 10 fabricated as described above. It is.

[0092] The operating conditions when the deterioration characteristic of curve B is obtained are as follows. That is, apply the input data line 21 [30 bonole, first power line 1 U kon 0 boreor, second power line 12 [30 bonole] to the write selection line 22 as described above (select ) Signal SEL was applied periodically and operated for 6 hours. As described in the operation description of the circuit in FIG. 2, even in the organic semiconductor circuit in FIG. 10, the OFET 5 for writing becomes non-conductive during a period other than a short period in which the scanning (selection) signal SEL is applied, and the capacitor 3 The voltage is maintained. This voltage is the load Since it is continuously applied to the gate lg of the driving OFET1, the load driving OFET1 maintains the conductive state. The conditions for obtaining the recovery characteristics of curve C are as follows. That is, the voltage was not applied to the input data line 21 and the voltage was not applied between the first power supply line 11 and the second power supply line 12 and left for 6 hours.

[0093] As shown in Fig. 11, if the voltage of the same polarity is continuously applied to the load driving OFET1, the characteristic of the source-drain current Ids with respect to the gate voltage Vg (switching characteristic) is Deteriorates significantly to curve B. Also, if the load driving OFET1 is left without applying voltage, the degraded switching characteristics will recover from curve B to curve C. As the load 3 in the circuit of FIG. 11, a bipolar light emitting element is used as in the circuit shown in FIG. 6, or two light emitting elements are connected with opposite polarities as in the circuit shown in FIG. Even if it is used, it has been confirmed that the switching characteristics deteriorate as described above if the voltage of the same polarity is continuously applied to the load driving OFET.

 (Embodiment 4)

 Next, an embodiment in which the organic semiconductor circuit of the present invention and its driving method are applied to a sensor circuit will be described. According to the description of the present embodiment, the organic semiconductor circuit of the present invention and the driving method thereof can be applied to a sensor array including various sensors other than a display panel including a display element as in the above-described embodiments. Will be understood

FIG. 12 is a circuit diagram of an organic semiconductor circuit including a sensor element according to Embodiment 4 of the present invention. This organic semiconductor circuit includes a sensor element S7, sensor voltage dividing resistors S9 and SI0, load driving FETs 1 and 2, a load resistor 3, and a read selection OFET8.

 [0095] A sensor element (hereinafter simply referred to as a sensor) S7 is a sensor whose resistance value changes according to the detection result. For example, pressure sensors using pressure-sensitive rubber known as elastomers mixed with powders such as carbon, photosensors such as phototransistors that utilize the fact that the conductivity of semiconductors changes with light, and conductivity due to adsorption of compounds. The sensor S7 can be a chemical sensor that utilizes the change, a chemical sensor that gives the redox potential of the complex formed by the adsorption of the compound substance to the gate of the FET, and the like.

[0096] The voltage between the first reference power supply line S13 and the second reference power supply line S14 is the sensor S7 and The voltage is divided by the series resistance of the sensor voltage dividing resistor S10 and the sensor voltage dividing resistor S9, and the divided voltage is applied to the gates lg and 2g of the load driving OFET1 and 2. The sensor voltage dividing resistor S10 can be omitted depending on the change characteristic of the resistance value of the sensor S7 in the usage region. In addition, if the change in the resistance value of sensor S7 is too large, a resistance with an appropriate resistance value may be connected in parallel with sensor S7 to adjust the change range.

The organic semiconductor circuit of this embodiment also includes a p-type OFET1 and an n-type OFET2 as load driving OFETs, and their sources Is and 2s are connected to the first power supply line 11 in common. . The drains Id and 2d of OFET1 and OFET2 are connected to one terminal of a load resistor 3, which is a common load, and the other terminal of the load resistor 3 is connected to the second power supply line 12. The gates lg and 2g of OFET1 and OFET2 are commonly connected, and the voltage divided by the sensor S7 and the sensor voltage dividing resistors S9 and S10 is applied to the connection node.

Depending on the polarity of the divided voltage, one of the load driving OFETs 1 and 2 becomes conductive, and the other becomes nonconductive. The value of the resistance between the source and drain of the conductive load driving OFET varies depending on the gate voltage (divided voltage). The voltage between the first power supply line 11 and the second power supply line 12 is divided by the source-drain resistance and the load resistance 3, and the read selection line S25 is scanned (selected) by the divided voltage. Read selection that becomes conductive when the data is read out to the output data line S 24 via OFET8.

In the organic semiconductor circuit of this embodiment, the voltage between the first reference power supply line S13 and the second reference power supply line S14 is inverted every predetermined time (or before the predetermined time elapses). For example, the voltage of the first reference power supply line S 13 is fixed to 0 volts, and the voltage of the second reference power supply line S 14 is inverted between the positive voltage and the negative voltage. As a result, the polarity of the gate voltage (control voltage) of OFET1 and OFET2, which is the voltage divided by sensor S7 and sensor voltage dividing resistors S9 and S10, is reversed, and the one of OFET1 and OFET2 is in the conductive state accordingly. The non-conducting one is replaced. This operation suppresses the deterioration of the switching characteristics of the load driving OFETs 1 and 2 as in the embodiment of the organic semiconductor circuit including the display element described above. [0100] An organic sensor array can be configured by arranging a plurality of the organic semiconductor circuits of FIG. 12 including the sensor S7 in one or two dimensions. Each organic semiconductor circuit (unit sensor circuit) that constitutes the organic sensor array has a voltage corresponding to the detection result (resistance value) of sensor S7 when its read selection line S25 is run (selected). Is output to the output data line S24.

 [0101] When a plurality of unit sensor circuits are arranged in a two-dimensional matrix, a common read selection line S25 is wired to each of a plurality of rows constituting the matrix. The read selection line S25 is independent for each row, and a voltage signal of a selection level is applied to the read selection line S25 in each row in order. That is, the scanning signal is periodically applied.

 [0102] Further, a common output data line S24 is wired to each of the plurality of columns constituting the matrix, and the output data line S24 is independent for each column. The voltage corresponding to the detection result (resistance value) of the unit sensor circuit force sensor S7 of each column in the row selected by the scanning signal is output to the output data line S24 of each column. The first reference power supply line S13, the second reference power supply line S14, the first power supply line 11 and the second power supply line 12 are common to all rows and columns (that is, all unit sensor circuits).

 FIGS. 13A and 13B are timing charts for explaining a method of driving an organic sensor array in which a plurality of the organic semiconductor circuits of FIG. 12 are two-dimensionally arranged. The only difference between Figure 13A and Figure 13B is that the polarity of the voltage applied to the second reference power line S14 is reversed. That is, in FIG. 13A, a negative voltage is applied to the second reference power supply line S14, and in FIG. 13B, a positive voltage is applied to the second reference power supply line S14. Both of these timing charts show the operation timing of the nth row of the plurality of rows constituting the matrix. First, the operation when the nth row of the matrix is selected will be described in order with reference to the timing chart of FIG. 13A and FIG.

 (1) Apply 0 volt to the first power supply line 11 and the first reference power supply line S13, and apply a positive voltage to the second power supply line 12.

[0105] (2) A negative voltage is applied to the second reference power supply line S14. At this time, a negative voltage (divided voltage) corresponding to the resistance value of the sensor S7 is applied to the gates of the load driving OFETs 1 and 2 as a control voltage. Therefore, the p-type load drive OFET1 becomes conductive and the n-type negative The load driving OFET2 is turned off. As a result, the voltage division ratio between the resistance between the source and drain of the load driving OFET 1 and the load resistance 3 changes according to the resistance value of the sensor S7.

 (3) In the operation up to the (n−l) th row, the voltage of the read selection line S25 in the nth row is 0 volt, and the read selection OFET8 is in a non-conductive state.

 [0107] (4) When a negative pulse scan (selection) signal is applied to the read selection line S25 in the operation of the nth row, the read selection OFET8 becomes conductive, and the voltage according to the resistance value of the sensor S7 Is output to the output data line S24.

 (5) When the voltage of the read selection line S25 returns to 0 volts, the read selection OFET8 becomes non-conductive, and the operation of the nth row is completed.

 [0109] The above-described operation is repeated for the row after the (n + 1) -th power, so that each row is selected in turn, and the voltage corresponding to each resistance value of the plurality of sensors S7 in each row is set. It is output to the output data line S24 of each column and read.

 Next, the timing chart of FIG. 13B differs from the timing chart of FIG. 13A only in that the voltage applied to the second reference power supply line S14 is not a negative voltage but a positive voltage. Therefore, in the operation description with reference to the timing chart of FIG. 13A, only step (2) is changed as follows.

 [0111] (2) A positive voltage is applied to the second reference power supply line S14. At this time, a positive voltage (divided voltage) corresponding to the resistance value of the sensor S7 is applied as a control voltage to the gates of the load driving OFETs 1 and 2. Therefore, the n-type load driving OFET2 is turned on and the p-type load driving OFET1 is turned off. As a result, the voltage division ratio between the resistance between the source and drain of the load driving OFET2 and the load resistance 3 changes according to the resistance value of the sensor S7.

[0112] The operation of other steps is the same. Thus, by repeating the operation of the timing chart of FIG. 13A and the operation of the timing chart of FIG. 13 at regular time intervals (or before the predetermined time elapses), the first reference power supply line S 13 and the second reference power line S 13 Inverts the polarity of the voltage between power line S14. As a result, the polarities of the gate voltages (control voltages) of the load driving OFETs 1 and 2 are reversed, and the load driving OFETs 1 and 2 are switched between the conductive state and the non-conductive state. Since a reverse control voltage is applied to the non-conductive OFET gate electrode, recovery of the degraded switching characteristics is facilitated. [0113] The operation of inverting the polarity of the OFET control voltage must be performed before the lapse of a predetermined time (before deterioration of switching characteristics becomes large), but is synchronized with a periodic signal such as a scanning (reading selection) signal. It is preferable to carry out at regular intervals. This is preferably performed every time that is an integral multiple of the cycle of the scanning signal. However, when the multiple is increased, the circuit configuration for counting can be simplified if the multiple is set to a power of two.

 [0114] It should be noted that the read selection OFET8 has a very short period during which the control voltage (gate voltage) is applied, so that the deterioration of the switching characteristics as described above hardly poses a problem. Therefore, in this embodiment, the control voltage is inverted for the load driving OFETs 1 and 2 to which the control voltage is applied for a long time!読 み 出 し Read control OFE T8, where the control voltage is applied for a short time, the control voltage is not inverted. Further, a force n-type OFET using a p-type OFET may be used as the read selection OFET8. In this case, it is apparent that the operation is performed if the polarity of the read selection line S 25 is appropriately inverted according to the polarity of OFET.

 Note that the sensor circuit shown in FIG. 12 is a circuit configuration that is particularly preferable when a relatively high-speed detection operation is performed because a current is always passed through the sensor S7 to make it stable. Further, when the linear sensor sensor array is configured by arranging the unit sensor circuits in one dimension, the read selection OFET8 and the read selection line S25 can be omitted. In this case, it is preferable to reverse the polarity of the control voltages of the load driving OFETs 1 and 2 at regular intervals even when the voltage corresponding to the detection result of the sensor S7 is read continuously or irregularly. In addition, when periodically reading the voltage according to the detection result of the sensor S7, it is preferable to reverse the polarity of the control voltages of the load driving OFETs 1 and 2 every integer multiple of the period.

 It should be noted that the second reference power supply line may be provided independently for each row that is not common to all rows. Then, the scanning of each row is not completed and the polarity of the second reference power supply line is not reversed, but the polarity of the power supply line 12 in the second embodiment is reversed. The polarity inversion of the second reference power line can be sequentially performed.

[0117] In Embodiments 1 to 4 above, the OFET material is pentacene for p-type and p-type for n-type. Forces using fluorpentacene Other materials can be used. For example, oligothiophene or perylenetetracarboxylic acid diimide can be used. In addition, the electrode material can be appropriately changed according to these materials and polarity. In addition to gold, aluminum, magnesium, nickel, etc. can be used. The present invention is not limited to these exemplified OFET materials and electrode materials.

[0118] While the organic semiconductor circuit including the light emitting element and the driving method thereof, the organic semiconductor circuit including the sensor and the driving method thereof have been described above with some embodiments, the present invention is not limited to these embodiments. It is also possible to carry out by appropriately modifying or combining the above. Further, the present invention is not limited to these embodiments, and the present invention can be implemented with an IC tag or the like.

 Industrial applicability

[0119] The organic semiconductor circuit and the driving method thereof according to the present invention are applied to various electronic devices such as a sheet-like display using an organic semiconductor switching element, a sensor array, a portable information device using them, and a wireless IC tag. It can be applied, and the effect of effectively suppressing deterioration of the characteristics of the organic semiconductor switching element can be obtained.

Claims

The scope of the claims  [1] A method for driving an organic semiconductor circuit including a load and an organic semiconductor switching element that drives the load, wherein the polarity of a control voltage applied to control the organic semiconductor switching element is set to a value before a predetermined time has elapsed. A method for driving an organic semiconductor circuit, characterized by repeating the inversion operation.  [2] Repeat the operation of inverting the polarity of the control voltage at regular intervals  The method for driving an organic semiconductor circuit according to claim 1. [3] A scan signal is periodically applied to the organic semiconductor switching element for data writing or reading, and the operation of inverting the polarity of the control voltage is repeated every time that is an integral multiple of the cycle of the scan signal.  The method for driving an organic semiconductor circuit according to claim 2. [4] The organic semiconductor circuit includes a plurality of organic field effect transistors as the organic semiconductor switching element.  The method for driving an organic semiconductor circuit according to claim 1, 2 or 3. [5] One or more pairs of organic semiconductor switching elements formed by connecting the control lines of two types of organic semiconductor switching elements having different polarities to each other when the control voltage is in a conductive state, and switching between these organic semiconductors An organic semiconductor circuit comprising: a load connected to an element; and an operation of reversing the polarity of a control voltage applied to the control line before a predetermined time elapses. [6] The two types of organic semiconductor switching elements are connected to a common load.  The organic semiconductor circuit according to claim 5. [7] The two types of organic semiconductor switching elements are connected to individual loads.  The organic semiconductor circuit according to claim 5. [8] The load is an organic light emitting device  The organic semiconductor circuit according to claim 5, 6 or 7. [9] The load is a bipolar organic light emitting device The organic semiconductor circuit according to claim 5 or 6. [10] A sensor element is provided, and based on the detection result, the control voltage is applied to the control lines of the two types of organic semiconductor switching elements.  The organic semiconductor circuit according to claim 5. [11] An organic display panel, wherein a plurality of organic semiconductor circuits according to claim 8 or 9 are two-dimensionally arranged to constitute a plurality of pixels. [12] An organic sensor array, wherein a plurality of the organic semiconductor circuits according to claim 10 are arranged one-dimensionally or two-dimensionally.